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ubsan: cr16: left shift cannot be represented in type 'int'
[deliverable/binutils-gdb.git] / opcodes / tic54x-opc.c
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5c84d377 1/* Table of opcodes for the Texas Instruments TMS320C54X
b3adc24a 2 Copyright (C) 1999-2020 Free Software Foundation, Inc.
5c84d377
TW		 3 Contributed by Timothy Wall (twall@cygnus.com)
4
9b201bb5
NC		 5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
5c84d377 8 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
5c84d377 11
9b201bb5
NC		 12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
5c84d377
TW		 16
17 You should have received a copy of the GNU General Public License
9b201bb5
NC		 18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
5c84d377 21
c1485d85 22#include "sysdep.h"
6e917903 23#include "dis-asm.h"
5c84d377
TW		 24#include "opcode/tic54x.h"
25
26/* these are the only register names not found in mmregs */
3d207518 27const tic54x_symbol regs[] = {
5bd67f35
AJ		 28 { "AR0", 16 }, { "ar0", 16 },
29 { "AR1", 17 }, { "ar1", 17 },
30 { "AR2", 18 }, { "ar2", 18 },
31 { "AR3", 19 }, { "ar3", 19 },
32 { "AR4", 20 }, { "ar4", 20 },
33 { "AR5", 21 }, { "ar5", 21 },
34 { "AR6", 22 }, { "ar6", 22 },
35 { "AR7", 23 }, { "ar7", 23 },
36 { NULL, 0}
5c84d377
TW		 37};
38
39/* status bits, MM registers, condition codes, etc */
40/* some symbols are only valid for certain chips... */
3d207518 41const tic54x_symbol mmregs[] = {
5bd67f35
AJ		 42 { "IMR", 0 }, { "imr", 0 },
43 { "IFR", 1 }, { "ifr", 1 },
44 { "ST0", 6 }, { "st0", 6 },
45 { "ST1", 7 }, { "st1", 7 },
46 { "AL", 8 }, { "al", 8 },
47 { "AH", 9 }, { "ah", 9 },
48 { "AG", 10 }, { "ag", 10 },
49 { "BL", 11 }, { "bl", 11 },
50 { "BH", 12 }, { "bh", 12 },
51 { "BG", 13 }, { "bg", 13 },
52 { "T", 14 }, { "t", 14 },
53 { "TRN", 15 }, { "trn", 15 },
54 { "AR0", 16 }, { "ar0", 16 },
55 { "AR1", 17 }, { "ar1", 17 },
56 { "AR2", 18 }, { "ar2", 18 },
57 { "AR3", 19 }, { "ar3", 19 },
58 { "AR4", 20 }, { "ar4", 20 },
59 { "AR5", 21 }, { "ar5", 21 },
60 { "AR6", 22 }, { "ar6", 22 },
61 { "AR7", 23 }, { "ar7", 23 },
62 { "SP", 24 }, { "sp", 24 },
63 { "BK", 25 }, { "bk", 25 },
64 { "BRC", 26 }, { "brc", 26 },
65 { "RSA", 27 }, { "rsa", 27 },
66 { "REA", 28 }, { "rea", 28 },
67 { "PMST",29 }, { "pmst",29 },
68 { "XPC", 30 }, { "xpc", 30 }, /* 'c548 only */
69 /* optional peripherals */ /* optional peripherals */
70 { "M1F", 31 }, { "m1f", 31 },
71 { "DRR0",0x20 }, { "drr0",0x20 },
72 { "BDRR0",0x20 }, { "bdrr0",0x20 }, /* 'c543, 545 */
73 { "DXR0",0x21 }, { "dxr0",0x21 },
74 { "BDXR0",0x21 }, { "bdxr0",0x21 }, /* 'c543, 545 */
75 { "SPC0",0x22 }, { "spc0",0x22 },
76 { "BSPC0",0x22 }, { "bspc0",0x22 }, /* 'c543, 545 */
77 { "SPCE0",0x23 }, { "spce0",0x23 },
78 { "BSPCE0",0x23 }, { "bspce0",0x23 }, /* 'c543, 545 */
79 { "TIM", 0x24 }, { "tim", 0x24 },
80 { "PRD", 0x25 }, { "prd", 0x25 },
81 { "TCR", 0x26 }, { "tcr", 0x26 },
82 { "SWWSR",0x28 }, { "swwsr",0x28 },
83 { "BSCR",0x29 }, { "bscr",0x29 },
84 { "HPIC",0x2C }, { "hpic",0x2c },
85 /* 'c541, 'c545 */ /* 'c541, 'c545 */
86 { "DRR1",0x30 }, { "drr1",0x30 },
87 { "DXR1",0x31 }, { "dxr1",0x31 },
88 { "SPC1",0x32 }, { "spc1",0x32 },
89 /* 'c542, 'c543 */ /* 'c542, 'c543 */
90 { "TRCV",0x30 }, { "trcv",0x30 },
91 { "TDXR",0x31 }, { "tdxr",0x31 },
92 { "TSPC",0x32 }, { "tspc",0x32 },
93 { "TCSR",0x33 }, { "tcsr",0x33 },
94 { "TRTA",0x34 }, { "trta",0x34 },
95 { "TRAD",0x35 }, { "trad",0x35 },
96 { "AXR0",0x38 }, { "axr0",0x38 },
97 { "BKX0",0x39 }, { "bkx0",0x39 },
98 { "ARR0",0x3A }, { "arr0",0x3a },
99 { "BKR0",0x3B }, { "bkr0",0x3b },
100 /* 'c545, 'c546, 'c548 */ /* 'c545, 'c546, 'c548 */
101 { "CLKMD",0x58 }, { "clkmd",0x58 },
102 /* 'c548 */ /* 'c548 */
103 { "AXR1",0x3C }, { "axr1",0x3c },
104 { "BKX1",0x3D }, { "bkx1",0x3d },
105 { "ARR1",0x3E }, { "arr1",0x3e },
106 { "BKR1",0x3F }, { "bkr1",0x3f },
107 { "BDRR1",0x40 }, { "bdrr1",0x40 },
108 { "BDXR1",0x41 }, { "bdxr1",0x41 },
109 { "BSPC1",0x42 }, { "bspc1",0x42 },
110 { "BSPCE1",0x43 }, { "bspce1",0x43 },
111 { NULL, 0},
5c84d377
TW		 112};
113
3d207518 114const tic54x_symbol condition_codes[] = {
5c84d377
TW		 115 /* condition codes */
116 { "UNC", 0 }, { "unc", 0 },
117#define CC1 0x40
118#define CCB 0x08
119#define CCEQ 0x05
120#define CCNEQ 0x04
121#define CCLT 0x03
122#define CCLEQ 0x07
123#define CCGT 0x06
124#define CCGEQ 0x02
125#define CCOV 0x70
126#define CCNOV 0x60
127#define CCBIO 0x03
128#define CCNBIO 0x02
129#define CCTC 0x30
130#define CCNTC 0x20
131#define CCC 0x0C
132#define CCNC 0x08
133 { "aeq", CC1|CCEQ }, { "AEQ", CC1|CCEQ },
134 { "aneq", CC1|CCNEQ }, { "ANEQ", CC1|CCNEQ },
135 { "alt", CC1|CCLT }, { "ALT", CC1|CCLT },
136 { "aleq", CC1|CCLEQ }, { "ALEQ", CC1|CCLEQ },
5bd67f35
AJ		 137 { "agt", CC1|CCGT }, { "AGT", CC1|CCGT },
138 { "ageq", CC1|CCGEQ }, { "AGEQ", CC1|CCGEQ },
139 { "aov", CC1|CCOV }, { "AOV", CC1|CCOV },
140 { "anov", CC1|CCNOV }, { "ANOV", CC1|CCNOV },
141 { "beq", CC1|CCB|CCEQ }, { "BEQ", CC1|CCB|CCEQ },
142 { "bneq", CC1|CCB|CCNEQ }, { "BNEQ", CC1|CCB|CCNEQ },
143 { "blt", CC1|CCB|CCLT }, { "BLT", CC1|CCB|CCLT },
144 { "bleq", CC1|CCB|CCLEQ }, { "BLEQ", CC1|CCB|CCLEQ },
145 { "bgt", CC1|CCB|CCGT }, { "BGT", CC1|CCB|CCGT },
146 { "bgeq", CC1|CCB|CCGEQ }, { "BGEQ", CC1|CCB|CCGEQ },
147 { "bov", CC1|CCB|CCOV }, { "BOV", CC1|CCB|CCOV },
148 { "bnov", CC1|CCB|CCNOV }, { "BNOV", CC1|CCB|CCNOV },
149 { "tc", CCTC }, { "TC", CCTC },
150 { "ntc", CCNTC }, { "NTC", CCNTC },
151 { "c", CCC }, { "C", CCC },
152 { "nc", CCNC }, { "NC", CCNC },
153 { "bio", CCBIO }, { "BIO", CCBIO },
154 { "nbio", CCNBIO }, { "NBIO", CCNBIO },
155 { NULL, 0 }
5c84d377
TW		 156};
157
3d207518 158const tic54x_symbol cc2_codes[] = {
5c84d377
TW		 159 { "UNC", 0 }, { "unc", 0 },
160 { "AEQ", 5 }, { "aeq", 5 },
161 { "ANEQ", 4 }, { "aneq", 4 },
162 { "AGT", 6 }, { "agt", 6 },
163 { "ALT", 3 }, { "alt", 3 },
164 { "ALEQ", 7 }, { "aleq", 7 },
165 { "AGEQ", 2 }, { "ageq", 2 },
166 { "BEQ", 13 }, { "beq", 13 },
167 { "BNEQ", 12 },{ "bneq", 12 },
168 { "BGT", 14 }, { "bgt", 14 },
169 { "BLT", 11 }, { "blt", 11 },
170 { "BLEQ", 15 },{ "bleq", 15 },
171 { "BGEQ", 10 },{ "bgeq", 10 },
5bd67f35 172 { NULL, 0 },
5c84d377
TW		 173};
174
3d207518 175const tic54x_symbol cc3_codes[] = {
5c84d377
TW		 176 { "EQ", 0x0000 }, { "eq", 0x0000 },
177 { "LT", 0x0100 }, { "lt", 0x0100 },
178 { "GT", 0x0200 }, { "gt", 0x0200 },
179 { "NEQ", 0x0300 }, { "neq", 0x0300 },
5bd67f35 180 { "0", 0x0000 },
5c84d377
TW		 181 { "1", 0x0100 },
182 { "2", 0x0200 },
183 { "3", 0x0300 },
5bd67f35 184 { "00", 0x0000 },
5c84d377
TW		 185 { "01", 0x0100 },
186 { "10", 0x0200 },
187 { "11", 0x0300 },
5bd67f35 188 { NULL, 0 },
5c84d377
TW		 189};
190
191/* FIXME -- also allow decimal digits */
3d207518 192const tic54x_symbol status_bits[] = {
5c84d377
TW		 193 /* status register 0 */
194 { "TC", 12 }, { "tc", 12 },
195 { "C", 11 }, { "c", 11 },
196 { "OVA", 10 }, { "ova", 10 },
197 { "OVB", 9 }, { "ovb", 9 },
198 /* status register 1 */
199 { "BRAF",15 }, { "braf",15 },
200 { "CPL", 14 }, { "cpl", 14 },
201 { "XF", 13 }, { "xf", 13 },
202 { "HM", 12 }, { "hm", 12 },
203 { "INTM",11 }, { "intm",11 },
204 { "OVM", 9 }, { "ovm", 9 },
205 { "SXM", 8 }, { "sxm", 8 },
206 { "C16", 7 }, { "c16", 7 },
207 { "FRCT", 6 }, { "frct", 6 },
208 { "CMPT", 5 }, { "cmpt", 5 },
5bd67f35 209 { NULL, 0 },
5c84d377
TW		 210};
211
212const char *misc_symbols[] = {
213 "ARP", "arp",
214 "DP", "dp",
215 "ASM", "asm",
216 "TS", "ts",
217 NULL
218};
219
220/* Due to the way instructions are hashed and scanned in
221 gas/config/tc-tic54x.c, all identically-named opcodes must be consecutively
5bd67f35 222 placed
5c84d377
TW		 223
224 Items marked with "PREFER" have been moved prior to a more costly
225 instruction with a similar operand format.
226
227 Mnemonics which can take either a predefined symbol or a memory reference
228 as an argument are arranged so that the more restrictive (predefined
229 symbol) version is checked first (marked "SRC").
230*/
6e917903
TW		 231#define ZPAR 0,{OP_None}
232#define REST 0,0,ZPAR
233#define XREST ZPAR
d3ce72d0 234const insn_template tic54x_unknown_opcode =
6e917903 235 { "???", 1,0,0,0x0000, 0x0000, {0}, 0, REST};
d3ce72d0 236const insn_template tic54x_optab[] = {
5c84d377 237 /* these must precede bc/bcd, cc/ccd to avoid misinterpretation */
6e917903
TW		 238 { "fb", 2,1,1,0xF880, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST},
239 { "fbd", 2,1,1,0xFA80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST},
240 { "fcall", 2,1,1,0xF980, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST},
241 { "fcalld",2,1,1,0xFB80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST},
5c84d377 242
6e917903
TW		 243 { "abdst", 1,2,2,0xE300, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
244 { "abs", 1,1,2,0xF485, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
245 { "add", 1,1,3,0xF400, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
246 { "add", 1,2,3,0xF480, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
247 { "add", 1,2,2,0x0000, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
248 { "add", 1,3,3,0x0400, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST},
249 { "add", 1,3,4,0x3C00, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
250 { "add", 1,3,3,0x9000, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST},/*PREFER*/
5bd67f35 251 { "add", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST},
6e917903
TW		 252 FL_EXT|FL_SMR, 0x0C00, 0xFCE0, XREST},
253 { "add", 1,3,3,0xA000, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
254 { "add", 2,2,4,0xF000, 0xFCF0, {OP_lk,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, 0, REST},
255 { "add", 2,3,4,0xF060, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
256 { "addc", 1,2,2,0x0600, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
257 { "addm", 2,2,2,0x6B00, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, REST},
258 { "adds", 1,2,2,0x0200, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
259 { "and", 1,1,3,0xF080, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},
260 { "and", 1,2,2,0x1800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST },
261 { "and", 2,2,4,0xF030, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
262 { "and", 2,3,4,0xF063, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
263 { "andm", 2,2,2,0x6800, 0xFF00, {OP_lk,OP_Smem}, FL_NR, REST},
264 { "b", 2,1,1,0xF073, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, REST},
265 { "bd", 2,1,1,0xF273, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, REST},
266 { "bacc", 1,1,1,0xF4E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST},
267 { "baccd", 1,1,1,0xF6E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST},
268 { "banz", 2,2,2,0x6C00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_NR, REST},
269 { "banzd", 2,2,2,0x6E00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_DELAY|FL_NR, REST},
5bd67f35 270 { "bc", 2,2,4,0xF800, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
6e917903 271 B_BRANCH|FL_NR, REST},
5c84d377 272 { "bcd", 2,2,4,0xFA00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
6e917903
TW		 273 B_BRANCH|FL_DELAY|FL_NR, REST},
274 { "bit", 1,2,2,0x9600, 0xFF00, {OP_Xmem,OP_BITC}, 0, REST},
275 { "bitf", 2,2,2,0x6100, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, REST},
276 { "bitt", 1,1,1,0x3400, 0xFF00, {OP_Smem}, FL_SMR, REST},
277 { "cala", 1,1,1,0xF4E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST},
278 { "calad", 1,1,1,0xF6E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST},
279 { "call", 2,1,1,0xF074, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, REST},
280 { "calld", 2,1,1,0xF274, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, REST},
5bd67f35 281 { "cc", 2,2,4,0xF900, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
6e917903 282 B_BRANCH|FL_NR, REST},
5c84d377 283 { "ccd", 2,2,4,0xFB00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
6e917903
TW		 284 B_BRANCH|FL_DELAY|FL_NR, REST},
285 { "cmpl", 1,1,2,0xF493, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
286 { "cmpm", 2,2,2,0x6000, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, REST},
287 { "cmpr", 1,2,2,0xF4A8, 0xFCF8, {OP_CC3,OP_ARX}, FL_NR, REST},
288 { "cmps", 1,2,2,0x8E00, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
289 { "dadd", 1,2,3,0x5000, 0xFC00, {OP_Lmem,OP_SRC,OPT|OP_DST}, 0, REST},
290 { "dadst", 1,2,2,0x5A00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
291 { "delay", 1,1,1,0x4D00, 0xFF00, {OP_Smem}, FL_SMR, REST},
292 { "dld", 1,2,2,0x5600, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
293 { "drsub", 1,2,2,0x5800, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST},
294 { "dsadt", 1,2,2,0x5E00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
295 { "dst", 1,2,2,0x4E00, 0xFE00, {OP_SRC1,OP_Lmem}, FL_NR, REST},
296 { "dsub", 1,2,2,0x5400, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST},
297 { "dsubt", 1,2,2,0x5C00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
298 { "estop", 1,0,0,0xF4F0, 0xFFFF, {OP_None}, 0, REST}, /* undocumented */
299 { "exp", 1,1,1,0xF48E, 0xFEFF, {OP_SRC1}, 0, REST},
300 { "fbacc", 1,1,1,0xF4E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST},
301 { "fbaccd",1,1,1,0xF6E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST},
302 { "fcala", 1,1,1,0xF4E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST},
303 { "fcalad",1,1,1,0xF6E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST},
304 { "firs", 2,3,3,0xE000, 0xFF00, {OP_Xmem,OP_Ymem,OP_pmad}, 0, REST},
305 { "frame", 1,1,1,0xEE00, 0xFF00, {OP_k8}, 0, REST},
306 { "fret", 1,0,0,0xF4E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, REST},
307 { "fretd", 1,0,0,0xF6E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, REST},
308 { "frete", 1,0,0,0xF4E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, REST},
309 { "freted",1,0,0,0xF6E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, REST},
310 { "idle", 1,1,1,0xF4E1, 0xFCFF, {OP_123}, FL_NR, REST},
311 { "intr", 1,1,1,0xF7C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, REST},
312 { "ld", 1,2,3,0xF482, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
313 { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OP_DST}, 0, REST},/*SRC*/
5c84d377 314 /* alternate syntax */
6e917903
TW		 315 { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
316 { "ld", 1,2,2,0xE800, 0xFE00, {OP_k8u,OP_DST}, 0, REST},/*SRC*/
317 { "ld", 1,2,2,0xED00, 0xFFE0, {OP_k5,OP_ASM}, 0, REST},/*SRC*/
318 { "ld", 1,2,2,0xF4A0, 0xFFF8, {OP_k3,OP_ARP}, FL_NR, REST},/*SRC*/
319 { "ld", 1,2,2,0xEA00, 0xFE00, {OP_k9,OP_DP}, FL_NR, REST},/*PREFER */
320 { "ld", 1,2,2,0x3000, 0xFF00, {OP_Smem,OP_T}, FL_SMR, REST},/*SRC*/
321 { "ld", 1,2,2,0x4600, 0xFF00, {OP_Smem,OP_DP}, FL_SMR, REST},/*SRC*/
322 { "ld", 1,2,2,0x3200, 0xFF00, {OP_Smem,OP_ASM}, FL_SMR, REST},/*SRC*/
323 { "ld", 1,2,2,0x1000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
324 { "ld", 1,3,3,0x1400, 0xFE00, {OP_Smem,OP_TS,OP_DST}, FL_SMR, REST},
325 { "ld", 1,3,3,0x4400, 0xFE00, {OP_Smem,OP_16,OP_DST}, FL_SMR, REST},
326 { "ld", 1,3,3,0x9400, 0xFE00, {OP_Xmem,OP_SHFT,OP_DST}, 0, REST},/*PREFER*/
5bd67f35 327 { "ld", 2,2,3,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_DST},
6e917903
TW		 328 FL_EXT|FL_SMR, 0x0C40, 0xFEE0, XREST},
329 { "ld", 2,2,3,0xF020, 0xFEF0, {OP_lk,OPT|OP_SHFT,OP_DST}, 0, REST},
330 { "ld", 2,3,3,0xF062, 0xFEFF, {OP_lk,OP_16,OP_DST}, 0, REST},
331 { "ldm", 1,2,2,0x4800, 0xFE00, {OP_MMR,OP_DST}, 0, REST},
332 { "ldr", 1,2,2,0x1600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
333 { "ldu", 1,2,2,0x1200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
334 { "ldx", 2,3,3,0xF062, 0xFEFF, {OP_xpmad_ms7,OP_16,OP_DST}, FL_FAR, REST},/*pseudo-op*/
335 { "lms", 1,2,2,0xE100, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
336 { "ltd", 1,1,1,0x4C00, 0xFF00, {OP_Smem}, FL_SMR, REST},
337 { "mac", 1,2,2,0x2800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
338 { "mac", 1,3,4,0xB000, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
339 { "mac", 2,2,3,0xF067, 0xFCFF, {OP_lk,OP_SRC,OPT|OP_DST}, 0, REST},
340 { "mac", 2,3,4,0x6400, 0xFC00, {OP_Smem,OP_lk,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
341 { "macr", 1,2,2,0x2A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
342 { "macr", 1,3,4,0xB400, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST},FL_SMR, REST},
343 { "maca", 1,2,3,0xF488, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, REST},/*SRC*/
344 { "maca", 1,1,2,0x3500, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
345 { "macar", 1,2,3,0xF489, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, REST},/*SRC*/
346 { "macar", 1,1,2,0x3700, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
347 { "macd", 2,3,3,0x7A00, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST},
348 { "macp", 2,3,3,0x7800, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST},
349 { "macsu", 1,3,3,0xA600, 0xFE00, {OP_Xmem,OP_Ymem,OP_SRC1}, 0, REST},
350 { "mar", 1,1,1,0x6D00, 0xFF00, {OP_Smem}, 0, REST},
351 { "mas", 1,2,2,0x2C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
352 { "mas", 1,3,4,0xB800, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
353 { "masr", 1,2,2,0x2E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
354 { "masr", 1,3,4,0xBC00, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
355 { "masa", 1,2,3,0xF48A, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, REST},/*SRC*/
356 { "masa", 1,1,2,0x3300, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
357 { "masar", 1,2,3,0xF48B, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, REST},
358 { "max", 1,1,1,0xF486, 0xFEFF, {OP_DST}, 0, REST},
359 { "min", 1,1,1,0xF487, 0xFEFF, {OP_DST}, 0, REST},
360 { "mpy", 1,2,2,0x2000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
361 { "mpy", 1,3,3,0xA400, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
362 { "mpy", 2,3,3,0x6200, 0xFE00, {OP_Smem,OP_lk,OP_DST}, FL_SMR, REST},
363 { "mpy", 2,2,2,0xF066, 0xFEFF, {OP_lk,OP_DST}, 0, REST},
364 { "mpyr", 1,2,2,0x2200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
365 { "mpya", 1,1,1,0xF48C, 0xFEFF, {OP_DST}, 0, REST}, /*SRC*/
366 { "mpya", 1,1,1,0x3100, 0xFF00, {OP_Smem}, FL_SMR, REST},
367 { "mpyu", 1,2,2,0x2400, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
368 { "mvdd", 1,2,2,0xE500, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
369 { "mvdk", 2,2,2,0x7100, 0xFF00, {OP_Smem,OP_dmad}, FL_SMR, REST},
370 { "mvdm", 2,2,2,0x7200, 0xFF00, {OP_dmad,OP_MMR}, 0, REST},
371 { "mvdp", 2,2,2,0x7D00, 0xFF00, {OP_Smem,OP_pmad}, FL_SMR, REST},
372 { "mvkd", 2,2,2,0x7000, 0xFF00, {OP_dmad,OP_Smem}, 0, REST},
373 { "mvmd", 2,2,2,0x7300, 0xFF00, {OP_MMR,OP_dmad}, 0, REST},
374 { "mvmm", 1,2,2,0xE700, 0xFF00, {OP_MMRX,OP_MMRY}, FL_NR, REST},
375 { "mvpd", 2,2,2,0x7C00, 0xFF00, {OP_pmad,OP_Smem}, 0, REST},
376 { "neg", 1,1,2,0xF484, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
377 { "nop", 1,0,0,0xF495, 0xFFFF, {OP_None}, 0, REST},
378 { "norm", 1,1,2,0xF48F, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
379 { "or", 1,1,3,0xF0A0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
380 { "or", 1,2,2,0x1A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
381 { "or", 2,2,4,0xF040, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
382 { "or", 2,3,4,0xF064, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
383 { "orm", 2,2,2,0x6900, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, REST},
384 { "poly", 1,1,1,0x3600, 0xFF00, {OP_Smem}, FL_SMR, REST},
385 { "popd", 1,1,1,0x8B00, 0xFF00, {OP_Smem}, 0, REST},
386 { "popm", 1,1,1,0x8A00, 0xFF00, {OP_MMR}, 0, REST},
387 { "portr", 2,2,2,0x7400, 0xFF00, {OP_PA,OP_Smem}, 0, REST},
388 { "portw", 2,2,2,0x7500, 0xFF00, {OP_Smem,OP_PA}, FL_SMR, REST},
389 { "pshd", 1,1,1,0x4B00, 0xFF00, {OP_Smem}, FL_SMR, REST},
390 { "pshm", 1,1,1,0x4A00, 0xFF00, {OP_MMR}, 0, REST},
391 { "ret", 1,0,0,0xFC00, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
392 { "retd", 1,0,0,0xFE00, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
5bd67f35 393 { "rc", 1,1,3,0xFC00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC},
6e917903 394 B_RET|FL_NR, REST},
5bd67f35 395 { "rcd", 1,1,3,0xFE00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC},
6e917903
TW		 396 B_RET|FL_DELAY|FL_NR, REST},
397 { "reada", 1,1,1,0x7E00, 0xFF00, {OP_Smem}, 0, REST},
398 { "reset", 1,0,0,0xF7E0, 0xFFFF, {OP_None}, FL_NR, REST},
399 { "rete", 1,0,0,0xF4EB, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
400 { "reted", 1,0,0,0xF6EB, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
401 { "retf", 1,0,0,0xF49B, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
402 { "retfd", 1,0,0,0xF69B, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
403 { "rnd", 1,1,2,0xF49F, 0xFCFF, {OP_SRC,OPT|OP_DST}, FL_LP|FL_NR, REST},
404 { "rol", 1,1,1,0xF491, 0xFEFF, {OP_SRC1}, 0, REST},
405 { "roltc", 1,1,1,0xF492, 0xFEFF, {OP_SRC1}, 0, REST},
406 { "ror", 1,1,1,0xF490, 0xFEFF, {OP_SRC1}, 0, REST},
407 { "rpt", 1,1,1,0x4700, 0xFF00, {OP_Smem}, B_REPEAT|FL_NR|FL_SMR, REST},
408 { "rpt", 1,1,1,0xEC00, 0xFF00, {OP_k8u}, B_REPEAT|FL_NR, REST},
409 { "rpt", 2,1,1,0xF070, 0xFFFF, {OP_lku}, B_REPEAT|FL_NR, REST},
410 { "rptb", 2,1,1,0xF072, 0xFFFF, {OP_pmad}, FL_NR, REST},
411 { "rptbd", 2,1,1,0xF272, 0xFFFF, {OP_pmad}, FL_DELAY|FL_NR, REST},
412 { "rptz", 2,2,2,0xF071, 0xFEFF, {OP_DST,OP_lku}, B_REPEAT|FL_NR, REST},
413 { "rsbx", 1,1,2,0xF4B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, REST},
414 { "saccd", 1,3,3,0x9E00, 0xFE00, {OP_SRC1,OP_Xmem,OP_CC2}, 0, REST},
415 { "sat", 1,1,1,0xF483, 0xFEFF, {OP_SRC1}, 0, REST},
416 { "sfta", 1,2,3,0xF460, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},
417 { "sftc", 1,1,1,0xF494, 0xFEFF, {OP_SRC1}, 0, REST},
418 { "sftl", 1,2,3,0xF0E0, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},
419 { "sqdst", 1,2,2,0xE200, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
420 { "squr", 1,2,2,0xF48D, 0xFEFF, {OP_A,OP_DST}, 0, REST},/*SRC*/
421 { "squr", 1,2,2,0x2600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
422 { "squra", 1,2,2,0x3800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
423 { "squrs", 1,2,2,0x3A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
424 { "srccd", 1,2,2,0x9D00, 0xFF00, {OP_Xmem,OP_CC2}, 0, REST},
425 { "ssbx", 1,1,2,0xF5B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, REST},
426 { "st", 1,2,2,0x8C00, 0xFF00, {OP_T,OP_Smem}, 0, REST},
427 { "st", 1,2,2,0x8D00, 0xFF00, {OP_TRN,OP_Smem}, 0, REST},
428 { "st", 2,2,2,0x7600, 0xFF00, {OP_lk,OP_Smem}, 0, REST},
429 { "sth", 1,2,2,0x8200, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
430 { "sth", 1,3,3,0x8600, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST},
431 { "sth", 1,3,3,0x9A00, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST},
5bd67f35 432 { "sth", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem},
6e917903
TW		 433 FL_EXT, 0x0C60, 0xFEE0, XREST},
434 { "stl", 1,2,2,0x8000, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
435 { "stl", 1,3,3,0x8400, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST},
436 { "stl", 1,3,3,0x9800, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST},
5bd67f35 437 { "stl", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem},
6e917903
TW		 438 FL_EXT, 0x0C80, 0xFEE0, XREST },
439 { "stlm", 1,2,2,0x8800, 0xFE00, {OP_SRC1,OP_MMR}, 0, REST},
440 { "stm", 2,2,2,0x7700, 0xFF00, {OP_lk,OP_MMR}, 0, REST},
441 { "strcd", 1,2,2,0x9C00, 0xFF00, {OP_Xmem,OP_CC2}, 0, REST},
442 { "sub", 1,1,3,0xF420, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
443 { "sub", 1,2,3,0xF481, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
444 { "sub", 1,2,2,0x0800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
445 { "sub", 1,3,3,0x0C00, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST},
446 { "sub", 1,3,4,0x4000, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
447 { "sub", 1,3,3,0x9200, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST}, /*PREFER*/
5bd67f35 448 { "sub", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST},
6e917903
TW		 449 FL_EXT|FL_SMR, 0x0C20, 0xFCE0, XREST},
450 { "sub", 1,3,3,0xA200, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
451 { "sub", 2,2,4,0xF010, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
452 { "sub", 2,3,4,0xF061, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
453 { "subb", 1,2,2,0x0E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
454 { "subc", 1,2,2,0x1E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
455 { "subs", 1,2,2,0x0A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
456 { "trap", 1,1,1,0xF4C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, REST},
457 { "writa", 1,1,1,0x7F00, 0xFF00, {OP_Smem}, FL_SMR, REST},
458 { "xc", 1,2,4,0xFD00, 0xFD00, {OP_12,OP_CC,OPT|OP_CC,OPT|OP_CC}, FL_NR, REST},
459 { "xor", 1,1,3,0xF0C0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
460 { "xor", 1,2,2,0x1C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
461 { "xor", 2,2,4,0xF050, 0xFCF0, {OP_lku,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
462 { "xor", 2,3,4,0xF065, 0xFCFF, {OP_lku,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
463 { "xorm", 2,2,2,0x6A00, 0xFF00, {OP_lku,OP_Smem}, FL_NR|FL_SMR, REST},
464 { NULL, 0,0,0,0,0, {}, 0, REST},
5c84d377
TW		 465};
466
467/* assume all parallel instructions have at least three operands */
d3ce72d0 468const insn_template tic54x_paroptab[] = {
6e917903
TW		 469 { "ld",1,1,2,0xA800, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
470 "mac", {OP_Ymem,OPT|OP_RND},},
471 { "ld",1,1,2,0xAA00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
472 "macr", {OP_Ymem,OPT|OP_RND},},
473 { "ld",1,1,2,0xAC00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
474 "mas", {OP_Ymem,OPT|OP_RND},},
475 { "ld",1,1,2,0xAE00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
476 "masr", {OP_Ymem,OPT|OP_RND},},
477 { "st",1,2,2,0xC000, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
478 "add", {OP_Xmem,OP_DST}, },
479 { "st",1,2,2,0xC800, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
480 "ld", {OP_Xmem,OP_DST}, },
481 { "st",1,2,2,0xE400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
482 "ld", {OP_Xmem,OP_T}, },
483 { "st",1,2,2,0xD000, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
484 "mac", {OP_Xmem,OP_DST}, },
485 { "st",1,2,2,0xD400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
486 "macr", {OP_Xmem,OP_DST}, },
487 { "st",1,2,2,0xD800, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
488 "mas", {OP_Xmem,OP_DST}, },
489 { "st",1,2,2,0xDC00, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
490 "masr", {OP_Xmem,OP_DST}, },
491 { "st",1,2,2,0xCC00, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
492 "mpy", {OP_Xmem,OP_DST}, },
493 { "st",1,2,2,0xC400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
494 "sub", {OP_Xmem,OP_DST}, },
495 { NULL, 0, 0, 0, 0, 0, {0,0,0,0}, 0, REST },
5c84d377 496};
GDB Binutils - Deliverables
This page took 0.889905 seconds and 4 git commands to generate.