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5c84d377 TW |
1 | /* Table of opcodes for the Texas Instruments TMS320C54X |
2 | Copyright (C) 1999, 2000 Free Software Foundation, Inc. | |
3 | Contributed by Timothy Wall (twall@cygnus.com) | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
17 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA | |
18 | 02111-1307, USA. */ | |
19 | ||
20 | #include <stdio.h> | |
21 | #include "ansidecl.h" | |
22 | #include "opcode/tic54x.h" | |
23 | ||
24 | /* these are the only register names not found in mmregs */ | |
25 | const symbol regs[] = { | |
26 | { "AR0", 16 }, { "ar0", 16 }, | |
27 | { "AR1", 17 }, { "ar1", 17 }, | |
28 | { "AR2", 18 }, { "ar2", 18 }, | |
29 | { "AR3", 19 }, { "ar3", 19 }, | |
30 | { "AR4", 20 }, { "ar4", 20 }, | |
31 | { "AR5", 21 }, { "ar5", 21 }, | |
32 | { "AR6", 22 }, { "ar6", 22 }, | |
33 | { "AR7", 23 }, { "ar7", 23 }, | |
34 | { NULL, } | |
35 | }; | |
36 | ||
37 | /* status bits, MM registers, condition codes, etc */ | |
38 | /* some symbols are only valid for certain chips... */ | |
39 | const symbol mmregs[] = { | |
40 | { "IMR", 0 }, { "imr", 0 }, | |
41 | { "IFR", 1 }, { "ifr", 1 }, | |
42 | { "ST0", 6 }, { "st0", 6 }, | |
43 | { "ST1", 7 }, { "st1", 7 }, | |
44 | { "AL", 8 }, { "al", 8 }, | |
45 | { "AH", 9 }, { "ah", 9 }, | |
46 | { "AG", 10 }, { "ag", 10 }, | |
47 | { "BL", 11 }, { "bl", 11 }, | |
48 | { "BH", 12 }, { "bh", 12 }, | |
49 | { "BG", 13 }, { "bg", 13 }, | |
50 | { "T", 14 }, { "t", 14 }, | |
51 | { "TRN", 15 }, { "trn", 15 }, | |
52 | { "AR0", 16 }, { "ar0", 16 }, | |
53 | { "AR1", 17 }, { "ar1", 17 }, | |
54 | { "AR2", 18 }, { "ar2", 18 }, | |
55 | { "AR3", 19 }, { "ar3", 19 }, | |
56 | { "AR4", 20 }, { "ar4", 20 }, | |
57 | { "AR5", 21 }, { "ar5", 21 }, | |
58 | { "AR6", 22 }, { "ar6", 22 }, | |
59 | { "AR7", 23 }, { "ar7", 23 }, | |
60 | { "SP", 24 }, { "sp", 24 }, | |
61 | { "BK", 25 }, { "bk", 25 }, | |
62 | { "BRC", 26 }, { "brc", 26 }, | |
63 | { "RSA", 27 }, { "rsa", 27 }, | |
64 | { "REA", 28 }, { "rea", 28 }, | |
65 | { "PMST",29 }, { "pmst",29 }, | |
66 | { "XPC", 30 }, { "xpc", 30 }, /* 'c548 only */ | |
67 | /* optional peripherals */ /* optional peripherals */ | |
68 | { "M1F", 31 }, { "m1f", 31 }, | |
69 | { "DRR0",0x20 }, { "drr0",0x20 }, | |
70 | { "BDRR0",0x20 }, { "bdrr0",0x20 }, /* 'c543, 545 */ | |
71 | { "DXR0",0x21 }, { "dxr0",0x21 }, | |
72 | { "BDXR0",0x21 }, { "bdxr0",0x21 }, /* 'c543, 545 */ | |
73 | { "SPC0",0x22 }, { "spc0",0x22 }, | |
74 | { "BSPC0",0x22 }, { "bspc0",0x22 }, /* 'c543, 545 */ | |
75 | { "SPCE0",0x23 }, { "spce0",0x23 }, | |
76 | { "BSPCE0",0x23 }, { "bspce0",0x23 }, /* 'c543, 545 */ | |
77 | { "TIM", 0x24 }, { "tim", 0x24 }, | |
78 | { "PRD", 0x25 }, { "prd", 0x25 }, | |
79 | { "TCR", 0x26 }, { "tcr", 0x26 }, | |
80 | { "SWWSR",0x28 }, { "swwsr",0x28 }, | |
81 | { "BSCR",0x29 }, { "bscr",0x29 }, | |
82 | { "HPIC",0x2C }, { "hpic",0x2c }, | |
83 | /* 'c541, 'c545 */ /* 'c541, 'c545 */ | |
84 | { "DRR1",0x30 }, { "drr1",0x30 }, | |
85 | { "DXR1",0x31 }, { "dxr1",0x31 }, | |
86 | { "SPC1",0x32 }, { "spc1",0x32 }, | |
87 | /* 'c542, 'c543 */ /* 'c542, 'c543 */ | |
88 | { "TRCV",0x30 }, { "trcv",0x30 }, | |
89 | { "TDXR",0x31 }, { "tdxr",0x31 }, | |
90 | { "TSPC",0x32 }, { "tspc",0x32 }, | |
91 | { "TCSR",0x33 }, { "tcsr",0x33 }, | |
92 | { "TRTA",0x34 }, { "trta",0x34 }, | |
93 | { "TRAD",0x35 }, { "trad",0x35 }, | |
94 | { "AXR0",0x38 }, { "axr0",0x38 }, | |
95 | { "BKX0",0x39 }, { "bkx0",0x39 }, | |
96 | { "ARR0",0x3A }, { "arr0",0x3a }, | |
97 | { "BKR0",0x3B }, { "bkr0",0x3b }, | |
98 | /* 'c545, 'c546, 'c548 */ /* 'c545, 'c546, 'c548 */ | |
99 | { "CLKMD",0x58 }, { "clkmd",0x58 }, | |
100 | /* 'c548 */ /* 'c548 */ | |
101 | { "AXR1",0x3C }, { "axr1",0x3c }, | |
102 | { "BKX1",0x3D }, { "bkx1",0x3d }, | |
103 | { "ARR1",0x3E }, { "arr1",0x3e }, | |
104 | { "BKR1",0x3F }, { "bkr1",0x3f }, | |
105 | { "BDRR1",0x40 }, { "bdrr1",0x40 }, | |
106 | { "BDXR1",0x41 }, { "bdxr1",0x41 }, | |
107 | { "BSPC1",0x42 }, { "bspc1",0x42 }, | |
108 | { "BSPCE1",0x43 }, { "bspce1",0x43 }, | |
109 | { NULL }, | |
110 | }; | |
111 | ||
112 | const symbol condition_codes[] = { | |
113 | /* condition codes */ | |
114 | { "UNC", 0 }, { "unc", 0 }, | |
115 | #define CC1 0x40 | |
116 | #define CCB 0x08 | |
117 | #define CCEQ 0x05 | |
118 | #define CCNEQ 0x04 | |
119 | #define CCLT 0x03 | |
120 | #define CCLEQ 0x07 | |
121 | #define CCGT 0x06 | |
122 | #define CCGEQ 0x02 | |
123 | #define CCOV 0x70 | |
124 | #define CCNOV 0x60 | |
125 | #define CCBIO 0x03 | |
126 | #define CCNBIO 0x02 | |
127 | #define CCTC 0x30 | |
128 | #define CCNTC 0x20 | |
129 | #define CCC 0x0C | |
130 | #define CCNC 0x08 | |
131 | { "aeq", CC1|CCEQ }, { "AEQ", CC1|CCEQ }, | |
132 | { "aneq", CC1|CCNEQ }, { "ANEQ", CC1|CCNEQ }, | |
133 | { "alt", CC1|CCLT }, { "ALT", CC1|CCLT }, | |
134 | { "aleq", CC1|CCLEQ }, { "ALEQ", CC1|CCLEQ }, | |
135 | { "agt", CC1|CCGT }, { "AGT", CC1|CCGT }, | |
136 | { "ageq", CC1|CCGEQ }, { "AGEQ", CC1|CCGEQ }, | |
137 | { "aov", CC1|CCOV }, { "AOV", CC1|CCOV }, | |
138 | { "anov", CC1|CCNOV }, { "ANOV", CC1|CCNOV }, | |
139 | { "beq", CC1|CCB|CCEQ }, { "BEQ", CC1|CCB|CCEQ }, | |
140 | { "bneq", CC1|CCB|CCNEQ }, { "BNEQ", CC1|CCB|CCNEQ }, | |
141 | { "blt", CC1|CCB|CCLT }, { "BLT", CC1|CCB|CCLT }, | |
142 | { "bleq", CC1|CCB|CCLEQ }, { "BLEQ", CC1|CCB|CCLEQ }, | |
143 | { "bgt", CC1|CCB|CCGT }, { "BGT", CC1|CCB|CCGT }, | |
144 | { "bgeq", CC1|CCB|CCGEQ }, { "BGEQ", CC1|CCB|CCGEQ }, | |
145 | { "bov", CC1|CCB|CCOV }, { "BOV", CC1|CCB|CCOV }, | |
146 | { "bnov", CC1|CCB|CCNOV }, { "BNOV", CC1|CCB|CCNOV }, | |
147 | { "tc", CCTC }, { "TC", CCTC }, | |
148 | { "ntc", CCNTC }, { "NTC", CCNTC }, | |
149 | { "c", CCC }, { "C", CCC }, | |
150 | { "nc", CCNC }, { "NC", CCNC }, | |
151 | { "bio", CCBIO }, { "BIO", CCBIO }, | |
152 | { "nbio", CCNBIO }, { "NBIO", CCNBIO }, | |
153 | { NULL, } | |
154 | }; | |
155 | ||
156 | const symbol cc2_codes[] = { | |
157 | { "UNC", 0 }, { "unc", 0 }, | |
158 | { "AEQ", 5 }, { "aeq", 5 }, | |
159 | { "ANEQ", 4 }, { "aneq", 4 }, | |
160 | { "AGT", 6 }, { "agt", 6 }, | |
161 | { "ALT", 3 }, { "alt", 3 }, | |
162 | { "ALEQ", 7 }, { "aleq", 7 }, | |
163 | { "AGEQ", 2 }, { "ageq", 2 }, | |
164 | { "BEQ", 13 }, { "beq", 13 }, | |
165 | { "BNEQ", 12 },{ "bneq", 12 }, | |
166 | { "BGT", 14 }, { "bgt", 14 }, | |
167 | { "BLT", 11 }, { "blt", 11 }, | |
168 | { "BLEQ", 15 },{ "bleq", 15 }, | |
169 | { "BGEQ", 10 },{ "bgeq", 10 }, | |
170 | { NULL }, | |
171 | }; | |
172 | ||
173 | const symbol cc3_codes[] = { | |
174 | { "EQ", 0x0000 }, { "eq", 0x0000 }, | |
175 | { "LT", 0x0100 }, { "lt", 0x0100 }, | |
176 | { "GT", 0x0200 }, { "gt", 0x0200 }, | |
177 | { "NEQ", 0x0300 }, { "neq", 0x0300 }, | |
178 | { "0", 0x0000 }, | |
179 | { "1", 0x0100 }, | |
180 | { "2", 0x0200 }, | |
181 | { "3", 0x0300 }, | |
182 | { "00", 0x0000 }, | |
183 | { "01", 0x0100 }, | |
184 | { "10", 0x0200 }, | |
185 | { "11", 0x0300 }, | |
186 | { NULL }, | |
187 | }; | |
188 | ||
189 | /* FIXME -- also allow decimal digits */ | |
190 | const symbol status_bits[] = { | |
191 | /* status register 0 */ | |
192 | { "TC", 12 }, { "tc", 12 }, | |
193 | { "C", 11 }, { "c", 11 }, | |
194 | { "OVA", 10 }, { "ova", 10 }, | |
195 | { "OVB", 9 }, { "ovb", 9 }, | |
196 | /* status register 1 */ | |
197 | { "BRAF",15 }, { "braf",15 }, | |
198 | { "CPL", 14 }, { "cpl", 14 }, | |
199 | { "XF", 13 }, { "xf", 13 }, | |
200 | { "HM", 12 }, { "hm", 12 }, | |
201 | { "INTM",11 }, { "intm",11 }, | |
202 | { "OVM", 9 }, { "ovm", 9 }, | |
203 | { "SXM", 8 }, { "sxm", 8 }, | |
204 | { "C16", 7 }, { "c16", 7 }, | |
205 | { "FRCT", 6 }, { "frct", 6 }, | |
206 | { "CMPT", 5 }, { "cmpt", 5 }, | |
207 | { NULL }, | |
208 | }; | |
209 | ||
210 | const char *misc_symbols[] = { | |
211 | "ARP", "arp", | |
212 | "DP", "dp", | |
213 | "ASM", "asm", | |
214 | "TS", "ts", | |
215 | NULL | |
216 | }; | |
217 | ||
218 | /* Due to the way instructions are hashed and scanned in | |
219 | gas/config/tc-tic54x.c, all identically-named opcodes must be consecutively | |
220 | placed | |
221 | ||
222 | Items marked with "PREFER" have been moved prior to a more costly | |
223 | instruction with a similar operand format. | |
224 | ||
225 | Mnemonics which can take either a predefined symbol or a memory reference | |
226 | as an argument are arranged so that the more restrictive (predefined | |
227 | symbol) version is checked first (marked "SRC"). | |
228 | */ | |
229 | const template tic54x_unknown_opcode = | |
230 | { "???", 1,0,0,0x0000, 0x0000, {0}, }; | |
231 | const template tic54x_optab[] = { | |
232 | /* these must precede bc/bcd, cc/ccd to avoid misinterpretation */ | |
233 | { "fb", 2,1,1,0xF880, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, }, | |
234 | { "fbd", 2,1,1,0xFA80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, }, | |
235 | { "fcall", 2,1,1,0xF980, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, }, | |
236 | { "fcalld",2,1,1,0xFB80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, }, | |
237 | ||
238 | { "abdst", 1,2,2,0xE300, 0xFF00, {OP_Xmem,OP_Ymem}, }, | |
239 | { "abs", 1,1,2,0xF485, 0xFCFF, {OP_SRC,OPT|OP_DST}, }, | |
240 | { "add", 1,1,3,0xF400, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, },/*SRC*/ | |
241 | { "add", 1,2,3,0xF480, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, },/*SRC*/ | |
242 | { "add", 1,2,2,0x0000, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, | |
243 | { "add", 1,3,3,0x0400, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR }, | |
244 | { "add", 1,3,4,0x3C00, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR}, | |
245 | { "add", 1,3,3,0x9000, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, },/*PREFER*/ | |
246 | { "add", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, | |
247 | FL_EXT|FL_SMR, 0x0C00, 0xFCE0}, | |
248 | { "add", 1,3,3,0xA000, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, }, | |
249 | { "add", 2,2,4,0xF000, 0xFCF0, {OP_lk,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, }, | |
250 | { "add", 2,3,4,0xF060, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, }, | |
251 | { "addc", 1,2,2,0x0600, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, | |
252 | { "addm", 2,2,2,0x6B00, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, }, | |
253 | { "adds", 1,2,2,0x0200, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, | |
254 | { "and", 1,1,3,0xF080, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, }, | |
255 | { "and", 1,2,2,0x1800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, | |
256 | { "and", 2,2,4,0xF030, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, }, | |
257 | { "and", 2,3,4,0xF063, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, }, | |
258 | { "andm", 2,2,2,0x6800, 0xFF00, {OP_lk,OP_Smem}, FL_NR, }, | |
259 | { "b", 2,1,1,0xF073, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, }, | |
260 | { "bd", 2,1,1,0xF273, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, }, | |
261 | { "bacc", 1,1,1,0xF4E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, }, | |
262 | { "baccd", 1,1,1,0xF6E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, }, | |
263 | { "banz", 2,2,2,0x6C00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_NR, }, | |
264 | { "banzd", 2,2,2,0x6E00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_DELAY|FL_NR, }, | |
265 | { "bc", 2,2,4,0xF800, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, | |
266 | B_BRANCH|FL_NR, }, | |
267 | { "bcd", 2,2,4,0xFA00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, | |
268 | B_BRANCH|FL_DELAY|FL_NR, }, | |
269 | { "bit", 1,2,2,0x9600, 0xFF00, {OP_Xmem,OP_BITC}, }, | |
270 | { "bitf", 2,2,2,0x6100, 0xFF00, {OP_Smem,OP_lk}, FL_SMR }, | |
271 | { "bitt", 1,1,1,0x3400, 0xFF00, {OP_Smem}, FL_SMR }, | |
272 | { "cala", 1,1,1,0xF4E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, }, | |
273 | { "calad", 1,1,1,0xF6E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, }, | |
274 | { "call", 2,1,1,0xF074, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, }, | |
275 | { "calld", 2,1,1,0xF274, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, }, | |
276 | { "cc", 2,2,4,0xF900, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, | |
277 | B_BRANCH|FL_NR, }, | |
278 | { "ccd", 2,2,4,0xFB00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, | |
279 | B_BRANCH|FL_DELAY|FL_NR, }, | |
280 | { "cmpl", 1,1,2,0xF493, 0xFCFF, {OP_SRC,OPT|OP_DST}, }, | |
281 | { "cmpm", 2,2,2,0x6000, 0xFF00, {OP_Smem,OP_lk}, FL_SMR }, | |
282 | { "cmpr", 1,2,2,0xF4A8, 0xFCF8, {OP_CC3,OP_ARX}, FL_NR, }, | |
283 | { "cmps", 1,2,2,0x8E00, 0xFE00, {OP_SRC1,OP_Smem}, }, | |
284 | { "dadd", 1,2,3,0x5000, 0xFC00, {OP_Lmem,OP_SRC,OPT|OP_DST}, }, | |
285 | { "dadst", 1,2,2,0x5A00, 0xFE00, {OP_Lmem,OP_DST}, }, | |
286 | { "delay", 1,1,1,0x4D00, 0xFF00, {OP_Smem}, FL_SMR }, | |
287 | { "dld", 1,2,2,0x5600, 0xFE00, {OP_Lmem,OP_DST}, }, | |
288 | { "drsub", 1,2,2,0x5800, 0xFE00, {OP_Lmem,OP_SRC1}, }, | |
289 | { "dsadt", 1,2,2,0x5E00, 0xFE00, {OP_Lmem,OP_DST}, }, | |
290 | { "dst", 1,2,2,0x4E00, 0xFE00, {OP_SRC1,OP_Lmem}, FL_NR, }, | |
291 | { "dsub", 1,2,2,0x5400, 0xFE00, {OP_Lmem,OP_SRC1}, }, | |
292 | { "dsubt", 1,2,2,0x5C00, 0xFE00, {OP_Lmem,OP_DST}, }, | |
293 | { "exp", 1,1,1,0xF48E, 0xFEFF, {OP_SRC1}, }, | |
294 | { "fbacc", 1,1,1,0xF4E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, }, | |
295 | { "fbaccd",1,1,1,0xF6E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, }, | |
296 | { "fcala", 1,1,1,0xF4E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, }, | |
297 | { "fcalad",1,1,1,0xF6E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, }, | |
298 | { "firs", 2,3,3,0xE000, 0xFF00, {OP_Xmem,OP_Ymem,OP_pmad}, }, | |
299 | { "frame", 1,1,1,0xEE00, 0xFF00, {OP_k8}, }, | |
300 | { "fret", 1,0,0,0xF4E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, }, | |
301 | { "fretd", 1,0,0,0xF6E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, }, | |
302 | { "frete", 1,0,0,0xF4E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, }, | |
303 | { "freted",1,0,0,0xF6E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, }, | |
304 | { "idle", 1,1,1,0xF4E1, 0xFCFF, {OP_123}, FL_NR, }, | |
305 | { "intr", 1,1,1,0xF7C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, }, | |
306 | { "ld", 1,2,3,0xF482, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, },/*SRC*/ | |
307 | { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OP_DST}, },/*SRC*/ | |
308 | /* alternate syntax */ | |
309 | { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, },/*SRC*/ | |
310 | { "ld", 1,2,2,0xE800, 0xFE00, {OP_k8u,OP_DST}, },/*SRC*/ | |
311 | { "ld", 1,2,2,0xED00, 0xFFE0, {OP_k5,OP_ASM}, },/*SRC*/ | |
312 | { "ld", 1,2,2,0xF4A0, 0xFFF8, {OP_k3,OP_ARP}, FL_NR, },/*SRC*/ | |
313 | { "ld", 1,2,2,0xEA00, 0xFE00, {OP_k9,OP_DP}, FL_NR, },/*PREFER */ | |
314 | { "ld", 1,2,2,0x3000, 0xFF00, {OP_Smem,OP_T}, FL_SMR },/*SRC*/ | |
315 | { "ld", 1,2,2,0x4600, 0xFF00, {OP_Smem,OP_DP}, FL_SMR },/*SRC*/ | |
316 | { "ld", 1,2,2,0x3200, 0xFF00, {OP_Smem,OP_ASM}, FL_SMR },/*SRC*/ | |
317 | { "ld", 1,2,2,0x1000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, | |
318 | { "ld", 1,3,3,0x1400, 0xFE00, {OP_Smem,OP_TS,OP_DST}, FL_SMR }, | |
319 | { "ld", 1,3,3,0x4400, 0xFE00, {OP_Smem,OP_16,OP_DST}, FL_SMR }, | |
320 | { "ld", 1,3,3,0x9400, 0xFE00, {OP_Xmem,OP_SHFT,OP_DST}, },/*PREFER*/ | |
321 | { "ld", 2,2,3,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_DST}, | |
322 | FL_EXT|FL_SMR, 0x0C40, 0xFEE0 }, | |
323 | { "ld", 2,2,3,0xF020, 0xFEF0, {OP_lk,OPT|OP_SHFT,OP_DST}, }, | |
324 | { "ld", 2,3,3,0xF062, 0xFEFF, {OP_lk,OP_16,OP_DST}, }, | |
325 | { "ldm", 1,2,2,0x4800, 0xFE00, {OP_MMR,OP_DST}, }, | |
326 | { "ldr", 1,2,2,0x1600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, | |
327 | { "ldu", 1,2,2,0x1200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, | |
328 | { "ldx", 2,3,3,0xF062, 0xFEFF, {OP_xpmad_ms7,OP_16,OP_DST}, FL_FAR},/*pseudo-op*/ | |
329 | { "lms", 1,2,2,0xE100, 0xFF00, {OP_Xmem,OP_Ymem}, }, | |
330 | { "ltd", 1,1,1,0x4C00, 0xFF00, {OP_Smem}, FL_SMR }, | |
331 | { "mac", 1,2,2,0x2800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, | |
332 | { "mac", 1,3,4,0xB000, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, }, | |
333 | { "mac", 2,2,3,0xF067, 0xFCFF, {OP_lk,OP_SRC,OPT|OP_DST}, }, | |
334 | { "mac", 2,3,4,0x6400, 0xFC00, {OP_Smem,OP_lk,OP_SRC,OPT|OP_DST}, FL_SMR }, | |
335 | { "macr", 1,2,2,0x2A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, | |
336 | { "macr", 1,3,4,0xB400, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST},FL_SMR}, | |
337 | { "maca", 1,2,3,0xF488, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR },/*SRC*/ | |
338 | { "maca", 1,1,2,0x3500, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR }, | |
339 | { "macar", 1,2,3,0xF489, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR },/*SRC*/ | |
340 | { "macar", 1,1,2,0x3700, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR }, | |
341 | { "macd", 2,3,3,0x7A00, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR }, | |
342 | { "macp", 2,3,3,0x7800, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR }, | |
343 | { "macsu", 1,3,3,0xA600, 0xFE00, {OP_Xmem,OP_Ymem,OP_SRC1}, }, | |
344 | { "mar", 1,1,1,0x6D00, 0xFF00, {OP_Smem}, }, | |
345 | { "mas", 1,2,2,0x2C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, | |
346 | { "mas", 1,3,4,0xB800, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, }, | |
347 | { "masr", 1,2,2,0x2E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, | |
348 | { "masr", 1,3,4,0xBC00, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, }, | |
349 | { "masa", 1,2,3,0xF48A, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, },/*SRC*/ | |
350 | { "masa", 1,1,2,0x3300, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR }, | |
351 | { "masar", 1,2,3,0xF48B, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, }, | |
352 | { "max", 1,1,1,0xF486, 0xFEFF, {OP_DST}, }, | |
353 | { "min", 1,1,1,0xF487, 0xFEFF, {OP_DST}, }, | |
354 | { "mpy", 1,2,2,0x2000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, | |
355 | { "mpy", 1,3,3,0xA400, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, }, | |
356 | { "mpy", 2,3,3,0x6200, 0xFE00, {OP_Smem,OP_lk,OP_DST}, FL_SMR }, | |
357 | { "mpy", 2,2,2,0xF066, 0xFEFF, {OP_lk,OP_DST}, }, | |
358 | { "mpyr", 1,2,2,0x2200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, | |
359 | { "mpya", 1,1,1,0xF48C, 0xFEFF, {OP_DST}, }, /*SRC*/ | |
360 | { "mpya", 1,1,1,0x3100, 0xFF00, {OP_Smem}, FL_SMR }, | |
361 | { "mpyu", 1,2,2,0x2400, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, | |
362 | { "mvdd", 1,2,2,0xE500, 0xFF00, {OP_Xmem,OP_Ymem}, }, | |
363 | { "mvdk", 2,2,2,0x7100, 0xFF00, {OP_Smem,OP_dmad}, FL_SMR }, | |
364 | { "mvdm", 2,2,2,0x7200, 0xFF00, {OP_dmad,OP_MMR}, }, | |
365 | { "mvdp", 2,2,2,0x7D00, 0xFF00, {OP_Smem,OP_pmad}, FL_SMR }, | |
366 | { "mvkd", 2,2,2,0x7000, 0xFF00, {OP_dmad,OP_Smem}, }, | |
367 | { "mvmd", 2,2,2,0x7300, 0xFF00, {OP_MMR,OP_dmad}, }, | |
368 | { "mvmm", 1,2,2,0xE700, 0xFF00, {OP_MMRX,OP_MMRY}, FL_NR, }, | |
369 | { "mvpd", 2,2,2,0x7C00, 0xFF00, {OP_pmad,OP_Smem}, }, | |
370 | { "neg", 1,1,2,0xF484, 0xFCFF, {OP_SRC,OPT|OP_DST}, }, | |
371 | { "nop", 1,0,0,0xF495, 0xFFFF, {OP_None}, }, | |
372 | { "norm", 1,1,2,0xF48F, 0xFCFF, {OP_SRC,OPT|OP_DST}, }, | |
373 | { "or", 1,1,3,0xF0A0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, },/*SRC*/ | |
374 | { "or", 1,2,2,0x1A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, | |
375 | { "or", 2,2,4,0xF040, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, }, | |
376 | { "or", 2,3,4,0xF064, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, }, | |
377 | { "orm", 2,2,2,0x6900, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, }, | |
378 | { "poly", 1,1,1,0x3600, 0xFF00, {OP_Smem}, FL_SMR }, | |
379 | { "popd", 1,1,1,0x8B00, 0xFF00, {OP_Smem}, }, | |
380 | { "popm", 1,1,1,0x8A00, 0xFF00, {OP_MMR}, }, | |
381 | { "portr", 2,2,2,0x7400, 0xFF00, {OP_PA,OP_Smem}, }, | |
382 | { "portw", 2,2,2,0x7500, 0xFF00, {OP_Smem,OP_PA}, FL_SMR }, | |
383 | { "pshd", 1,1,1,0x4B00, 0xFF00, {OP_Smem}, FL_SMR }, | |
384 | { "pshm", 1,1,1,0x4A00, 0xFF00, {OP_MMR}, }, | |
385 | { "ret", 1,0,0,0xFC00, 0xFFFF, {OP_None}, B_RET|FL_NR, }, | |
386 | { "retd", 1,0,0,0xFE00, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, }, | |
387 | { "rc", 1,1,3,0xFC00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC}, | |
388 | B_RET|FL_NR, }, | |
389 | { "rcd", 1,1,3,0xFE00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC}, | |
390 | B_RET|FL_DELAY|FL_NR, }, | |
391 | { "reada", 1,1,1,0x7E00, 0xFF00, {OP_Smem}, }, | |
392 | { "reset", 1,0,0,0xF7E0, 0xFFFF, {OP_None}, FL_NR, }, | |
393 | { "rete", 1,0,0,0xF4EB, 0xFFFF, {OP_None}, B_RET|FL_NR, }, | |
394 | { "reted", 1,0,0,0xF6EB, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, }, | |
395 | { "retf", 1,0,0,0xF49B, 0xFFFF, {OP_None}, B_RET|FL_NR, }, | |
396 | { "retfd", 1,0,0,0xF69B, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, }, | |
397 | { "rnd", 1,1,2,0xF49F, 0xFCFF, {OP_SRC,OPT|OP_DST}, FL_LP|FL_NR }, | |
398 | { "rol", 1,1,1,0xF491, 0xFEFF, {OP_SRC1}, }, | |
399 | { "roltc", 1,1,1,0xF492, 0xFEFF, {OP_SRC1}, }, | |
400 | { "ror", 1,1,1,0xF490, 0xFEFF, {OP_SRC1}, }, | |
401 | { "rpt", 1,1,1,0x4700, 0xFF00, {OP_Smem}, B_REPEAT|FL_NR|FL_SMR, }, | |
402 | { "rpt", 1,1,1,0xEC00, 0xFF00, {OP_k8u}, B_REPEAT|FL_NR, }, | |
403 | { "rpt", 2,1,1,0xF070, 0xFFFF, {OP_lku}, B_REPEAT|FL_NR, }, | |
404 | { "rptb", 2,1,1,0xF072, 0xFFFF, {OP_pmad}, FL_NR, }, | |
405 | { "rptbd", 2,1,1,0xF272, 0xFFFF, {OP_pmad}, FL_DELAY|FL_NR, }, | |
406 | { "rptz", 2,2,2,0xF071, 0xFEFF, {OP_DST,OP_lku}, B_REPEAT|FL_NR, }, | |
407 | { "rsbx", 1,1,2,0xF4B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, }, | |
408 | { "saccd", 1,3,3,0x9E00, 0xFE00, {OP_SRC1,OP_Xmem,OP_CC2}, }, | |
409 | { "sat", 1,1,1,0xF483, 0xFEFF, {OP_SRC1}, }, | |
410 | { "sfta", 1,2,3,0xF460, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, }, | |
411 | { "sftc", 1,1,1,0xF494, 0xFEFF, {OP_SRC1}, }, | |
412 | { "sftl", 1,2,3,0xF0E0, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, }, | |
413 | { "sqdst", 1,2,2,0xE200, 0xFF00, {OP_Xmem,OP_Ymem}, }, | |
414 | { "squr", 1,2,2,0xF48D, 0xFEFF, {OP_A,OP_DST}, },/*SRC*/ | |
415 | { "squr", 1,2,2,0x2600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, | |
416 | { "squra", 1,2,2,0x3800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, | |
417 | { "squrs", 1,2,2,0x3A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, | |
418 | { "srccd", 1,2,2,0x9D00, 0xFF00, {OP_Xmem,OP_CC2}, }, | |
419 | { "ssbx", 1,1,2,0xF5B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, }, | |
420 | { "st", 1,2,2,0x8C00, 0xFF00, {OP_T,OP_Smem}, }, | |
421 | { "st", 1,2,2,0x8D00, 0xFF00, {OP_TRN,OP_Smem}, }, | |
422 | { "st", 2,2,2,0x7600, 0xFF00, {OP_lk,OP_Smem}, }, | |
423 | { "sth", 1,2,2,0x8200, 0xFE00, {OP_SRC1,OP_Smem}, }, | |
424 | { "sth", 1,3,3,0x8600, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, }, | |
425 | { "sth", 1,3,3,0x9A00, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, }, | |
426 | { "sth", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem}, | |
427 | FL_EXT, 0x0C60, 0xFEE0 }, | |
428 | { "stl", 1,2,2,0x8000, 0xFE00, {OP_SRC1,OP_Smem}, }, | |
429 | { "stl", 1,3,3,0x8400, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, }, | |
430 | { "stl", 1,3,3,0x9800, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, }, | |
431 | { "stl", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem}, | |
432 | FL_EXT, 0x0C80, 0xFEE0 }, | |
433 | { "stlm", 1,2,2,0x8800, 0xFE00, {OP_SRC1,OP_MMR}, }, | |
434 | { "stm", 2,2,2,0x7700, 0xFF00, {OP_lk,OP_MMR}, }, | |
435 | { "strcd", 1,2,2,0x9C00, 0xFF00, {OP_Xmem,OP_CC2}, }, | |
436 | { "sub", 1,1,3,0xF420, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, },/*SRC*/ | |
437 | { "sub", 1,2,3,0xF481, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, },/*SRC*/ | |
438 | { "sub", 1,2,2,0x0800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, | |
439 | { "sub", 1,3,3,0x0C00, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR }, | |
440 | { "sub", 1,3,4,0x4000, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR }, | |
441 | { "sub", 1,3,3,0x9200, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, }, /*PREFER*/ | |
442 | { "sub", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, | |
443 | FL_EXT|FL_SMR, 0x0C20, 0xFCE0 }, | |
444 | { "sub", 1,3,3,0xA200, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, }, | |
445 | { "sub", 2,2,4,0xF010, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, }, | |
446 | { "sub", 2,3,4,0xF061, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, }, | |
447 | { "subb", 1,2,2,0x0E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, | |
448 | { "subc", 1,2,2,0x1E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, | |
449 | { "subs", 1,2,2,0x0A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, | |
450 | { "trap", 1,1,1,0xF4C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, }, | |
451 | { "writa", 1,1,1,0x7F00, 0xFF00, {OP_Smem}, FL_SMR }, | |
452 | { "xc", 1,2,4,0xFD00, 0xFD00, {OP_12,OP_CC,OPT|OP_CC,OPT|OP_CC}, FL_NR, }, | |
453 | { "xor", 1,1,3,0xF0C0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, },/*SRC*/ | |
454 | { "xor", 1,2,2,0x1C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, | |
455 | { "xor", 2,2,4,0xF050, 0xFCF0, {OP_lku,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, }, | |
456 | { "xor", 2,3,4,0xF065, 0xFCFF, {OP_lku,OP_16,OP_SRC,OPT|OP_DST}, }, | |
457 | { "xorm", 2,2,2,0x6A00, 0xFF00, {OP_lku,OP_Smem}, FL_NR|FL_SMR, }, | |
458 | { NULL, }, | |
459 | }; | |
460 | ||
461 | /* assume all parallel instructions have at least three operands */ | |
462 | const partemplate tic54x_paroptab[] = { | |
463 | { "ld","mac", 1,1,2,0xA800, 0xFE00, {OP_Xmem,OP_DST},{OP_Ymem,OPT|OP_RND},}, | |
464 | { "ld","macr",1,1,2,0xAA00, 0xFE00, {OP_Xmem,OP_DST},{OP_Ymem,OPT|OP_RND},}, | |
465 | { "ld","mas", 1,1,2,0xAC00, 0xFE00, {OP_Xmem,OP_DST},{OP_Ymem,OPT|OP_RND},}, | |
466 | { "ld","masr",1,1,2,0xAE00, 0xFE00, {OP_Xmem,OP_DST},{OP_Ymem,OPT|OP_RND},}, | |
467 | { "st","add", 1,2,2,0xC000, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, | |
468 | { "st","ld", 1,2,2,0xC800, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, | |
469 | { "st","ld", 1,2,2,0xE400, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_T}, }, | |
470 | { "st","mac", 1,2,2,0xD000, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, | |
471 | { "st","macr",1,2,2,0xD400, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, | |
472 | { "st","mas", 1,2,2,0xD800, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, | |
473 | { "st","masr",1,2,2,0xDC00, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, | |
474 | { "st","mpy", 1,2,2,0xCC00, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, | |
475 | { "st","sub", 1,2,2,0xC400, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, | |
476 | { NULL,NULL }, | |
477 | }; |