Commit | Line | Data |
---|---|---|
6357e7f6 FF |
1 | /* Opcode table for TI TMS320C80 (MVP). |
2 | Copyright 1996 Free Software Foundation, Inc. | |
3 | ||
4 | This file is part of GDB, GAS, and the GNU binutils. | |
5 | ||
6 | GDB, GAS, and the GNU binutils are free software; you can redistribute | |
7 | them and/or modify them under the terms of the GNU General Public | |
8 | License as published by the Free Software Foundation; either version | |
9 | 1, or (at your option) any later version. | |
10 | ||
11 | GDB, GAS, and the GNU binutils are distributed in the hope that they | |
12 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
13 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
14 | the GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this file; see the file COPYING. If not, write to the Free | |
18 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
19 | ||
872dc6f0 | 20 | #include <stdio.h> |
6357e7f6 FF |
21 | #include "ansidecl.h" |
22 | #include "opcode/tic80.h" | |
872dc6f0 FF |
23 | |
24 | /* This file holds the TMS320C80 (MVP) opcode table. The table is | |
25 | strictly constant data, so the compiler should be able to put it in | |
26 | the .text section. | |
27 | ||
28 | This file also holds the operand table. All knowledge about | |
29 | inserting operands into instructions and vice-versa is kept in this | |
30 | file. */ | |
31 | ||
32 | \f | |
33 | /* The operands table. The fields are: | |
34 | ||
35 | bits, shift, insertion function, extraction function, flags | |
36 | */ | |
37 | ||
38 | const struct tic80_operand tic80_operands[] = | |
39 | { | |
40 | ||
41 | /* The zero index is used to indicate the end of the list of operands. */ | |
42 | ||
43 | #define UNUSED (0) | |
44 | { 0, 0, 0, 0, 0 }, | |
45 | ||
46 | /* Short signed immediate value in bits 14-0. */ | |
47 | ||
48 | #define SSI (UNUSED + 1) | |
49 | { 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED }, | |
50 | ||
51 | /* Short unsigned immediate value in bits 14-0 */ | |
52 | ||
53 | #define SUI (SSI + 1) | |
54 | { 15, 0, NULL, NULL, 0 }, | |
55 | ||
56 | /* Short unsigned bitfield in bits 14-0. We distinguish this | |
57 | from a regular unsigned immediate value only for the convenience | |
58 | of the disassembler and the user. */ | |
59 | ||
60 | #define SUBF (SUI + 1) | |
61 | { 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD }, | |
62 | ||
63 | /* Long signed immediate in following 32 bit word */ | |
64 | ||
65 | #define LSI (SUBF + 1) | |
66 | { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED }, | |
67 | ||
68 | /* Long unsigned immediate in following 32 bit word */ | |
69 | ||
70 | #define LUI (LSI + 1) | |
71 | { 32, 0, NULL, NULL, 0 }, | |
72 | ||
73 | /* Long unsigned bitfield in following 32 bit word. We distinguish | |
74 | this from a regular unsigned immediate value only for the | |
75 | convenience of the disassembler and the user. */ | |
76 | ||
77 | #define LUBF (LUI + 1) | |
78 | { 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD }, | |
79 | ||
003df617 FF |
80 | /* Single precision floating point immediate in following 32 bit |
81 | word. */ | |
82 | ||
83 | #define SPFI (LUBF + 1) | |
84 | { 32, 0, NULL, NULL, TIC80_OPERAND_FLOAT }, | |
85 | ||
872dc6f0 FF |
86 | /* Register in bits 4-0 */ |
87 | ||
003df617 | 88 | #define REG_0 (SPFI + 1) |
872dc6f0 FF |
89 | { 5, 0, NULL, NULL, TIC80_OPERAND_GPR }, |
90 | ||
91 | /* Register in bits 26-22 */ | |
92 | ||
50965d0e | 93 | #define REG_22 (REG_0 + 1) |
872dc6f0 FF |
94 | { 5, 22, NULL, NULL, TIC80_OPERAND_GPR }, |
95 | ||
96 | /* Register in bits 31-27 */ | |
97 | ||
50965d0e | 98 | #define REG_DEST (REG_22 + 1) |
872dc6f0 FF |
99 | { 5, 27, NULL, NULL, TIC80_OPERAND_GPR }, |
100 | ||
5fdeceb4 | 101 | /* Short signed PC word offset in bits 14-0 */ |
1f8c8c60 | 102 | |
5fdeceb4 FF |
103 | #define OFF_SS_PC (REG_DEST + 1) |
104 | { 15, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED }, | |
1f8c8c60 | 105 | |
5fdeceb4 | 106 | /* Long signed PC word offset in following 32 bit word */ |
1f8c8c60 | 107 | |
5fdeceb4 FF |
108 | #define OFF_SL_PC (OFF_SS_PC + 1) |
109 | {32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED }, | |
110 | ||
111 | /* Short signed base relative byte offset in bits 14-0 */ | |
112 | ||
113 | #define OFF_SS_BR (OFF_SL_PC + 1) | |
114 | { 15, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED }, | |
115 | ||
116 | /* Long signed base relative byte offset in following 32 bit word */ | |
117 | ||
118 | #define OFF_SL_BR (OFF_SS_BR + 1) | |
119 | {32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED }, | |
1f8c8c60 FF |
120 | |
121 | /* BITNUM in bits 31-27 */ | |
122 | ||
5fdeceb4 | 123 | #define BITNUM (OFF_SL_BR + 1) |
1f8c8c60 FF |
124 | { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM }, |
125 | ||
126 | /* Condition code in bits 31-27 */ | |
127 | ||
128 | #define CC (BITNUM + 1) | |
129 | { 5, 27, NULL, NULL, TIC80_OPERAND_CC }, | |
130 | ||
131 | /* Control register number in bits 14-0 */ | |
132 | ||
50965d0e | 133 | #define CR_SI (CC + 1) |
1f8c8c60 FF |
134 | { 15, 0, NULL, NULL, TIC80_OPERAND_CR }, |
135 | ||
136 | /* Control register number in next 32 bit word */ | |
137 | ||
50965d0e | 138 | #define CR_LI (CR_SI + 1) |
1f8c8c60 FF |
139 | { 32, 0, NULL, NULL, TIC80_OPERAND_CR }, |
140 | ||
5fdeceb4 FF |
141 | /* A base register in bits 26-22, enclosed in parens */ |
142 | ||
143 | #define REG_BASE (CR_LI + 1) | |
144 | { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS }, | |
145 | ||
50965d0e FF |
146 | /* A base register in bits 26-22, enclosed in parens, with optional ":m" |
147 | flag in bit 17 (short immediate instructions only) */ | |
937fe722 | 148 | |
5fdeceb4 | 149 | #define REG_BASE_M_SI (REG_BASE + 1) |
937fe722 FF |
150 | { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI }, |
151 | ||
50965d0e FF |
152 | /* A base register in bits 26-22, enclosed in parens, with optional ":m" |
153 | flag in bit 15 (long immediate and register instructions only) */ | |
937fe722 | 154 | |
50965d0e | 155 | #define REG_BASE_M_LI (REG_BASE_M_SI + 1) |
937fe722 FF |
156 | { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI }, |
157 | ||
50965d0e FF |
158 | /* Scaled register in bits 4-0, with optional ":s" modifier flag in bit 11 */ |
159 | ||
160 | #define REG_SCALED (REG_BASE_M_LI + 1) | |
161 | { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED }, | |
162 | ||
163 | /* Long signed immediate in following 32 bit word, with optional ":s" modifier | |
164 | flag in bit 11 */ | |
165 | ||
166 | #define LSI_SCALED (REG_SCALED + 1) | |
167 | { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED }, | |
003df617 FF |
168 | |
169 | /* Unsigned immediate in bits 4-0, used only for shift instructions */ | |
170 | ||
171 | #define ROTATE (LSI_SCALED + 1) | |
172 | { 5, 0, NULL, NULL, 0 }, | |
173 | ||
174 | /* Unsigned immediate in bits 9-5, used only for shift instructions */ | |
175 | #define ENDMASK (ROTATE + 1) | |
176 | { 5, 5, NULL, NULL, 0 }, | |
177 | ||
872dc6f0 FF |
178 | }; |
179 | ||
180 | const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands); | |
181 | ||
182 | \f | |
183 | /* Macros used to generate entries for the opcodes table. */ | |
184 | ||
185 | #define FIXME 0 | |
186 | ||
937fe722 | 187 | /* Short-Immediate Format Instructions - basic opcode */ |
872dc6f0 FF |
188 | #define OP_SI(x) (((x) & 0x7F) << 15) |
189 | #define MASK_SI OP_SI(0x7F) | |
872dc6f0 | 190 | |
937fe722 | 191 | /* Long-Immediate Format Instructions - basic opcode */ |
872dc6f0 FF |
192 | #define OP_LI(x) (((x) & 0x3FF) << 12) |
193 | #define MASK_LI OP_LI(0x3FF) | |
872dc6f0 | 194 | |
937fe722 | 195 | /* Register Format Instructions - basic opcode */ |
872dc6f0 FF |
196 | #define OP_REG(x) OP_LI(x) /* For readability */ |
197 | #define MASK_REG MASK_LI /* For readability */ | |
872dc6f0 | 198 | |
003df617 FF |
199 | /* The 'n' bit at bit 10 */ |
200 | #define n(x) ((x) << 10) | |
201 | ||
202 | /* The 'i' bit at bit 11 */ | |
203 | #define i(x) ((x) << 11) | |
204 | ||
937fe722 FF |
205 | /* The 'F' bit at bit 27 */ |
206 | #define F(x) ((x) << 27) | |
207 | ||
50965d0e FF |
208 | /* The 'E' bit at bit 27 */ |
209 | #define E(x) ((x) << 27) | |
210 | ||
937fe722 FF |
211 | /* The 'M' bit at bit 15 in register and long immediate opcodes */ |
212 | #define M_REG(x) ((x) << 15) | |
213 | #define M_LI(x) ((x) << 15) | |
214 | ||
215 | /* The 'M' bit at bit 17 in short immediate opcodes */ | |
216 | #define M_SI(x) ((x) << 17) | |
217 | ||
218 | /* The 'SZ' field at bits 14-13 in register and long immediate opcodes */ | |
219 | #define SZ_REG(x) ((x) << 13) | |
220 | #define SZ_LI(x) ((x) << 13) | |
221 | ||
222 | /* The 'SZ' field at bits 16-15 in short immediate opcodes */ | |
223 | #define SZ_SI(x) ((x) << 15) | |
224 | ||
225 | /* The 'D' (direct external memory access) bit at bit 10 in long immediate | |
226 | and register opcodes. */ | |
227 | #define D(x) ((x) << 10) | |
228 | ||
229 | /* The 'S' (scale offset by data size) bit at bit 11 in long immediate | |
230 | and register opcodes. */ | |
231 | #define S(x) ((x) << 11) | |
232 | ||
003df617 FF |
233 | /* The 'PD' field at bits 10-9 in floating point instructions */ |
234 | #define PD(x) ((x) << 9) | |
235 | ||
236 | /* The 'P2' field at bits 8-7 in floating point instructions */ | |
237 | #define P2(x) ((x) << 7) | |
238 | ||
239 | /* The 'P1' field at bits 6-5 in floating point instructions */ | |
240 | #define P1(x) ((x) << 5) | |
241 | ||
c977d8fb | 242 | /* The 'a' field at bit 16 in vector instructions */ |
68c7761c FF |
243 | #define V_a1(x) ((x) << 16) |
244 | ||
245 | /* The 'a' field at bit 11 in vector instructions */ | |
246 | #define V_a0(x) ((x) << 11) | |
c977d8fb FF |
247 | |
248 | /* The 'm' field at bit 10 in vector instructions */ | |
249 | #define V_m(x) ((x) << 10) | |
250 | ||
251 | /* The 'S' field at bit 9 in vector instructions */ | |
252 | #define V_S(x) ((x) << 9) | |
253 | ||
254 | /* The 'Z' field at bit 8 in vector instructions */ | |
255 | #define V_Z(x) ((x) << 8) | |
256 | ||
257 | /* The 'p' field at bit 6 in vector instructions */ | |
258 | #define V_p(x) ((x) << 6) | |
259 | ||
260 | /* The opcode field at bits 21-17 for vector instructions */ | |
261 | #define OP_V(x) ((x) << 17) | |
262 | #define MASK_V OP_V(0x1F) | |
263 | ||
937fe722 | 264 | \f |
1eb54bb4 FF |
265 | /* The opcode table. Formatted for better readability on a wide screen. Also, all |
266 | entries with the same mnemonic are sorted so that they are adjacent in the table, | |
267 | allowing the use of a hash table to locate the first of a sequence of opcodes that have | |
268 | a particular name. */ | |
5fdeceb4 | 269 | |
872dc6f0 FF |
270 | const struct tic80_opcode tic80_opcodes[] = { |
271 | ||
1f8c8c60 | 272 | /* The "nop" instruction is really "rdcr 0,r0". We put it first so that this |
937fe722 | 273 | specific bit pattern will get disassembled as a nop rather than an rdcr. The |
1f8c8c60 FF |
274 | mask of all ones ensures that this will happen. */ |
275 | ||
276 | {"nop", OP_SI(0x4), ~0, 0, {0} }, | |
277 | ||
278 | /* The "br" instruction is really "bbz target,r0,31". We put it first so that | |
279 | this specific bit pattern will get disassembled as a br rather than bbz. */ | |
280 | ||
1eb54bb4 FF |
281 | {"br", OP_LI(0x391), 0xFFFFF000, 0, {OFF_SL_PC} }, |
282 | {"br", OP_REG(0x390), 0xFFFFF000, 0, {REG_0} }, | |
283 | {"br", OP_SI(0x48), 0xFFFF8000, 0, {OFF_SS_PC} }, | |
284 | {"br.a", OP_LI(0x393), 0xFFFFF000, 0, {OFF_SL_PC} }, | |
285 | {"br.a", OP_REG(0x392), 0xFFFFF000, 0, {REG_0} }, | |
286 | {"br.a", OP_SI(0x49), 0xFFFF8000, 0, {OFF_SS_PC} }, | |
1f8c8c60 | 287 | |
872dc6f0 FF |
288 | /* Signed integer ADD */ |
289 | ||
1eb54bb4 | 290 | {"add", OP_LI(0x3B1), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, |
c977d8fb | 291 | {"add", OP_REG(0x3B0), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, |
1eb54bb4 | 292 | {"add", OP_SI(0x58), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, |
872dc6f0 FF |
293 | |
294 | /* Unsigned integer ADD */ | |
295 | ||
1eb54bb4 | 296 | {"addu", OP_LI(0x3B3), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, |
c977d8fb | 297 | {"addu", OP_REG(0x3B2), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, |
1eb54bb4 | 298 | {"addu", OP_SI(0x59), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, |
872dc6f0 FF |
299 | |
300 | /* Bitwise AND */ | |
301 | ||
c977d8fb | 302 | {"and", OP_LI(0x323), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, |
1eb54bb4 FF |
303 | {"and", OP_REG(0x322), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, |
304 | {"and", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, | |
c977d8fb | 305 | {"and.tt", OP_LI(0x323), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, |
1eb54bb4 FF |
306 | {"and.tt", OP_REG(0x322), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, |
307 | {"and.tt", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, | |
872dc6f0 FF |
308 | |
309 | /* Bitwise AND with ones complement of both sources */ | |
310 | ||
c977d8fb | 311 | {"and.ff", OP_LI(0x331), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, |
1eb54bb4 FF |
312 | {"and.ff", OP_REG(0x330), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, |
313 | {"and.ff", OP_SI(0x18), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, | |
872dc6f0 FF |
314 | |
315 | /* Bitwise AND with ones complement of source 1 */ | |
316 | ||
c977d8fb | 317 | {"and.ft", OP_LI(0x329), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, |
1eb54bb4 FF |
318 | {"and.ft", OP_REG(0x328), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, |
319 | {"and.ft", OP_SI(0x14), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, | |
872dc6f0 FF |
320 | |
321 | /* Bitwise AND with ones complement of source 2 */ | |
322 | ||
c977d8fb | 323 | {"and.tf", OP_LI(0x325), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, |
1eb54bb4 FF |
324 | {"and.tf", OP_REG(0x324), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, |
325 | {"and.tf", OP_SI(0x12), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, | |
872dc6f0 | 326 | |
1f8c8c60 FF |
327 | /* Branch Bit One - nonannulled */ |
328 | ||
c977d8fb | 329 | {"bbo", OP_LI(0x395), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, |
1eb54bb4 FF |
330 | {"bbo", OP_REG(0x394), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, |
331 | {"bbo", OP_SI(0x4A), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, | |
1f8c8c60 FF |
332 | |
333 | /* Branch Bit One - annulled */ | |
334 | ||
c977d8fb | 335 | {"bbo.a", OP_LI(0x397), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, |
1eb54bb4 FF |
336 | {"bbo.a", OP_REG(0x396), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, |
337 | {"bbo.a", OP_SI(0x4B), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, | |
1f8c8c60 FF |
338 | |
339 | /* Branch Bit Zero - nonannulled */ | |
340 | ||
c977d8fb | 341 | {"bbz", OP_LI(0x391), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, |
1eb54bb4 FF |
342 | {"bbz", OP_REG(0x390), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, |
343 | {"bbz", OP_SI(0x48), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, | |
1f8c8c60 FF |
344 | |
345 | /* Branch Bit Zero - annulled */ | |
346 | ||
c977d8fb | 347 | {"bbz.a", OP_LI(0x393), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, |
1eb54bb4 FF |
348 | {"bbz.a", OP_REG(0x392), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, |
349 | {"bbz.a", OP_SI(0x49), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, | |
1f8c8c60 FF |
350 | |
351 | /* Branch Conditional - nonannulled */ | |
352 | ||
c977d8fb | 353 | {"bcnd", OP_LI(0x399), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} }, |
1eb54bb4 FF |
354 | {"bcnd", OP_REG(0x398), MASK_REG, 0, {REG_0, REG_22, CC} }, |
355 | {"bcnd", OP_SI(0x4C), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} }, | |
1f8c8c60 FF |
356 | |
357 | /* Branch Conditional - annulled */ | |
358 | ||
c977d8fb | 359 | {"bcnd.a", OP_LI(0x39B), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} }, |
1eb54bb4 FF |
360 | {"bcnd.a", OP_REG(0x39A), MASK_REG, 0, {REG_0, REG_22, CC} }, |
361 | {"bcnd.a", OP_SI(0x4D), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} }, | |
1f8c8c60 FF |
362 | |
363 | /* Branch Control Register */ | |
364 | ||
1eb54bb4 FF |
365 | {"brcr", OP_LI(0x30D), MASK_LI, 0, {CR_LI} }, |
366 | {"brcr", OP_REG(0x30C), MASK_REG, 0, {REG_0} }, | |
367 | {"brcr", OP_SI(0x6), MASK_SI, 0, {CR_SI} }, | |
1f8c8c60 | 368 | |
937fe722 FF |
369 | /* Branch and save return - nonannulled */ |
370 | ||
c977d8fb | 371 | {"bsr", OP_LI(0x381), MASK_LI, 0, {OFF_SL_PC, REG_DEST} }, |
1eb54bb4 FF |
372 | {"bsr", OP_REG(0x380), MASK_REG, 0, {REG_0, REG_DEST} }, |
373 | {"bsr", OP_SI(0x40), MASK_SI, 0, {OFF_SS_PC, REG_DEST} }, | |
937fe722 FF |
374 | |
375 | /* Branch and save return - annulled */ | |
376 | ||
c977d8fb | 377 | {"bsr.a", OP_LI(0x383), MASK_LI, 0, {OFF_SL_PC, REG_DEST} }, |
1eb54bb4 FF |
378 | {"bsr.a", OP_REG(0x382), MASK_REG, 0, {REG_0, REG_DEST} }, |
379 | {"bsr.a", OP_SI(0x41), MASK_SI, 0, {OFF_SS_PC, REG_DEST} }, | |
937fe722 FF |
380 | |
381 | /* Send command */ | |
382 | ||
1eb54bb4 FF |
383 | {"cmnd", OP_LI(0x305), MASK_LI, 0, {LUI} }, |
384 | {"cmnd", OP_REG(0x304), MASK_REG, 0, {REG_0} }, | |
385 | {"cmnd", OP_SI(0x2), MASK_SI, 0, {SUI} }, | |
937fe722 FF |
386 | |
387 | /* Integer compare */ | |
388 | ||
c977d8fb | 389 | {"cmp", OP_LI(0x3A1), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, |
1eb54bb4 FF |
390 | {"cmp", OP_REG(0x3A0), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, |
391 | {"cmp", OP_SI(0x50), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, | |
937fe722 FF |
392 | |
393 | /* Flush data cache subblock - don't clear subblock preset flag */ | |
394 | ||
1eb54bb4 | 395 | {"dcachec", OP_LI(0x371), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), 0, {LSI, REG_BASE_M_LI} }, |
c977d8fb | 396 | {"dcachec", OP_REG(0x370), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), 0, {REG_0, REG_BASE_M_LI} }, |
1eb54bb4 | 397 | {"dcachec", OP_SI(0x38), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} }, |
937fe722 FF |
398 | |
399 | /* Flush data cache subblock - clear subblock preset flag */ | |
400 | ||
1eb54bb4 | 401 | {"dcachef", OP_LI(0x371) | F(1), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), 0, {LSI, REG_BASE_M_LI} }, |
c977d8fb | 402 | {"dcachef", OP_REG(0x370) | F(1), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), 0, {REG_0, REG_BASE_M_LI} }, |
1eb54bb4 | 403 | {"dcachef", OP_SI(0x38) | F(1), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} }, |
50965d0e FF |
404 | |
405 | /* Direct load signed data into register */ | |
406 | ||
1eb54bb4 | 407 | {"dld", OP_LI(0x345) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, |
c977d8fb | 408 | {"dld", OP_REG(0x344) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, |
1eb54bb4 FF |
409 | {"dld.b", OP_LI(0x341) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, |
410 | {"dld.b", OP_REG(0x340) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
411 | {"dld.d", OP_LI(0x347) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
c977d8fb | 412 | {"dld.d", OP_REG(0x346) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, |
1eb54bb4 FF |
413 | {"dld.h", OP_LI(0x343) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, |
414 | {"dld.h", OP_REG(0x342) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
50965d0e FF |
415 | |
416 | /* Direct load unsigned data into register */ | |
417 | ||
1eb54bb4 FF |
418 | {"dld.ub", OP_LI(0x351) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, |
419 | {"dld.ub", OP_REG(0x350) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
420 | {"dld.uh", OP_LI(0x353) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
421 | {"dld.uh", OP_REG(0x352) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
50965d0e FF |
422 | |
423 | /* Direct store data into memory */ | |
424 | ||
1eb54bb4 | 425 | {"dst", OP_LI(0x365) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, |
c977d8fb | 426 | {"dst", OP_REG(0x364) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, |
1eb54bb4 FF |
427 | {"dst.b", OP_LI(0x361) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, |
428 | {"dst.b", OP_REG(0x360) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
429 | {"dst.d", OP_LI(0x367) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
c977d8fb | 430 | {"dst.d", OP_REG(0x366) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, |
1eb54bb4 FF |
431 | {"dst.h", OP_LI(0x363) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, |
432 | {"dst.h", OP_REG(0x362) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
50965d0e FF |
433 | |
434 | /* Emulation stop */ | |
435 | ||
c977d8fb | 436 | {"estop", OP_LI(0x3FC), MASK_LI, 0, {0} }, |
50965d0e FF |
437 | |
438 | /* Emulation trap */ | |
439 | ||
1eb54bb4 | 440 | {"etrap", OP_LI(0x303) | E(1), MASK_LI | E(1), 0, {LUI} }, |
c977d8fb | 441 | {"etrap", OP_REG(0x302) | E(1), MASK_REG | E(1), 0, {REG_0} }, |
1eb54bb4 | 442 | {"etrap", OP_SI(0x1) | E(1), MASK_SI | E(1), 0, {SUI} }, |
003df617 FF |
443 | |
444 | /* Floating-point addition */ | |
445 | ||
c977d8fb | 446 | {"fadd.ddd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, |
1eb54bb4 FF |
447 | {"fadd.dsd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, |
448 | {"fadd.sdd", OP_LI(0x3E1) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, | |
449 | {"fadd.sdd", OP_REG(0x3E0) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, | |
450 | {"fadd.ssd", OP_LI(0x3E1) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, | |
451 | {"fadd.ssd", OP_REG(0x3E0) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, | |
452 | {"fadd.sss", OP_LI(0x3E1) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, | |
453 | {"fadd.sss", OP_REG(0x3E0) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, | |
003df617 | 454 | |
5fdeceb4 | 455 | /* Floating point compare */ |
003df617 | 456 | |
c977d8fb | 457 | {"fcmp.dd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, |
1eb54bb4 FF |
458 | {"fcmp.ds", OP_REG(0x3EA) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, |
459 | {"fcmp.sd", OP_LI(0x3EB) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, | |
460 | {"fcmp.sd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, | |
461 | {"fcmp.ss", OP_LI(0x3EB) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, | |
462 | {"fcmp.ss", OP_REG(0x3EA) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, | |
5fdeceb4 | 463 | |
003df617 FF |
464 | /* Floating point divide */ |
465 | ||
c977d8fb | 466 | {"fdiv.ddd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, |
1eb54bb4 FF |
467 | {"fdiv.dsd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, |
468 | {"fdiv.sdd", OP_LI(0x3E7) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, | |
469 | {"fdiv.sdd", OP_REG(0x3E6) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, | |
470 | {"fdiv.ssd", OP_LI(0x3E7) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, | |
471 | {"fdiv.ssd", OP_REG(0x3E6) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, | |
472 | {"fdiv.sss", OP_LI(0x3E7) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, | |
473 | {"fdiv.sss", OP_REG(0x3E6) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, | |
003df617 | 474 | |
5fdeceb4 FF |
475 | /* Floating point multiply */ |
476 | ||
c977d8fb | 477 | {"fmpy.ddd", OP_REG(0x3E4) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, |
1eb54bb4 FF |
478 | {"fmpy.dsd", OP_REG(0x3E4) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, |
479 | {"fmpy.iii", OP_LI(0x3E5) | PD(2) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_22, REG_DEST} }, | |
c977d8fb | 480 | {"fmpy.iii", OP_REG(0x3E4) | PD(2) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, |
1eb54bb4 FF |
481 | {"fmpy.sdd", OP_LI(0x3E5) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, |
482 | {"fmpy.sdd", OP_REG(0x3E4) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, | |
483 | {"fmpy.ssd", OP_LI(0x3E5) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, | |
484 | {"fmpy.ssd", OP_REG(0x3E4) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, | |
485 | {"fmpy.sss", OP_LI(0x3E5) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, | |
486 | {"fmpy.sss", OP_REG(0x3E4) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, | |
487 | {"fmpy.uuu", OP_LI(0x3E5) | PD(3) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LUI, REG_22, REG_DEST} }, | |
c977d8fb | 488 | {"fmpy.uuu", OP_REG(0x3E4) | PD(3) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, |
5fdeceb4 | 489 | |
c977d8fb | 490 | /* Convert/Round to Minus Infinity */ |
5fdeceb4 | 491 | |
c977d8fb FF |
492 | {"frndm.dd", OP_REG(0x3E8) | PD(1) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
493 | {"frndm.di", OP_REG(0x3E8) | PD(2) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
1eb54bb4 | 494 | {"frndm.ds", OP_REG(0x3E8) | PD(0) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
c977d8fb | 495 | {"frndm.du", OP_REG(0x3E8) | PD(3) | P2(3) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
1eb54bb4 | 496 | {"frndm.id", OP_LI(0x3E9) | PD(1) | P2(3) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, |
c977d8fb | 497 | {"frndm.id", OP_REG(0x3E8) | PD(1) | P2(3) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
1eb54bb4 FF |
498 | {"frndm.is", OP_LI(0x3E9) | PD(0) | P2(3) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, |
499 | {"frndm.is", OP_REG(0x3E8) | PD(0) | P2(3) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
500 | {"frndm.sd", OP_LI(0x3E9) | PD(1) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, | |
501 | {"frndm.sd", OP_REG(0x3E8) | PD(1) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
502 | {"frndm.si", OP_LI(0x3E9) | PD(2) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, | |
503 | {"frndm.si", OP_REG(0x3E8) | PD(2) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
504 | {"frndm.ss", OP_LI(0x3E9) | PD(0) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, | |
505 | {"frndm.ss", OP_REG(0x3E8) | PD(0) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
506 | {"frndm.su", OP_LI(0x3E9) | PD(3) | P2(3) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, | |
507 | {"frndm.su", OP_REG(0x3E8) | PD(3) | P2(3) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
508 | {"frndm.ud", OP_LI(0x3E9) | PD(1) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, | |
c977d8fb | 509 | {"frndm.ud", OP_REG(0x3E8) | PD(1) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
1eb54bb4 FF |
510 | {"frndm.us", OP_LI(0x3E9) | PD(0) | P2(3) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, |
511 | {"frndm.us", OP_REG(0x3E8) | PD(0) | P2(3) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
5fdeceb4 FF |
512 | |
513 | /* Convert/Round to Nearest */ | |
514 | ||
c977d8fb FF |
515 | {"frndn.dd", OP_REG(0x3E8) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
516 | {"frndn.di", OP_REG(0x3E8) | PD(2) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
1eb54bb4 | 517 | {"frndn.ds", OP_REG(0x3E8) | PD(0) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
c977d8fb | 518 | {"frndn.du", OP_REG(0x3E8) | PD(3) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
1eb54bb4 | 519 | {"frndn.id", OP_LI(0x3E9) | PD(1) | P2(0) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, |
c977d8fb | 520 | {"frndn.id", OP_REG(0x3E8) | PD(1) | P2(0) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
1eb54bb4 FF |
521 | {"frndn.is", OP_LI(0x3E9) | PD(0) | P2(0) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, |
522 | {"frndn.is", OP_REG(0x3E8) | PD(0) | P2(0) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
523 | {"frndn.sd", OP_LI(0x3E9) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, | |
524 | {"frndn.sd", OP_REG(0x3E8) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
525 | {"frndn.si", OP_LI(0x3E9) | PD(2) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, | |
526 | {"frndn.si", OP_REG(0x3E8) | PD(2) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
527 | {"frndn.ss", OP_LI(0x3E9) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, | |
528 | {"frndn.ss", OP_REG(0x3E8) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
529 | {"frndn.su", OP_LI(0x3E9) | PD(3) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, | |
530 | {"frndn.su", OP_REG(0x3E8) | PD(3) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
531 | {"frndn.ud", OP_LI(0x3E9) | PD(1) | P2(0) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, | |
c977d8fb | 532 | {"frndn.ud", OP_REG(0x3E8) | PD(1) | P2(0) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
1eb54bb4 FF |
533 | {"frndn.us", OP_LI(0x3E9) | PD(0) | P2(0) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, |
534 | {"frndn.us", OP_REG(0x3E8) | PD(0) | P2(0) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
5fdeceb4 FF |
535 | |
536 | /* Convert/Round to Positive Infinity */ | |
537 | ||
c977d8fb FF |
538 | {"frndp.dd", OP_REG(0x3E8) | PD(1) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
539 | {"frndp.di", OP_REG(0x3E8) | PD(2) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
1eb54bb4 | 540 | {"frndp.ds", OP_REG(0x3E8) | PD(0) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
c977d8fb | 541 | {"frndp.du", OP_REG(0x3E8) | PD(3) | P2(2) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
1eb54bb4 | 542 | {"frndp.id", OP_LI(0x3E9) | PD(1) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, |
c977d8fb | 543 | {"frndp.id", OP_REG(0x3E8) | PD(1) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
1eb54bb4 FF |
544 | {"frndp.is", OP_LI(0x3E9) | PD(0) | P2(2) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, |
545 | {"frndp.is", OP_REG(0x3E8) | PD(0) | P2(2) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
546 | {"frndp.sd", OP_LI(0x3E9) | PD(1) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, | |
547 | {"frndp.sd", OP_REG(0x3E8) | PD(1) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
548 | {"frndp.si", OP_LI(0x3E9) | PD(2) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, | |
549 | {"frndp.si", OP_REG(0x3E8) | PD(2) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
550 | {"frndp.ss", OP_LI(0x3E9) | PD(0) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, | |
551 | {"frndp.ss", OP_REG(0x3E8) | PD(0) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
552 | {"frndp.su", OP_LI(0x3E9) | PD(3) | P2(2) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, | |
553 | {"frndp.su", OP_REG(0x3E8) | PD(3) | P2(2) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
554 | {"frndp.ud", OP_LI(0x3E9) | PD(1) | P2(2) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, | |
c977d8fb | 555 | {"frndp.ud", OP_REG(0x3E8) | PD(1) | P2(2) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
1eb54bb4 FF |
556 | {"frndp.us", OP_LI(0x3E9) | PD(0) | P2(2) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, |
557 | {"frndp.us", OP_REG(0x3E8) | PD(0) | P2(2) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
5fdeceb4 FF |
558 | |
559 | /* Convert/Round to Zero */ | |
560 | ||
c977d8fb FF |
561 | {"frndz.dd", OP_REG(0x3E8) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
562 | {"frndz.di", OP_REG(0x3E8) | PD(2) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
1eb54bb4 | 563 | {"frndz.ds", OP_REG(0x3E8) | PD(0) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
c977d8fb | 564 | {"frndz.du", OP_REG(0x3E8) | PD(3) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
1eb54bb4 | 565 | {"frndz.id", OP_LI(0x3E9) | PD(1) | P2(1) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, |
c977d8fb | 566 | {"frndz.id", OP_REG(0x3E8) | PD(1) | P2(1) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
1eb54bb4 FF |
567 | {"frndz.is", OP_LI(0x3E9) | PD(0) | P2(1) | P1(2), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, |
568 | {"frndz.is", OP_REG(0x3E8) | PD(0) | P2(1) | P1(2), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
569 | {"frndz.sd", OP_LI(0x3E9) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, | |
570 | {"frndz.sd", OP_REG(0x3E8) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
571 | {"frndz.si", OP_LI(0x3E9) | PD(2) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, | |
572 | {"frndz.si", OP_REG(0x3E8) | PD(2) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
573 | {"frndz.ss", OP_LI(0x3E9) | PD(0) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, | |
574 | {"frndz.ss", OP_REG(0x3E8) | PD(0) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
575 | {"frndz.su", OP_LI(0x3E9) | PD(3) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, | |
576 | {"frndz.su", OP_REG(0x3E8) | PD(3) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
577 | {"frndz.ud", OP_LI(0x3E9) | PD(1) | P2(1) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, | |
c977d8fb | 578 | {"frndz.ud", OP_REG(0x3E8) | PD(1) | P2(1) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
1eb54bb4 FF |
579 | {"frndz.us", OP_LI(0x3E9) | PD(0) | P2(1) | P1(3), MASK_LI | PD(3) | P2(3) | P1(3), 0, {LSI, REG_DEST} }, |
580 | {"frndz.us", OP_REG(0x3E8) | PD(0) | P2(1) | P1(3), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
5fdeceb4 FF |
581 | |
582 | /* Floating point square root */ | |
583 | ||
c977d8fb | 584 | {"fsqrt.dd", OP_REG(0x3EE) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, |
1eb54bb4 FF |
585 | {"fsqrt.sd", OP_LI(0x3EF) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, |
586 | {"fsqrt.sd", OP_REG(0x3EE) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
587 | {"fsqrt.ss", OP_LI(0x3EF) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_DEST} }, | |
588 | {"fsqrt.ss", OP_REG(0x3EE) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_DEST} }, | |
5fdeceb4 FF |
589 | |
590 | /* Floating point subtraction */ | |
591 | ||
c977d8fb | 592 | { "fsub.ddd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, |
1eb54bb4 FF |
593 | { "fsub.dsd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(1), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, |
594 | { "fsub.sdd", OP_LI(0x3E3) | PD(1) | P2(1) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, | |
595 | { "fsub.sdd", OP_REG(0x3E2) | PD(1) | P2(1) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, | |
596 | { "fsub.ssd", OP_LI(0x3E3) | PD(1) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, | |
597 | { "fsub.ssd", OP_REG(0x3E2) | PD(1) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, | |
598 | { "fsub.sss", OP_LI(0x3E3) | PD(0) | P2(0) | P1(0), MASK_LI | PD(3) | P2(3) | P1(3), 0, {SPFI, REG_22, REG_DEST} }, | |
599 | { "fsub.sss", OP_REG(0x3E2) | PD(0) | P2(0) | P1(0), MASK_REG | PD(3) | P2(3) | P1(3), 0, {REG_0, REG_22, REG_DEST} }, | |
5fdeceb4 FF |
600 | |
601 | /* Illegal instructions */ | |
602 | ||
1eb54bb4 FF |
603 | {"illop0", OP_SI(0x0), MASK_SI, 0, {0} }, |
604 | {"illopF", 0x1FF << 13, 0x1FF << 13, 0, {0} }, | |
5fdeceb4 FF |
605 | |
606 | /* Jump and save return */ | |
607 | ||
c977d8fb | 608 | {"jsr", OP_LI(0x389), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} }, |
1eb54bb4 FF |
609 | {"jsr", OP_REG(0x388), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} }, |
610 | {"jsr", OP_SI(0x44), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, | |
c977d8fb | 611 | {"jsr.a", OP_LI(0x38B), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} }, |
1eb54bb4 FF |
612 | {"jsr.a", OP_REG(0x38A), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} }, |
613 | {"jsr.a", OP_SI(0x45), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, | |
5fdeceb4 FF |
614 | |
615 | /* Load Signed Data Into Register */ | |
616 | ||
1eb54bb4 | 617 | {"ld", OP_LI(0x345) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, |
c977d8fb | 618 | {"ld", OP_REG(0x344) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, |
1eb54bb4 FF |
619 | {"ld", OP_SI(0x22), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST} }, |
620 | {"ld.b", OP_LI(0x341) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
621 | {"ld.b", OP_REG(0x340) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
622 | {"ld.b", OP_SI(0x20), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST} }, | |
623 | {"ld.d", OP_LI(0x347) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
c977d8fb | 624 | {"ld.d", OP_REG(0x346) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, |
1eb54bb4 FF |
625 | {"ld.d", OP_SI(0x23), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST} }, |
626 | {"ld.h", OP_LI(0x343) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
627 | {"ld.h", OP_REG(0x342) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
628 | {"ld.h", OP_SI(0x21), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST} }, | |
5fdeceb4 FF |
629 | |
630 | /* Load Unsigned Data Into Register */ | |
631 | ||
1eb54bb4 | 632 | {"ld.ub", OP_LI(0x351) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, |
c977d8fb | 633 | {"ld.ub", OP_REG(0x350) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, |
1eb54bb4 FF |
634 | {"ld.ub", OP_SI(0x28), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST} }, |
635 | {"ld.uh", OP_LI(0x353) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
c977d8fb | 636 | {"ld.uh", OP_REG(0x352) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, |
1eb54bb4 | 637 | {"ld.uh", OP_SI(0x29), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST} }, |
5fdeceb4 FF |
638 | |
639 | /* Leftmost one */ | |
640 | ||
c977d8fb | 641 | {"lmo", OP_LI(0x3F0), MASK_LI, 0, {REG_22, REG_DEST} }, |
5fdeceb4 FF |
642 | |
643 | /* Bitwise logical OR */ | |
644 | ||
c977d8fb | 645 | {"or.ff", OP_LI(0x33D), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, |
1eb54bb4 FF |
646 | {"or.ff", OP_REG(0x33C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, |
647 | {"or.ff", OP_SI(0x1E), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, | |
c977d8fb | 648 | {"or.ft", OP_LI(0x33B), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, |
1eb54bb4 FF |
649 | {"or.ft", OP_REG(0x33A), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, |
650 | {"or.ft", OP_SI(0x1D), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, | |
c977d8fb | 651 | {"or.tf", OP_LI(0x337), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, |
1eb54bb4 FF |
652 | {"or.tf", OP_REG(0x336), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, |
653 | {"or.tf", OP_SI(0x1B), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, | |
c977d8fb | 654 | {"or.tt", OP_LI(0x32F), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, |
1eb54bb4 FF |
655 | {"or.tt", OP_REG(0x32E), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, |
656 | {"or.tt", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, | |
5fdeceb4 FF |
657 | |
658 | /* Read Control Register */ | |
659 | ||
1eb54bb4 | 660 | {"rdcr", OP_LI(0x309), MASK_LI | (0x1F << 22), 0, {CR_LI, REG_DEST} }, |
c977d8fb | 661 | {"rdcr", OP_REG(0x308), MASK_REG | (0x1F << 22), 0, {REG_0, REG_DEST} }, |
1eb54bb4 | 662 | {"rdcr", OP_SI(0x4), MASK_SI | (0x1F << 22), 0, {CR_SI, REG_DEST} }, |
5fdeceb4 FF |
663 | |
664 | /* Rightmost one */ | |
665 | ||
c977d8fb | 666 | {"rmo", OP_LI(0x3F2), MASK_LI, 0, {REG_22, REG_DEST} }, |
5fdeceb4 FF |
667 | |
668 | /* Shift Register Left - note that rotl, shl, and ins are all alternate names for one of the shift instructions. | |
669 | They appear prior to their sl equivalent so that they will be diassembled as the alternate name. */ | |
670 | ||
c977d8fb | 671 | |
1eb54bb4 FF |
672 | {"ins", OP_REG(0x31E) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
673 | {"ins", OP_SI(0xF) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, | |
c977d8fb | 674 | {"rotl", OP_REG(0x310) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 FF |
675 | {"rotl", OP_SI(0x8) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
676 | {"shl", OP_REG(0x31C) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, | |
677 | {"shl", OP_SI(0xE) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, | |
c977d8fb | 678 | {"sl.dm", OP_REG(0x312) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 | 679 | {"sl.dm", OP_SI(0x9) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
c977d8fb | 680 | {"sl.ds", OP_REG(0x314) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 FF |
681 | {"sl.ds", OP_SI(0xA) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
682 | {"sl.dz", OP_REG(0x310) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, | |
683 | {"sl.dz", OP_SI(0x8) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, | |
c977d8fb | 684 | {"sl.em", OP_REG(0x318) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 | 685 | {"sl.em", OP_SI(0xC) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
c977d8fb | 686 | {"sl.es", OP_REG(0x31A) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 FF |
687 | {"sl.es", OP_SI(0xD) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
688 | {"sl.ez", OP_REG(0x316) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, | |
689 | {"sl.ez", OP_SI(0xB) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, | |
c977d8fb | 690 | {"sl.im", OP_REG(0x31E) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 FF |
691 | {"sl.im", OP_SI(0xF) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
692 | {"sl.iz", OP_REG(0x31C) | i(0) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, | |
693 | {"sl.iz", OP_SI(0xE) | i(0) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, | |
5fdeceb4 FF |
694 | |
695 | /* Shift Register Left With Inverted Endmask */ | |
696 | ||
c977d8fb | 697 | {"sli.dm", OP_REG(0x312) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 | 698 | {"sli.dm", OP_SI(0x9) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
c977d8fb | 699 | {"sli.ds", OP_REG(0x314) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 FF |
700 | {"sli.ds", OP_SI(0xA) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
701 | {"sli.dz", OP_REG(0x310) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, | |
702 | {"sli.dz", OP_SI(0x8) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, | |
c977d8fb | 703 | {"sli.em", OP_REG(0x318) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 | 704 | {"sli.em", OP_SI(0xC) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
c977d8fb | 705 | {"sli.es", OP_REG(0x31A) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 FF |
706 | {"sli.es", OP_SI(0xD) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
707 | {"sli.ez", OP_REG(0x316) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, | |
708 | {"sli.ez", OP_SI(0xB) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, | |
c977d8fb | 709 | {"sli.im", OP_REG(0x31E) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 FF |
710 | {"sli.im", OP_SI(0xF) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
711 | {"sli.iz", OP_REG(0x31C) | i(1) | n(0), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, | |
712 | {"sli.iz", OP_SI(0xE) | i(1) | n(0), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, | |
5fdeceb4 FF |
713 | |
714 | /* Shift Register Right - note that exts, extu, rotr, sra, and srl are all alternate names for one of the shift instructions. | |
715 | They appear prior to their sr equivalent so that they will be diassembled as the alternate name. */ | |
716 | ||
1eb54bb4 FF |
717 | {"exts", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
718 | {"exts", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, | |
c977d8fb | 719 | {"extu", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 FF |
720 | {"extu", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
721 | {"rotr", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, | |
722 | {"rotr", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, | |
723 | {"sra", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, | |
724 | {"sra", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, | |
725 | {"srl", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, | |
726 | {"srl", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, | |
c977d8fb | 727 | {"sr.dm", OP_REG(0x312) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 | 728 | {"sr.dm", OP_SI(0x9) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
c977d8fb | 729 | {"sr.ds", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 FF |
730 | {"sr.ds", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
731 | {"sr.dz", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, | |
732 | {"sr.dz", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, | |
c977d8fb | 733 | {"sr.em", OP_REG(0x318) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 | 734 | {"sr.em", OP_SI(0xC) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
c977d8fb | 735 | {"sr.es", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 FF |
736 | {"sr.es", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
737 | {"sr.ez", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, | |
738 | {"sr.ez", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, | |
c977d8fb | 739 | {"sr.im", OP_REG(0x31E) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 FF |
740 | {"sr.im", OP_SI(0xF) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
741 | {"sr.iz", OP_REG(0x31C) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, | |
742 | {"sr.iz", OP_SI(0xE) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, | |
5fdeceb4 FF |
743 | |
744 | /* Shift Register Right With Inverted Endmask */ | |
745 | ||
c977d8fb | 746 | {"sri.dm", OP_REG(0x312) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 | 747 | {"sri.dm", OP_SI(0x9) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
c977d8fb | 748 | {"sri.ds", OP_REG(0x314) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 FF |
749 | {"sri.ds", OP_SI(0xA) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
750 | {"sri.dz", OP_REG(0x310) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, | |
751 | {"sri.dz", OP_SI(0x8) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, | |
c977d8fb | 752 | {"sri.em", OP_REG(0x318) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 | 753 | {"sri.em", OP_SI(0xC) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
c977d8fb | 754 | {"sri.es", OP_REG(0x31A) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 FF |
755 | {"sri.es", OP_SI(0xD) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
756 | {"sri.ez", OP_REG(0x316) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, | |
757 | {"sri.ez", OP_SI(0xB) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, | |
c977d8fb | 758 | {"sri.im", OP_REG(0x31E) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, |
1eb54bb4 FF |
759 | {"sri.im", OP_SI(0xF) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, |
760 | {"sri.iz", OP_REG(0x31C) | i(1) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} }, | |
761 | {"sri.iz", OP_SI(0xE) | i(1) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} }, | |
5fdeceb4 FF |
762 | |
763 | /* Store Data into Memory */ | |
764 | ||
1eb54bb4 | 765 | {"st", OP_LI(0x365) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, |
c977d8fb | 766 | {"st", OP_REG(0x364) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, |
1eb54bb4 FF |
767 | {"st", OP_SI(0x32), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST}}, |
768 | {"st.b", OP_LI(0x361) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
769 | {"st.b", OP_REG(0x360) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
770 | {"st.b", OP_SI(0x30), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST}}, | |
771 | {"st.d", OP_LI(0x367) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
c977d8fb | 772 | {"st.d", OP_REG(0x366) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, |
1eb54bb4 FF |
773 | {"st.d", OP_SI(0x33), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST}}, |
774 | {"st.h", OP_LI(0x363) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
775 | {"st.h", OP_REG(0x362) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, | |
776 | {"st.h", OP_SI(0x31), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST}}, | |
5fdeceb4 FF |
777 | |
778 | /* Signed Integer Subtract */ | |
779 | ||
c977d8fb | 780 | {"sub", OP_LI(0x3B5), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, |
1eb54bb4 FF |
781 | {"sub", OP_REG(0x3B4), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, |
782 | {"sub", OP_SI(0x5A), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, | |
5fdeceb4 FF |
783 | |
784 | /* Unsigned Integer Subtract */ | |
785 | ||
c977d8fb | 786 | {"subu", OP_LI(0x3B7), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, |
1eb54bb4 FF |
787 | {"subu", OP_REG(0x3B6), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, |
788 | {"subu", OP_SI(0x5B), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, | |
5fdeceb4 | 789 | |
68c7761c FF |
790 | /* Write Control Register |
791 | Is a special form of the "swcr" instruction so comes before it in the table. */ | |
792 | ||
68c7761c | 793 | {"wrcr", OP_LI(0x30B), MASK_LI | (0x1F << 27), 0, {CR_LI, REG_22} }, |
1eb54bb4 FF |
794 | {"wrcr", OP_REG(0x30A), MASK_REG | (0x1F << 27), 0, {REG_0, REG_22} }, |
795 | {"wrcr", OP_SI(0x5), MASK_SI | (0x1F << 27), 0, {CR_SI, REG_22} }, | |
68c7761c | 796 | |
5fdeceb4 FF |
797 | /* Swap Control Register */ |
798 | ||
c977d8fb | 799 | {"swcr", OP_LI(0x30B), MASK_LI, 0, {CR_LI, REG_22, REG_DEST} }, |
1eb54bb4 FF |
800 | {"swcr", OP_REG(0x30A), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, |
801 | {"swcr", OP_SI(0x5), MASK_SI, 0, {CR_SI, REG_22, REG_DEST} }, | |
5fdeceb4 FF |
802 | |
803 | /* Trap */ | |
804 | ||
1eb54bb4 | 805 | {"trap", OP_LI(0x303) | E(0), MASK_LI | E(1), 0, {LUI} }, |
c977d8fb | 806 | {"trap", OP_REG(0x302) | E(0), MASK_REG | E(1), 0, {REG_0} }, |
1eb54bb4 | 807 | {"trap", OP_SI(0x1) | E(0), MASK_SI | E(1), 0, {SUI} }, |
c977d8fb FF |
808 | |
809 | /* Vector Floating-Point Add */ | |
810 | ||
68c7761c | 811 | {"vadd.dd", OP_REG(0x3C0) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, |
1eb54bb4 FF |
812 | {"vadd.sd", OP_LI(0x3C1) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, |
813 | {"vadd.sd", OP_REG(0x3C0) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, | |
814 | {"vadd.ss", OP_LI(0x3C1) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, | |
815 | {"vadd.ss", OP_REG(0x3C0) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, | |
68c7761c FF |
816 | |
817 | /* Vector Floating-Point Multiply and Add to Accumulator | |
818 | FIXME! This is not yet implemented. From the documentation there appears to be no way to | |
819 | tell the difference between the opcodes for instructions that have register destinations | |
820 | and instructions that have accumulator destinations. Further investigation is necessary. | |
821 | Since this isn't critical to getting a TIC80 toolchain up and running, it is defered | |
822 | until later. */ | |
823 | ||
824 | /* Vector Floating-Point Multiply | |
825 | Note: If r0 is in the destination reg, then this is a "vector nop" instruction. */ | |
826 | ||
68c7761c | 827 | {"vmpy.dd", OP_REG(0x3C4) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} }, |
1eb54bb4 FF |
828 | {"vmpy.sd", OP_LI(0x3C5) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} }, |
829 | {"vmpy.sd", OP_REG(0x3C4) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} }, | |
830 | {"vmpy.ss", OP_LI(0x3C5) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} }, | |
831 | {"vmpy.ss", OP_REG(0x3C4) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} }, | |
68c7761c FF |
832 | |
833 | /* Vector Floating-Point Multiply and Subtract from Accumulator | |
834 | FIXME: See note above for vmac instruction */ | |
c977d8fb | 835 | |
68c7761c FF |
836 | /* Vector Floating-Point Subtract Accumulator From Source |
837 | FIXME: See note above for vmac instruction */ | |
c977d8fb | 838 | |
68c7761c FF |
839 | /* Vector Round With Floating-Point Input |
840 | FIXME: See note above for vmac instruction */ | |
8fdffbc4 | 841 | |
68c7761c FF |
842 | /* Vector Round with Integer Input */ |
843 | ||
1eb54bb4 | 844 | {"vrnd.id", OP_LI (0x3CB) | P2(1) | P1(0), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LSI, REG_22}}, |
68c7761c | 845 | {"vrnd.id", OP_REG (0x3CA) | P2(1) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}}, |
1eb54bb4 FF |
846 | {"vrnd.is", OP_LI (0x3CB) | P2(0) | P1(0), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LSI, REG_22}}, |
847 | {"vrnd.is", OP_REG (0x3CA) | P2(0) | P1(0), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}}, | |
848 | {"vrnd.ud", OP_LI (0x3CB) | P2(1) | P1(1), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LUI, REG_22}}, | |
68c7761c | 849 | {"vrnd.ud", OP_REG (0x3CA) | P2(1) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}}, |
1eb54bb4 FF |
850 | {"vrnd.us", OP_LI (0x3CB) | P2(0) | P1(1), MASK_LI | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {LUI, REG_22}}, |
851 | {"vrnd.us", OP_REG (0x3CA) | P2(0) | P1(1), MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22}}, | |
68c7761c FF |
852 | |
853 | /* Vector Floating-Point Subtract */ | |
854 | ||
68c7761c | 855 | {"vsub.dd", OP_REG(0x3C2) | P2(1) | P1(1), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, |
1eb54bb4 FF |
856 | {"vsub.sd", OP_LI(0x3C3) | P2(1) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, |
857 | {"vsub.sd", OP_REG(0x3C2) | P2(1) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, | |
858 | {"vsub.ss", OP_LI(0x3C3) | P2(0) | P1(0), MASK_LI | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {SPFI, REG_22, REG_22} }, | |
859 | {"vsub.ss", OP_REG(0x3C2) | P2(0) | P1(0), MASK_REG | V_a1(1) | P2(1) | P1(1), TIC80_VECTOR, {REG_0, REG_22, REG_22} }, | |
68c7761c FF |
860 | |
861 | /* Vector Load Data Into Register - Note that the vector load/store instructions come after the other | |
862 | vector instructions so that the disassembler will always print the load/store instruction second for | |
863 | vector instructions that have two instructions in the same opcode. */ | |
5fdeceb4 | 864 | |
c977d8fb | 865 | {"vld0.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, |
1eb54bb4 | 866 | {"vld0.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(0), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, |
c977d8fb | 867 | {"vld1.d", OP_V(0x1E) | V_m(1) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, |
1eb54bb4 | 868 | {"vld1.s", OP_V(0x1E) | V_m(1) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, |
5fdeceb4 | 869 | |
68c7761c FF |
870 | /* Vector Store Data Into Memory - Note that the vector load/store instructions come after the other |
871 | vector instructions so that the disassembler will always print the load/store instruction second for | |
872 | vector instructions that have two instructions in the same opcode. */ | |
873 | ||
68c7761c | 874 | {"vst.d", OP_V(0x1E) | V_m(0) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, |
1eb54bb4 | 875 | {"vst.s", OP_V(0x1E) | V_m(0) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, |
68c7761c | 876 | |
68c7761c | 877 | {"xnor", OP_LI(0x333), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, |
1eb54bb4 FF |
878 | {"xnor", OP_REG(0x332), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, |
879 | {"xnor", OP_SI(0x19), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, | |
68c7761c | 880 | |
68c7761c | 881 | {"xor", OP_LI(0x32D), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, |
1eb54bb4 FF |
882 | {"xor", OP_REG(0x32C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, |
883 | {"xor", OP_SI(0x16), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, | |
872dc6f0 FF |
884 | |
885 | }; | |
886 | ||
887 | const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]); | |
888 |