Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Assemble V850 instructions. |
78c8d46c | 2 | Copyright 1996-2013 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 NC |
4 | This file is part of the GNU opcodes library. |
5 | ||
6 | This library is free software; you can redistribute it and/or modify | |
8ad30312 | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
252b5132 | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
252b5132 | 15 | |
8ad30312 NC |
16 | You should have received a copy of the GNU General Public License |
17 | along with this program; if not, write to the Free Software | |
47b0e7ad NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
252b5132 | 20 | |
0d8dfecf | 21 | #include "sysdep.h" |
df7b86aa | 22 | #include <stdio.h> |
252b5132 | 23 | #include "opcode/v850.h" |
1cd986c5 | 24 | #include "bfd.h" |
252b5132 RH |
25 | #include "opintl.h" |
26 | ||
8ad30312 | 27 | /* Regular opcodes. */ |
252b5132 RH |
28 | #define OP(x) ((x & 0x3f) << 5) |
29 | #define OP_MASK OP (0x3f) | |
30 | ||
1cd986c5 NC |
31 | /* Conditional branch opcodes (Format III). */ |
32 | #define BOP(x) ((0x58 << 4) | (x & 0x0f)) | |
33 | #define BOP_MASK ((0x78 << 4) | 0x0f) | |
34 | ||
35 | /* Conditional branch opcodes (Format VII). */ | |
36 | #define BOP7(x) (0x107e0 | (x & 0xf)) | |
37 | #define BOP7_MASK (0x1ffe0 | 0xf) | |
252b5132 | 38 | |
8ad30312 | 39 | /* One-word opcodes. */ |
252b5132 RH |
40 | #define one(x) ((unsigned int) (x)) |
41 | ||
8ad30312 | 42 | /* Two-word opcodes. */ |
252b5132 | 43 | #define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16)) |
1cd986c5 | 44 | |
252b5132 RH |
45 | \f |
46 | /* The functions used to insert and extract complicated operands. */ | |
47 | ||
48 | /* Note: There is a conspiracy between these functions and | |
49 | v850_insert_operand() in gas/config/tc-v850.c. Error messages | |
50 | containing the string 'out of range' will be ignored unless a | |
51 | specific command line option is given to GAS. */ | |
52 | ||
53 | static const char * not_valid = N_ ("displacement value is not in range and is not aligned"); | |
54 | static const char * out_of_range = N_ ("displacement value is out of range"); | |
55 | static const char * not_aligned = N_ ("displacement value is not aligned"); | |
56 | ||
57 | static const char * immediate_out_of_range = N_ ("immediate value is out of range"); | |
1cd986c5 NC |
58 | static const char * branch_out_of_range = N_ ("branch value out of range"); |
59 | static const char * branch_out_of_range_and_odd_offset = N_ ("branch value not in range and to odd offset"); | |
60 | static const char * branch_to_odd_offset = N_ ("branch to odd offset"); | |
78c8d46c NC |
61 | static const char * pos_out_of_range = N_ ("position value is out of range"); |
62 | static const char * width_out_of_range = N_ ("width value is out of range"); | |
63 | static const char * selid_out_of_range = N_ ("SelID is out of range"); | |
64 | static const char * vector8_out_of_range = N_ ("vector8 is out of range"); | |
65 | static const char * vector5_out_of_range = N_ ("vector5 is out of range"); | |
66 | static const char * imm10_out_of_range = N_ ("imm10 is out of range"); | |
67 | static const char * sr_selid_out_of_range = N_ ("SR/SelID is out of range"); | |
1cd986c5 NC |
68 | |
69 | int | |
70 | v850_msg_is_out_of_range (const char* msg) | |
71 | { | |
72 | return msg == out_of_range | |
73 | || msg == immediate_out_of_range | |
74 | || msg == branch_out_of_range; | |
75 | } | |
252b5132 RH |
76 | |
77 | static unsigned long | |
1cd986c5 | 78 | insert_i5div1 (unsigned long insn, long value, const char ** errmsg) |
252b5132 | 79 | { |
1cd986c5 | 80 | if (value > 30 || value < 2) |
252b5132 | 81 | { |
1cd986c5 NC |
82 | if (value & 1) |
83 | * errmsg = _(not_valid); | |
252b5132 | 84 | else |
1cd986c5 | 85 | * errmsg = _(out_of_range); |
252b5132 | 86 | } |
1cd986c5 NC |
87 | else if (value & 1) |
88 | * errmsg = _(not_aligned); | |
252b5132 | 89 | |
1cd986c5 NC |
90 | value = (32 - value)/2; |
91 | ||
92 | return (insn | ((value << (2+16)) & 0x3c0000)); | |
252b5132 RH |
93 | } |
94 | ||
95 | static unsigned long | |
1cd986c5 | 96 | extract_i5div1 (unsigned long insn, int * invalid) |
252b5132 | 97 | { |
1cd986c5 NC |
98 | unsigned long ret = (insn & 0x003c0000) >> (16+2); |
99 | ret = 32 - (ret * 2); | |
252b5132 | 100 | |
1cd986c5 NC |
101 | if (invalid != 0) |
102 | *invalid = (ret > 30 || ret < 2) ? 1 : 0; | |
252b5132 RH |
103 | return ret; |
104 | } | |
105 | ||
106 | static unsigned long | |
1cd986c5 | 107 | insert_i5div2 (unsigned long insn, long value, const char ** errmsg) |
252b5132 | 108 | { |
1cd986c5 | 109 | if (value > 30 || value < 4) |
252b5132 | 110 | { |
1cd986c5 NC |
111 | if (value & 1) |
112 | * errmsg = _(not_valid); | |
252b5132 | 113 | else |
1cd986c5 | 114 | * errmsg = _(out_of_range); |
252b5132 | 115 | } |
1cd986c5 NC |
116 | else if (value & 1) |
117 | * errmsg = _(not_aligned); | |
252b5132 | 118 | |
1cd986c5 NC |
119 | value = (32 - value)/2; |
120 | ||
78c8d46c | 121 | return insn | ((value << (2 + 16)) & 0x3c0000); |
252b5132 RH |
122 | } |
123 | ||
124 | static unsigned long | |
1cd986c5 | 125 | extract_i5div2 (unsigned long insn, int * invalid) |
252b5132 | 126 | { |
1cd986c5 NC |
127 | unsigned long ret = (insn & 0x003c0000) >> (16+2); |
128 | ret = 32 - (ret * 2); | |
252b5132 | 129 | |
1cd986c5 NC |
130 | if (invalid != 0) |
131 | *invalid = (ret > 30 || ret < 4) ? 1 : 0; | |
132 | return ret; | |
252b5132 RH |
133 | } |
134 | ||
135 | static unsigned long | |
1cd986c5 | 136 | insert_i5div3 (unsigned long insn, long value, const char ** errmsg) |
252b5132 | 137 | { |
1cd986c5 | 138 | if (value > 32 || value < 2) |
252b5132 | 139 | { |
1cd986c5 | 140 | if (value & 1) |
252b5132 RH |
141 | * errmsg = _(not_valid); |
142 | else | |
143 | * errmsg = _(out_of_range); | |
144 | } | |
1cd986c5 | 145 | else if (value & 1) |
252b5132 RH |
146 | * errmsg = _(not_aligned); |
147 | ||
1cd986c5 NC |
148 | value = (32 - value)/2; |
149 | ||
78c8d46c | 150 | return insn | ((value << (2+16)) & 0x3c0000); |
252b5132 RH |
151 | } |
152 | ||
153 | static unsigned long | |
1cd986c5 | 154 | extract_i5div3 (unsigned long insn, int * invalid) |
252b5132 | 155 | { |
1cd986c5 NC |
156 | unsigned long ret = (insn & 0x003c0000) >> (16+2); |
157 | ret = 32 - (ret * 2); | |
252b5132 | 158 | |
1cd986c5 NC |
159 | if (invalid != 0) |
160 | *invalid = (ret > 32 || ret < 2) ? 1 : 0; | |
161 | return ret; | |
252b5132 RH |
162 | } |
163 | ||
164 | static unsigned long | |
1cd986c5 | 165 | insert_d5_4 (unsigned long insn, long value, const char ** errmsg) |
252b5132 | 166 | { |
1cd986c5 | 167 | if (value > 0x1f || value < 0) |
252b5132 | 168 | { |
1cd986c5 | 169 | if (value & 1) |
252b5132 RH |
170 | * errmsg = _(not_valid); |
171 | else | |
172 | * errmsg = _(out_of_range); | |
173 | } | |
1cd986c5 | 174 | else if (value & 1) |
252b5132 RH |
175 | * errmsg = _(not_aligned); |
176 | ||
177 | value >>= 1; | |
178 | ||
1cd986c5 | 179 | return insn | (value & 0x0f); |
252b5132 RH |
180 | } |
181 | ||
182 | static unsigned long | |
1cd986c5 | 183 | extract_d5_4 (unsigned long insn, int * invalid) |
252b5132 | 184 | { |
1cd986c5 NC |
185 | unsigned long ret = (insn & 0x0f); |
186 | ||
187 | ret <<= 1; | |
252b5132 | 188 | |
1cd986c5 NC |
189 | if (invalid != 0) |
190 | *invalid = 0; | |
191 | return ret; | |
252b5132 RH |
192 | } |
193 | ||
194 | static unsigned long | |
47b0e7ad | 195 | insert_d8_6 (unsigned long insn, long value, const char ** errmsg) |
252b5132 RH |
196 | { |
197 | if (value > 0xff || value < 0) | |
198 | { | |
199 | if ((value % 4) != 0) | |
1cd986c5 | 200 | * errmsg = _(not_valid); |
252b5132 RH |
201 | else |
202 | * errmsg = _(out_of_range); | |
203 | } | |
204 | else if ((value % 4) != 0) | |
205 | * errmsg = _(not_aligned); | |
206 | ||
207 | value >>= 1; | |
208 | ||
47b0e7ad | 209 | return insn | (value & 0x7e); |
252b5132 RH |
210 | } |
211 | ||
212 | static unsigned long | |
1cd986c5 | 213 | extract_d8_6 (unsigned long insn, int * invalid) |
252b5132 RH |
214 | { |
215 | unsigned long ret = (insn & 0x7e); | |
216 | ||
1cd986c5 NC |
217 | ret <<= 1; |
218 | ||
219 | if (invalid != 0) | |
220 | *invalid = 0; | |
221 | return ret; | |
252b5132 RH |
222 | } |
223 | ||
224 | static unsigned long | |
1cd986c5 | 225 | insert_d8_7 (unsigned long insn, long value, const char ** errmsg) |
252b5132 | 226 | { |
1cd986c5 | 227 | if (value > 0xff || value < 0) |
252b5132 | 228 | { |
1cd986c5 | 229 | if ((value % 2) != 0) |
252b5132 RH |
230 | * errmsg = _(not_valid); |
231 | else | |
1cd986c5 | 232 | * errmsg = _(out_of_range); |
252b5132 | 233 | } |
1cd986c5 | 234 | else if ((value % 2) != 0) |
252b5132 RH |
235 | * errmsg = _(not_aligned); |
236 | ||
237 | value >>= 1; | |
238 | ||
1cd986c5 | 239 | return insn | (value & 0x7f); |
252b5132 RH |
240 | } |
241 | ||
242 | static unsigned long | |
1cd986c5 | 243 | extract_d8_7 (unsigned long insn, int * invalid) |
252b5132 | 244 | { |
1cd986c5 NC |
245 | unsigned long ret = (insn & 0x7f); |
246 | ||
247 | ret <<= 1; | |
248 | ||
249 | if (invalid != 0) | |
250 | *invalid = 0; | |
251 | return ret; | |
252 | } | |
253 | ||
254 | static unsigned long | |
255 | insert_v8 (unsigned long insn, long value, const char ** errmsg) | |
256 | { | |
257 | if (value > 0xff || value < 0) | |
258 | * errmsg = _(immediate_out_of_range); | |
259 | ||
260 | return insn | (value & 0x1f) | ((value & 0xe0) << (27-5)); | |
261 | } | |
262 | ||
263 | static unsigned long | |
264 | extract_v8 (unsigned long insn, int * invalid) | |
265 | { | |
3f26eb3a | 266 | unsigned long ret = (insn & 0x1f) | ((insn >> (27-5)) & 0xe0); |
1cd986c5 NC |
267 | |
268 | if (invalid != 0) | |
269 | *invalid = 0; | |
270 | return ret; | |
271 | } | |
272 | ||
273 | static unsigned long | |
274 | insert_d9 (unsigned long insn, long value, const char ** errmsg) | |
275 | { | |
276 | if (value > 0xff || value < -0x100) | |
277 | { | |
278 | if ((value % 2) != 0) | |
279 | * errmsg = branch_out_of_range_and_odd_offset; | |
280 | else | |
281 | * errmsg = branch_out_of_range; | |
282 | } | |
283 | else if ((value % 2) != 0) | |
284 | * errmsg = branch_to_odd_offset; | |
285 | ||
286 | return insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3); | |
287 | } | |
288 | ||
289 | static unsigned long | |
290 | extract_d9 (unsigned long insn, int * invalid) | |
291 | { | |
3f26eb3a | 292 | signed long ret = ((insn >> 7) & 0x1f0) | ((insn >> 3) & 0x0e); |
1cd986c5 | 293 | |
3f26eb3a | 294 | ret = (ret ^ 0x100) - 0x100; |
1cd986c5 NC |
295 | |
296 | if (invalid != 0) | |
297 | *invalid = 0; | |
298 | return ret; | |
299 | } | |
300 | ||
301 | static unsigned long | |
302 | insert_u16_loop (unsigned long insn, long value, const char ** errmsg) | |
303 | { | |
304 | if (value < -0xffff || value > 0) | |
305 | { | |
306 | if ((value % 2) != 0) | |
307 | * errmsg = branch_out_of_range_and_odd_offset; | |
308 | else | |
309 | * errmsg = branch_out_of_range; | |
310 | } | |
311 | else if ((value % 2) != 0) | |
312 | * errmsg = branch_to_odd_offset; | |
313 | ||
314 | return insn | ((-value & 0xfffe) << 16); | |
315 | } | |
316 | ||
317 | static unsigned long | |
318 | extract_u16_loop (unsigned long insn, int * invalid) | |
319 | { | |
320 | long ret = (insn >> 16) & 0xfffe; | |
321 | ret = -ret; | |
322 | ||
323 | if (invalid != 0) | |
324 | *invalid = 0; | |
325 | return ret; | |
326 | } | |
327 | ||
328 | static unsigned long | |
329 | insert_d16_15 (unsigned long insn, long value, const char ** errmsg) | |
330 | { | |
331 | if (value > 0x7fff || value < -0x8000) | |
332 | { | |
333 | if ((value % 2) != 0) | |
334 | * errmsg = _(not_valid); | |
335 | else | |
336 | * errmsg = _(out_of_range); | |
337 | } | |
338 | else if ((value % 2) != 0) | |
339 | * errmsg = _(not_aligned); | |
340 | ||
341 | return insn | ((value & 0xfffe) << 16); | |
342 | } | |
343 | ||
344 | static unsigned long | |
345 | extract_d16_15 (unsigned long insn, int * invalid) | |
346 | { | |
3f26eb3a AM |
347 | signed long ret = (insn >> 16) & 0xfffe; |
348 | ||
349 | ret = (ret ^ 0x8000) - 0x8000; | |
252b5132 | 350 | |
1cd986c5 NC |
351 | if (invalid != 0) |
352 | *invalid = 0; | |
353 | return ret; | |
252b5132 RH |
354 | } |
355 | ||
356 | static unsigned long | |
47b0e7ad | 357 | insert_d16_16 (unsigned long insn, signed long value, const char ** errmsg) |
252b5132 RH |
358 | { |
359 | if (value > 0x7fff || value < -0x8000) | |
360 | * errmsg = _(out_of_range); | |
361 | ||
47b0e7ad | 362 | return insn | ((value & 0xfffe) << 16) | ((value & 1) << 5); |
252b5132 RH |
363 | } |
364 | ||
365 | static unsigned long | |
1cd986c5 | 366 | extract_d16_16 (unsigned long insn, int * invalid) |
252b5132 | 367 | { |
3f26eb3a AM |
368 | signed long ret = ((insn >> 16) & 0xfffe) | ((insn >> 5) & 1); |
369 | ||
370 | ret = (ret ^ 0x8000) - 0x8000; | |
47b0e7ad | 371 | |
1cd986c5 NC |
372 | if (invalid != 0) |
373 | *invalid = 0; | |
252b5132 RH |
374 | return ret; |
375 | } | |
376 | ||
1cd986c5 NC |
377 | static unsigned long |
378 | insert_d17_16 (unsigned long insn, long value, const char ** errmsg) | |
379 | { | |
380 | if (value > 0xffff || value < -0x10000) | |
381 | * errmsg = _(out_of_range); | |
382 | ||
383 | return insn | ((value & 0xfffe) << 16) | ((value & 0x10000) >> (16 - 4)); | |
384 | } | |
385 | ||
386 | static unsigned long | |
387 | extract_d17_16 (unsigned long insn, int * invalid) | |
388 | { | |
3f26eb3a AM |
389 | signed long ret = ((insn >> 16) & 0xfffe) | ((insn << (16 - 4)) & 0x10000); |
390 | ||
391 | ret = (ret ^ 0x10000) - 0x10000; | |
1cd986c5 NC |
392 | |
393 | if (invalid != 0) | |
394 | *invalid = 0; | |
395 | return (unsigned long)ret; | |
396 | } | |
397 | ||
398 | static unsigned long | |
399 | insert_d22 (unsigned long insn, long value, const char ** errmsg) | |
400 | { | |
401 | if (value > 0x1fffff || value < -0x200000) | |
402 | { | |
403 | if ((value % 2) != 0) | |
404 | * errmsg = branch_out_of_range_and_odd_offset; | |
405 | else | |
406 | * errmsg = branch_out_of_range; | |
407 | } | |
408 | else if ((value % 2) != 0) | |
409 | * errmsg = branch_to_odd_offset; | |
410 | ||
411 | return insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16); | |
412 | } | |
413 | ||
414 | static unsigned long | |
415 | extract_d22 (unsigned long insn, int * invalid) | |
416 | { | |
3f26eb3a | 417 | signed long ret = ((insn >> 16) & 0xfffe) | ((insn << 16) & 0x3f0000); |
1cd986c5 | 418 | |
3f26eb3a | 419 | ret = (ret ^ 0x200000) - 0x200000; |
1cd986c5 NC |
420 | |
421 | if (invalid != 0) | |
422 | *invalid = 0; | |
423 | return (unsigned long) ret; | |
424 | } | |
425 | ||
426 | static unsigned long | |
427 | insert_d23 (unsigned long insn, long value, const char ** errmsg) | |
428 | { | |
429 | if (value > 0x3fffff || value < -0x400000) | |
3f26eb3a | 430 | * errmsg = out_of_range; |
1cd986c5 NC |
431 | |
432 | return insn | ((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7)); | |
433 | } | |
434 | ||
78c8d46c NC |
435 | static unsigned long |
436 | insert_d23_align1 (unsigned long insn, long value, const char ** errmsg) | |
437 | { | |
438 | if (value > 0x3fffff || value < -0x400000) | |
439 | { | |
440 | if (value & 0x1) | |
441 | * errmsg = _(not_valid); | |
442 | else | |
443 | * errmsg = _(out_of_range); | |
444 | } | |
445 | else if (value & 0x1) | |
446 | * errmsg = _(not_aligned); | |
447 | ||
448 | return insn | ((value & 0x7e) << 4) | ((value & 0x7fff80) << (16 - 7)); | |
449 | } | |
450 | ||
1cd986c5 NC |
451 | static unsigned long |
452 | extract_d23 (unsigned long insn, int * invalid) | |
453 | { | |
3f26eb3a | 454 | signed long ret = ((insn >> 4) & 0x7f) | ((insn >> (16-7)) & 0x7fff80); |
1cd986c5 | 455 | |
3f26eb3a | 456 | ret = (ret ^ 0x400000) - 0x400000; |
1cd986c5 NC |
457 | |
458 | if (invalid != 0) | |
459 | *invalid = 0; | |
460 | return (unsigned long) ret; | |
461 | } | |
462 | ||
252b5132 | 463 | static unsigned long |
47b0e7ad | 464 | insert_i9 (unsigned long insn, signed long value, const char ** errmsg) |
252b5132 RH |
465 | { |
466 | if (value > 0xff || value < -0x100) | |
467 | * errmsg = _(immediate_out_of_range); | |
468 | ||
469 | return insn | ((value & 0x1e0) << 13) | (value & 0x1f); | |
470 | } | |
471 | ||
472 | static unsigned long | |
1cd986c5 | 473 | extract_i9 (unsigned long insn, int * invalid) |
252b5132 | 474 | { |
3f26eb3a | 475 | signed long ret = ((insn >> 13) & 0x1e0) | (insn & 0x1f); |
252b5132 | 476 | |
3f26eb3a | 477 | ret = (ret ^ 0x100) - 0x100; |
47b0e7ad | 478 | |
1cd986c5 NC |
479 | if (invalid != 0) |
480 | *invalid = 0; | |
252b5132 RH |
481 | return ret; |
482 | } | |
483 | ||
484 | static unsigned long | |
47b0e7ad | 485 | insert_u9 (unsigned long insn, long v, const char ** errmsg) |
252b5132 | 486 | { |
fc05c67f | 487 | unsigned long value = (unsigned long) v; |
47b0e7ad | 488 | |
252b5132 RH |
489 | if (value > 0x1ff) |
490 | * errmsg = _(immediate_out_of_range); | |
491 | ||
492 | return insn | ((value & 0x1e0) << 13) | (value & 0x1f); | |
493 | } | |
494 | ||
495 | static unsigned long | |
1cd986c5 | 496 | extract_u9 (unsigned long insn, int * invalid) |
252b5132 | 497 | { |
3f26eb3a | 498 | unsigned long ret = ((insn >> 13) & 0x1e0) | (insn & 0x1f); |
47b0e7ad | 499 | |
1cd986c5 NC |
500 | if (invalid != 0) |
501 | *invalid = 0; | |
252b5132 RH |
502 | return ret; |
503 | } | |
504 | ||
505 | static unsigned long | |
47b0e7ad | 506 | insert_spe (unsigned long insn, long v, const char ** errmsg) |
252b5132 | 507 | { |
fc05c67f NC |
508 | unsigned long value = (unsigned long) v; |
509 | ||
252b5132 RH |
510 | if (value != 3) |
511 | * errmsg = _("invalid register for stack adjustment"); | |
512 | ||
3f26eb3a | 513 | return insn & ~0x180000; |
252b5132 RH |
514 | } |
515 | ||
516 | static unsigned long | |
1cd986c5 | 517 | extract_spe (unsigned long insn ATTRIBUTE_UNUSED, int * invalid) |
252b5132 | 518 | { |
1cd986c5 NC |
519 | if (invalid != 0) |
520 | *invalid = 0; | |
521 | ||
252b5132 RH |
522 | return 3; |
523 | } | |
524 | ||
525 | static unsigned long | |
1cd986c5 | 526 | insert_r4 (unsigned long insn, long v, const char ** errmsg) |
252b5132 | 527 | { |
fc05c67f NC |
528 | unsigned long value = (unsigned long) v; |
529 | ||
1cd986c5 | 530 | if (value >= 32) |
78c8d46c | 531 | * errmsg = _("invalid register name"); |
47b0e7ad | 532 | |
78c8d46c | 533 | return insn | ((value & 0x01) << 23) | ((value & 0x1e) << 16); |
252b5132 RH |
534 | } |
535 | ||
536 | static unsigned long | |
1cd986c5 | 537 | extract_r4 (unsigned long insn, int * invalid) |
252b5132 | 538 | { |
78c8d46c NC |
539 | unsigned long r4; |
540 | unsigned long insn2; | |
541 | ||
542 | insn2 = insn >> 16; | |
543 | r4 = (((insn2 & 0x0080) >> 7) | (insn2 & 0x001e)); | |
544 | ||
545 | if (invalid != 0) | |
546 | *invalid = 0; | |
547 | ||
548 | return r4; | |
549 | } | |
550 | ||
551 | static unsigned long G_pos; | |
552 | ||
553 | static unsigned long | |
554 | insert_POS (unsigned long insn, long pos, const char ** errmsg) | |
555 | { | |
556 | if (pos > 0x1f || pos < 0) | |
557 | * errmsg = _(pos_out_of_range); | |
558 | ||
559 | G_pos = (unsigned long) pos; | |
560 | ||
561 | return insn; /* Not an oparaton until WIDTH. */ | |
562 | } | |
563 | ||
564 | static unsigned long | |
565 | extract_POS_U (unsigned long insn, int * invalid) | |
566 | { | |
567 | unsigned long pos,lsb; | |
568 | unsigned long insn2; | |
569 | insn2 = insn >> 16; | |
570 | ||
571 | lsb = ((insn2 & 0x0800) >> 8) | |
572 | | ((insn2 & 0x000e) >> 1); | |
573 | lsb += 16; | |
574 | pos = lsb; | |
575 | ||
576 | if (invalid != 0) | |
577 | *invalid = 0; | |
578 | ||
579 | return pos; | |
580 | } | |
581 | ||
582 | static unsigned long | |
583 | extract_POS_L (unsigned long insn, int * invalid) | |
584 | { | |
585 | unsigned long pos,lsb; | |
586 | unsigned long insn2; | |
587 | insn2 = insn >> 16; | |
588 | ||
589 | lsb = ((insn2 & 0x0800) >> 8) | |
590 | | ((insn2 & 0x000e) >> 1); | |
591 | pos = lsb; | |
592 | ||
593 | if (invalid != 0) | |
594 | *invalid = 0; | |
595 | ||
596 | return pos; | |
597 | } | |
598 | ||
599 | static unsigned long | |
600 | insert_WIDTH (unsigned long insn, long width, const char ** errmsg) | |
601 | { | |
602 | unsigned long msb, lsb, opc, ret; | |
603 | unsigned long msb_expand, lsb_expand; | |
604 | ||
605 | msb = (unsigned long)width + G_pos - 1; | |
606 | lsb = G_pos; | |
607 | opc = 0; | |
608 | G_pos = 0; | |
609 | ||
610 | if (width > 0x20 || width < 0) | |
611 | * errmsg = _(width_out_of_range); | |
612 | ||
613 | if ((msb >= 16) && (lsb >= 16)) | |
614 | opc = 0x0090; | |
615 | else if ((msb >= 16) && (lsb < 16)) | |
616 | opc = 0x00b0; | |
617 | else if ((msb < 16) && (lsb < 16)) | |
618 | opc = 0x00d0; | |
619 | else | |
620 | * errmsg = _(width_out_of_range); | |
621 | ||
622 | msb &= 0x0f; | |
623 | msb_expand = msb << 12; | |
624 | lsb &= 0x0f; | |
625 | lsb_expand = ((lsb & 0x8) << 8)|((lsb & 0x7) << 1); | |
626 | ||
627 | ret = (insn & 0x0000ffff) | ((opc | msb_expand | lsb_expand) << 16); | |
628 | ||
629 | return ret; | |
630 | } | |
631 | ||
632 | static unsigned long | |
633 | extract_WIDTH_U (unsigned long insn, int * invalid) | |
634 | { | |
635 | unsigned long width, msb, lsb; | |
636 | unsigned long insn2; | |
637 | insn2 = insn >> 16; | |
638 | ||
639 | msb = ((insn2 & 0xf000) >> 12); | |
640 | msb += 16; | |
641 | lsb = ((insn2 & 0x0800) >> 8) | |
642 | | ((insn2 & 0x000e) >> 1); | |
643 | lsb += 16; | |
644 | ||
645 | if (invalid != 0) | |
646 | *invalid = 0; | |
647 | ||
648 | width = msb - lsb + 1; | |
649 | ||
650 | return width; | |
651 | } | |
652 | ||
653 | static unsigned long | |
654 | extract_WIDTH_M (unsigned long insn, int * invalid) | |
655 | { | |
656 | unsigned long width, msb, lsb; | |
657 | unsigned long insn2; | |
658 | insn2 = insn >> 16; | |
659 | ||
660 | msb = ((insn2 & 0xf000) >> 12) ; | |
661 | msb += 16; | |
662 | lsb = ((insn2 & 0x0800) >> 8) | |
663 | | ((insn2 & 0x000e) >> 1); | |
664 | ||
665 | if (invalid != 0) | |
666 | *invalid = 0; | |
667 | ||
668 | width = msb - lsb + 1; | |
669 | ||
670 | return width; | |
671 | } | |
672 | ||
673 | static unsigned long | |
674 | extract_WIDTH_L (unsigned long insn, int * invalid) | |
675 | { | |
676 | unsigned long width, msb, lsb; | |
677 | unsigned long insn2; | |
678 | insn2 = insn >> 16; | |
679 | ||
680 | msb = ((insn2 & 0xf000) >> 12) ; | |
681 | lsb = ((insn2 & 0x0800) >> 8) | |
682 | | ((insn2 & 0x000e) >> 1); | |
683 | ||
684 | if (invalid != 0) | |
685 | *invalid = 0; | |
686 | ||
687 | width = msb - lsb + 1; | |
688 | ||
689 | return width; | |
690 | } | |
691 | ||
692 | static unsigned long | |
693 | insert_SELID (unsigned long insn, long selid, const char ** errmsg) | |
694 | { | |
695 | unsigned long ret; | |
696 | ||
697 | if (selid > 0x1f || selid < 0) | |
698 | * errmsg = _(selid_out_of_range); | |
699 | ||
700 | ret = (insn | ((selid & 0x1f) << 27)); | |
701 | ||
702 | return ret; | |
703 | } | |
704 | ||
705 | static unsigned long | |
706 | extract_SELID (unsigned long insn, int * invalid) | |
707 | { | |
708 | unsigned long selid; | |
709 | unsigned long insn2; | |
710 | ||
711 | insn2 = insn >> 16; | |
712 | ||
713 | selid = ((insn2 & 0xf800) >> 11); | |
714 | ||
715 | if (invalid != 0) | |
716 | *invalid = 0; | |
717 | ||
718 | return selid; | |
719 | } | |
720 | ||
721 | static unsigned long | |
722 | insert_VECTOR8 (unsigned long insn, long vector8, const char ** errmsg) | |
723 | { | |
724 | unsigned long ret; | |
725 | unsigned long VVV,vvvvv; | |
726 | ||
727 | if (vector8 > 0xff || vector8 < 0) | |
728 | * errmsg = _(vector8_out_of_range); | |
729 | ||
730 | VVV = (vector8 & 0xe0) >> 5; | |
731 | vvvvv = (vector8 & 0x1f); | |
732 | ||
733 | ret = (insn | (VVV << 27) | vvvvv); | |
734 | ||
735 | return ret; | |
736 | } | |
737 | ||
738 | static unsigned long | |
739 | extract_VECTOR8 (unsigned long insn, int * invalid) | |
740 | { | |
741 | unsigned long vector8; | |
742 | unsigned long VVV,vvvvv; | |
743 | unsigned long insn2; | |
744 | ||
745 | insn2 = insn >> 16; | |
746 | VVV = ((insn2 & 0x3800) >> 11); | |
747 | vvvvv = (insn & 0x001f); | |
748 | vector8 = VVV << 5 | vvvvv; | |
749 | ||
750 | if (invalid != 0) | |
751 | *invalid = 0; | |
752 | ||
753 | return vector8; | |
754 | } | |
755 | ||
756 | static unsigned long | |
757 | insert_VECTOR5 (unsigned long insn, long vector5, const char ** errmsg) | |
758 | { | |
759 | unsigned long ret; | |
760 | unsigned long vvvvv; | |
761 | ||
762 | if (vector5 > 0x1f || vector5 < 0) | |
763 | * errmsg = _(vector5_out_of_range); | |
764 | ||
765 | vvvvv = (vector5 & 0x1f); | |
766 | ||
767 | ret = (insn | vvvvv); | |
768 | ||
769 | return ret; | |
770 | } | |
771 | ||
772 | static unsigned long | |
773 | extract_VECTOR5 (unsigned long insn, int * invalid) | |
774 | { | |
775 | unsigned long vector5; | |
776 | ||
777 | vector5 = (insn & 0x001f); | |
778 | ||
779 | if (invalid != 0) | |
780 | *invalid = 0; | |
781 | ||
782 | return vector5; | |
783 | } | |
784 | ||
785 | static unsigned long | |
786 | insert_CACHEOP (unsigned long insn, long cacheop, const char ** errmsg ATTRIBUTE_UNUSED) | |
787 | { | |
788 | unsigned long ret; | |
789 | unsigned long pp,PPPPP; | |
790 | ||
791 | pp = (cacheop & 0x60) >> 5; | |
792 | PPPPP = (cacheop & 0x1f); | |
793 | ||
794 | ret = insn | (pp << 11) | (PPPPP << 27); | |
795 | ||
796 | return ret; | |
797 | } | |
798 | ||
799 | static unsigned long | |
800 | extract_CACHEOP (unsigned long insn, int * invalid) | |
801 | { | |
802 | unsigned long ret; | |
803 | unsigned long pp,PPPPP; | |
804 | unsigned long insn2; | |
805 | ||
806 | insn2 = insn >> 16; | |
807 | ||
808 | PPPPP = ((insn2 & 0xf800) >> 11); | |
809 | pp = ((insn & 0x1800) >> 11); | |
810 | ||
811 | ret = (pp << 5) | PPPPP; | |
812 | ||
813 | if (invalid != 0) | |
814 | *invalid = 0; | |
815 | ||
816 | return ret; | |
817 | } | |
818 | ||
819 | static unsigned long | |
820 | insert_PREFOP (unsigned long insn, long prefop, const char ** errmsg ATTRIBUTE_UNUSED) | |
821 | { | |
822 | unsigned long ret; | |
823 | unsigned long PPPPP; | |
824 | ||
825 | PPPPP = (prefop & 0x1f); | |
826 | ||
827 | ret = insn | (PPPPP << 27); | |
828 | ||
829 | return ret; | |
830 | } | |
831 | ||
832 | static unsigned long | |
833 | extract_PREFOP (unsigned long insn, int * invalid) | |
834 | { | |
835 | unsigned long ret; | |
836 | unsigned long PPPPP; | |
837 | unsigned long insn2; | |
838 | ||
839 | insn2 = insn >> 16; | |
840 | ||
841 | PPPPP = (insn2 & 0xf800) >> 11; | |
842 | ||
843 | ret = PPPPP; | |
844 | ||
845 | if (invalid != 0) | |
846 | *invalid = 0; | |
847 | ||
848 | return ret; | |
849 | } | |
850 | ||
851 | static unsigned long | |
852 | insert_IMM10U (unsigned long insn, long value, const char ** errmsg) | |
853 | { | |
854 | unsigned long imm10, ret; | |
855 | unsigned long iiiii,IIIII; | |
856 | ||
857 | if (value > 0x3ff || value < 0) | |
858 | * errmsg = _(imm10_out_of_range); | |
859 | ||
860 | imm10 = ((unsigned long) value) & 0x3ff; | |
861 | IIIII = (imm10 >> 5) & 0x1f; | |
862 | iiiii = imm10 & 0x1f; | |
863 | ||
864 | ret = insn | IIIII << 27 | iiiii; | |
865 | ||
866 | return ret; | |
867 | } | |
868 | ||
869 | static unsigned long | |
870 | extract_IMM10U (unsigned long insn, int * invalid) | |
871 | { | |
872 | unsigned long ret; | |
873 | unsigned long iiiii,IIIII; | |
874 | unsigned long insn2; | |
875 | insn2 = insn >> 16; | |
876 | ||
877 | IIIII = ((insn2 & 0xf800) >> 11); | |
878 | iiiii = (insn & 0x001f); | |
879 | ||
880 | ret = (IIIII << 5) | iiiii; | |
881 | ||
882 | if (invalid != 0) | |
883 | *invalid = 0; | |
884 | ||
885 | return ret; | |
886 | } | |
887 | ||
888 | static unsigned long | |
889 | insert_SRSEL1 (unsigned long insn, long value, const char ** errmsg) | |
890 | { | |
891 | unsigned long imm10, ret; | |
892 | unsigned long sr,selid; | |
893 | ||
894 | if (value > 0x3ff || value < 0) | |
895 | * errmsg = _(sr_selid_out_of_range); | |
896 | ||
897 | imm10 = (unsigned long) value; | |
898 | selid = (imm10 & 0x3e0) >> 5; | |
899 | sr = imm10 & 0x1f; | |
900 | ||
901 | ret = insn | selid << 27 | sr; | |
902 | ||
903 | return ret; | |
904 | } | |
905 | ||
906 | static unsigned long | |
907 | extract_SRSEL1 (unsigned long insn, int * invalid) | |
908 | { | |
909 | unsigned long ret; | |
910 | unsigned long sr, selid; | |
911 | unsigned long insn2; | |
912 | ||
913 | insn2 = insn >> 16; | |
914 | ||
915 | selid = ((insn2 & 0xf800) >> 11); | |
916 | sr = (insn & 0x001f); | |
917 | ||
918 | ret = (selid << 5) | sr; | |
919 | ||
920 | if (invalid != 0) | |
921 | *invalid = 0; | |
922 | ||
923 | return ret; | |
924 | } | |
925 | ||
926 | static unsigned long | |
927 | insert_SRSEL2 (unsigned long insn, long value, const char ** errmsg) | |
928 | { | |
929 | unsigned long imm10, ret; | |
930 | unsigned long sr, selid; | |
931 | ||
932 | if (value > 0x3ff || value < 0) | |
933 | * errmsg = _(sr_selid_out_of_range); | |
934 | ||
935 | imm10 = (unsigned long) value; | |
936 | selid = (imm10 & 0x3e0) >> 5; | |
937 | sr = imm10 & 0x1f; | |
938 | ||
939 | ret = insn | selid << 27 | sr << 11; | |
940 | ||
941 | return ret; | |
942 | } | |
943 | ||
944 | static unsigned long | |
945 | extract_SRSEL2 (unsigned long insn, int * invalid) | |
946 | { | |
947 | unsigned long ret; | |
948 | unsigned long sr, selid; | |
949 | unsigned long insn2; | |
950 | ||
951 | insn2 = insn >> 16; | |
952 | ||
953 | selid = ((insn2 & 0xf800) >> 11); | |
954 | sr = ((insn & 0xf800) >> 11); | |
955 | ||
956 | ret = (selid << 5) | sr; | |
47b0e7ad | 957 | |
1cd986c5 NC |
958 | if (invalid != 0) |
959 | *invalid = 0; | |
78c8d46c | 960 | |
252b5132 RH |
961 | return ret; |
962 | } | |
252b5132 RH |
963 | \f |
964 | /* Warning: code in gas/config/tc-v850.c examines the contents of this array. | |
965 | If you change any of the values here, be sure to look for side effects in | |
fc05c67f | 966 | that code. */ |
252b5132 RH |
967 | const struct v850_operand v850_operands[] = |
968 | { | |
969 | #define UNUSED 0 | |
1cd986c5 | 970 | { 0, 0, NULL, NULL, 0, BFD_RELOC_NONE }, |
252b5132 | 971 | |
1cd986c5 | 972 | /* The R1 field in a format 1, 6, 7, 9, C insn. */ |
252b5132 | 973 | #define R1 (UNUSED + 1) |
1cd986c5 | 974 | { 5, 0, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE }, |
252b5132 RH |
975 | |
976 | /* As above, but register 0 is not allowed. */ | |
977 | #define R1_NOTR0 (R1 + 1) | |
1cd986c5 NC |
978 | { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, |
979 | ||
980 | /* Even register is allowed. */ | |
981 | #define R1_EVEN (R1_NOTR0 + 1) | |
982 | { 4, 1, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, | |
983 | ||
984 | /* Bang (bit reverse). */ | |
985 | #define R1_BANG (R1_EVEN + 1) | |
986 | { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_BANG, BFD_RELOC_NONE }, | |
987 | ||
988 | /* Percent (modulo). */ | |
989 | #define R1_PERCENT (R1_BANG + 1) | |
990 | { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_PERCENT, BFD_RELOC_NONE }, | |
252b5132 | 991 | |
1cd986c5 NC |
992 | /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9, C insn. */ |
993 | #define R2 (R1_PERCENT + 1) | |
994 | { 5, 11, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE }, | |
252b5132 RH |
995 | |
996 | /* As above, but register 0 is not allowed. */ | |
997 | #define R2_NOTR0 (R2 + 1) | |
1cd986c5 | 998 | { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, |
252b5132 | 999 | |
1cd986c5 NC |
1000 | /* Even register is allowed. */ |
1001 | #define R2_EVEN (R2_NOTR0 + 1) | |
1002 | { 4, 12, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, | |
252b5132 | 1003 | |
1cd986c5 NC |
1004 | /* Reg2 in dispose instruction. */ |
1005 | #define R2_DISPOSE (R2_EVEN + 1) | |
1006 | { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, | |
252b5132 | 1007 | |
1cd986c5 NC |
1008 | /* The R3 field in a format 11, 12, C insn. */ |
1009 | #define R3 (R2_DISPOSE + 1) | |
1010 | { 5, 27, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE }, | |
252b5132 | 1011 | |
1cd986c5 NC |
1012 | /* As above, but register 0 is not allowed. */ |
1013 | #define R3_NOTR0 (R3 + 1) | |
1014 | { 5, 27, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE }, | |
252b5132 | 1015 | |
1cd986c5 NC |
1016 | /* As above, but odd number registers are not allowed. */ |
1017 | #define R3_EVEN (R3_NOTR0 + 1) | |
1018 | { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, | |
252b5132 | 1019 | |
1cd986c5 NC |
1020 | /* As above, but register 0 is not allowed. */ |
1021 | #define R3_EVEN_NOTR0 (R3_EVEN + 1) | |
1022 | { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN | V850_NOT_R0, BFD_RELOC_NONE }, | |
252b5132 | 1023 | |
1cd986c5 NC |
1024 | /* Forth register in FPU Instruction. */ |
1025 | #define R4 (R3_EVEN_NOTR0 + 1) | |
1026 | { 5, 0, insert_r4, extract_r4, V850_OPERAND_REG, BFD_RELOC_NONE }, | |
252b5132 | 1027 | |
1cd986c5 NC |
1028 | /* As above, but odd number registers are not allowed. */ |
1029 | #define R4_EVEN (R4 + 1) | |
1030 | { 4, 17, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE }, | |
252b5132 | 1031 | |
1cd986c5 NC |
1032 | /* Stack pointer in prepare instruction. */ |
1033 | #define SP (R4_EVEN + 1) | |
1034 | { 2, 0, insert_spe, extract_spe, V850_OPERAND_REG, BFD_RELOC_NONE }, | |
252b5132 RH |
1035 | |
1036 | /* EP Register. */ | |
1cd986c5 NC |
1037 | #define EP (SP + 1) |
1038 | { 0, 0, NULL, NULL, V850_OPERAND_EP, BFD_RELOC_NONE }, | |
1039 | ||
1040 | /* A list of registers in a prepare/dispose instruction. */ | |
1041 | #define LIST12 (EP + 1) | |
1042 | { -1, 0xffe00001, NULL, NULL, V850E_OPERAND_REG_LIST, BFD_RELOC_NONE }, | |
252b5132 | 1043 | |
1cd986c5 | 1044 | /* System register operands. */ |
78c8d46c | 1045 | #define OLDSR1 (LIST12 + 1) |
1cd986c5 | 1046 | { 5, 0, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE }, |
252b5132 | 1047 | |
78c8d46c NC |
1048 | #define SR1 (OLDSR1 + 1) |
1049 | { 0, 0, insert_SRSEL1, extract_SRSEL1, V850_OPERAND_SRG, BFD_RELOC_NONE }, | |
1050 | ||
252b5132 | 1051 | /* The R2 field as a system register. */ |
78c8d46c | 1052 | #define OLDSR2 (SR1 + 1) |
1cd986c5 | 1053 | { 5, 11, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE }, |
252b5132 | 1054 | |
78c8d46c NC |
1055 | #define SR2 (OLDSR2 + 1) |
1056 | { 0, 0, insert_SRSEL2, extract_SRSEL2, V850_OPERAND_SRG, BFD_RELOC_NONE }, | |
1057 | ||
1cd986c5 NC |
1058 | /* FPU CC bit position. */ |
1059 | #define FFF (SR2 + 1) | |
1060 | { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE }, | |
252b5132 | 1061 | |
1cd986c5 NC |
1062 | /* The 4 bit condition code in a setf instruction. */ |
1063 | #define CCCC (FFF + 1) | |
1064 | { 4, 0, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE }, | |
252b5132 | 1065 | |
1cd986c5 NC |
1066 | /* Condition code in adf,sdf. */ |
1067 | #define CCCC_NOTSA (CCCC + 1) | |
1068 | { 4, 17, NULL, NULL, V850_OPERAND_CC|V850_NOT_SA, BFD_RELOC_NONE }, | |
252b5132 | 1069 | |
1cd986c5 NC |
1070 | /* Condition code in conditional moves. */ |
1071 | #define MOVCC (CCCC_NOTSA + 1) | |
1072 | { 4, 17, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE }, | |
252b5132 | 1073 | |
1cd986c5 NC |
1074 | /* Condition code in FPU. */ |
1075 | #define FLOAT_CCCC (MOVCC + 1) | |
1076 | { 4, 27, NULL, NULL, V850_OPERAND_FLOAT_CC, BFD_RELOC_NONE }, | |
252b5132 | 1077 | |
1cd986c5 NC |
1078 | /* The 1 bit immediate field in format C insn. */ |
1079 | #define VI1 (FLOAT_CCCC + 1) | |
1080 | { 1, 3, NULL, NULL, 0, BFD_RELOC_NONE }, | |
252b5132 | 1081 | |
1cd986c5 NC |
1082 | /* The 1 bit immediate field in format C insn. */ |
1083 | #define VC1 (VI1 + 1) | |
1084 | { 1, 0, NULL, NULL, 0, BFD_RELOC_NONE }, | |
252b5132 | 1085 | |
1cd986c5 NC |
1086 | /* The 2 bit immediate field in format C insn. */ |
1087 | #define DI2 (VC1 + 1) | |
1088 | { 2, 17, NULL, NULL, 0, BFD_RELOC_NONE }, | |
252b5132 | 1089 | |
1cd986c5 NC |
1090 | /* The 2 bit immediate field in format C insn. */ |
1091 | #define VI2 (DI2 + 1) | |
1092 | { 2, 0, NULL, NULL, 0, BFD_RELOC_NONE }, | |
252b5132 | 1093 | |
1cd986c5 NC |
1094 | /* The 2 bit immediate field in format C - DUP insn. */ |
1095 | #define VI2DUP (VI2 + 1) | |
1096 | { 2, 2, NULL, NULL, 0, BFD_RELOC_NONE }, | |
252b5132 | 1097 | |
1cd986c5 NC |
1098 | /* The 3 bit immediate field in format 8 insn. */ |
1099 | #define B3 (VI2DUP + 1) | |
1100 | { 3, 11, NULL, NULL, 0, BFD_RELOC_NONE }, | |
252b5132 | 1101 | |
1cd986c5 NC |
1102 | /* The 3 bit immediate field in format C insn. */ |
1103 | #define DI3 (B3 + 1) | |
1104 | { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE }, | |
252b5132 | 1105 | |
1cd986c5 NC |
1106 | /* The 3 bit immediate field in format C insn. */ |
1107 | #define I3U (DI3 + 1) | |
1108 | { 3, 0, NULL, NULL, 0, BFD_RELOC_NONE }, | |
252b5132 | 1109 | |
1cd986c5 NC |
1110 | /* The 4 bit immediate field in format C insn. */ |
1111 | #define I4U (I3U + 1) | |
1112 | { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE }, | |
252b5132 | 1113 | |
1cd986c5 NC |
1114 | /* The 4 bit immediate field in fetrap. */ |
1115 | #define I4U_NOTIMM0 (I4U + 1) | |
1116 | { 4, 11, NULL, NULL, V850_NOT_IMM0, BFD_RELOC_NONE }, | |
252b5132 | 1117 | |
1cd986c5 NC |
1118 | /* The unsigned disp4 field in a sld.bu. */ |
1119 | #define D4U (I4U_NOTIMM0 + 1) | |
1120 | { 4, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_4_OFFSET }, | |
252b5132 | 1121 | |
1cd986c5 NC |
1122 | /* The imm5 field in a format 2 insn. */ |
1123 | #define I5 (D4U + 1) | |
1124 | { 5, 0, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_NONE }, | |
252b5132 | 1125 | |
1cd986c5 NC |
1126 | /* The imm5 field in a format 11 insn. */ |
1127 | #define I5DIV1 (I5 + 1) | |
1128 | { 5, 0, insert_i5div1, extract_i5div1, 0, BFD_RELOC_NONE }, | |
252b5132 | 1129 | |
1cd986c5 NC |
1130 | #define I5DIV2 (I5DIV1 + 1) |
1131 | { 5, 0, insert_i5div2, extract_i5div2, 0, BFD_RELOC_NONE }, | |
252b5132 | 1132 | |
1cd986c5 NC |
1133 | #define I5DIV3 (I5DIV2 + 1) |
1134 | { 5, 0, insert_i5div3, extract_i5div3, 0, BFD_RELOC_NONE }, | |
252b5132 | 1135 | |
1cd986c5 NC |
1136 | /* The unsigned imm5 field in a format 2 insn. */ |
1137 | #define I5U (I5DIV3 + 1) | |
1138 | { 5, 0, NULL, NULL, 0, BFD_RELOC_NONE }, | |
252b5132 | 1139 | |
1cd986c5 NC |
1140 | /* The imm5 field in a prepare/dispose instruction. */ |
1141 | #define IMM5 (I5U + 1) | |
1142 | { 5, 1, NULL, NULL, 0, BFD_RELOC_NONE }, | |
252b5132 | 1143 | |
1cd986c5 NC |
1144 | /* The unsigned disp5 field in a sld.hu. */ |
1145 | #define D5_4U (IMM5 + 1) | |
1146 | { 5, 0, insert_d5_4, extract_d5_4, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_5_OFFSET }, | |
1147 | ||
1148 | /* The IMM6 field in a callt instruction. */ | |
1149 | #define IMM6 (D5_4U + 1) | |
1150 | { 6, 0, NULL, NULL, 0, BFD_RELOC_V850_CALLT_6_7_OFFSET }, | |
1151 | ||
1152 | /* The signed disp7 field in a format 4 insn. */ | |
1153 | #define D7U (IMM6 + 1) | |
1154 | { 7, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_7_OFFSET }, | |
1155 | ||
1156 | /* The unsigned DISP8 field in a format 4 insn. */ | |
1157 | #define D8_7U (D7U + 1) | |
1158 | { 8, 0, insert_d8_7, extract_d8_7, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_8_OFFSET }, | |
1159 | ||
1160 | /* The unsigned DISP8 field in a format 4 insn. */ | |
1161 | #define D8_6U (D8_7U + 1) | |
1162 | { 8, 0, insert_d8_6, extract_d8_6, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_6_8_OFFSET }, | |
1163 | ||
1164 | /* The unsigned DISP8 field in a format 4 insn. */ | |
1165 | #define V8 (D8_6U + 1) | |
1166 | { 8, 0, insert_v8, extract_v8, 0, BFD_RELOC_NONE }, | |
1167 | ||
1168 | /* The imm9 field in a multiply word. */ | |
1169 | #define I9 (V8 + 1) | |
1170 | { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED, BFD_RELOC_NONE }, | |
1171 | ||
1172 | /* The unsigned imm9 field in a multiply word. */ | |
1173 | #define U9 (I9 + 1) | |
1174 | { 9, 0, insert_u9, extract_u9, 0, BFD_RELOC_NONE }, | |
1175 | ||
1176 | /* The DISP9 field in a format 3 insn. */ | |
1177 | #define D9 (U9 + 1) | |
1178 | { 9, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL }, | |
1179 | ||
1180 | /* The DISP9 field in a format 3 insn, relaxable. */ | |
1181 | #define D9_RELAX (D9 + 1) | |
1182 | { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL }, | |
1183 | ||
1184 | /* The imm16 field in a format 6 insn. */ | |
1185 | #define I16 (D9_RELAX + 1) | |
1186 | { 16, 16, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_16 }, | |
1187 | ||
dd42f060 | 1188 | /* The signed 16 bit immediate following a prepare instruction. */ |
78c8d46c | 1189 | #define IMM16LO (I16 + 1) |
dd42f060 | 1190 | { 16, 32, NULL, NULL, V850E_IMMEDIATE16 | V850_OPERAND_SIGNED, BFD_RELOC_LO16 }, |
1cd986c5 NC |
1191 | |
1192 | /* The hi 16 bit immediate following a 32 bit instruction. */ | |
1193 | #define IMM16HI (IMM16LO + 1) | |
1194 | { 16, 16, NULL, NULL, V850E_IMMEDIATE16HI, BFD_RELOC_HI16 }, | |
1195 | ||
1196 | /* The unsigned imm16 in a format 6 insn. */ | |
1197 | #define I16U (IMM16HI + 1) | |
1198 | { 16, 16, NULL, NULL, 0, BFD_RELOC_16 }, | |
1199 | ||
1200 | /* The disp16 field in a format 8 insn. */ | |
1201 | #define D16 (I16U + 1) | |
1202 | { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_16 }, | |
1203 | ||
1204 | /* The disp16 field in an format 7 unsigned byte load insn. */ | |
1205 | #define D16_16 (D16 + 1) | |
1206 | { 16, 0, insert_d16_16, extract_d16_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_16_SPLIT_OFFSET }, | |
1207 | ||
1208 | /* The disp16 field in a format 6 insn. */ | |
1209 | #define D16_15 (D16_16 + 1) | |
1210 | { 16, 0, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED | V850_OPERAND_DISP , BFD_RELOC_V850_16_S1 }, | |
1211 | ||
1212 | /* The unsigned DISP16 field in a format 7 insn. */ | |
1213 | #define D16_LOOP (D16_15 + 1) | |
78c8d46c | 1214 | { 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_RELAX | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_16_PCREL }, |
1cd986c5 NC |
1215 | |
1216 | /* The DISP17 field in a format 7 insn. */ | |
1217 | #define D17_16 (D16_LOOP + 1) | |
1218 | { 17, 0, insert_d17_16, extract_d17_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_17_PCREL }, | |
1219 | ||
1220 | /* The DISP22 field in a format 4 insn, relaxable. | |
1221 | This _must_ follow D9_RELAX; the assembler assumes that the longer | |
1222 | version immediately follows the shorter version for relaxing. */ | |
1223 | #define D22 (D17_16 + 1) | |
1224 | { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_22_PCREL }, | |
1225 | ||
1226 | #define D23 (D22 + 1) | |
1227 | { 23, 0, insert_d23, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 }, | |
1228 | ||
78c8d46c NC |
1229 | #define D23_ALIGN1 (D23 + 1) |
1230 | { 23, 0, insert_d23_align1, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 }, | |
1231 | ||
1cd986c5 | 1232 | /* The 32 bit immediate following a 32 bit instruction. */ |
78c8d46c | 1233 | #define IMM32 (D23_ALIGN1 + 1) |
1cd986c5 NC |
1234 | { 32, 32, NULL, NULL, V850E_IMMEDIATE32, BFD_RELOC_32 }, |
1235 | ||
1236 | #define D32_31 (IMM32 + 1) | |
1237 | { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_32_ABS }, | |
1238 | ||
1239 | #define D32_31_PCREL (D32_31 + 1) | |
1240 | { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_32_PCREL }, | |
1241 | ||
78c8d46c NC |
1242 | #define POS_U (D32_31_PCREL + 1) |
1243 | { 0, 0, insert_POS, extract_POS_U, 0, BFD_RELOC_NONE }, | |
1244 | ||
1245 | #define POS_M (POS_U + 1) | |
1246 | { 0, 0, insert_POS, extract_POS_L, 0, BFD_RELOC_NONE }, | |
1247 | ||
1248 | #define POS_L (POS_M + 1) | |
1249 | { 0, 0, insert_POS, extract_POS_L, 0, BFD_RELOC_NONE }, | |
1250 | ||
1251 | #define WIDTH_U (POS_L + 1) | |
1252 | { 0, 0, insert_WIDTH, extract_WIDTH_U, 0, BFD_RELOC_NONE }, | |
1253 | ||
1254 | #define WIDTH_M (WIDTH_U + 1) | |
1255 | { 0, 0, insert_WIDTH, extract_WIDTH_M, 0, BFD_RELOC_NONE }, | |
1256 | ||
1257 | #define WIDTH_L (WIDTH_M + 1) | |
1258 | { 0, 0, insert_WIDTH, extract_WIDTH_L, 0, BFD_RELOC_NONE }, | |
1259 | ||
1260 | #define SELID (WIDTH_L + 1) | |
1261 | { 5, 27, insert_SELID, extract_SELID, 0, BFD_RELOC_NONE }, | |
1262 | ||
1263 | #define RIE_IMM5 (SELID + 1) | |
1264 | { 5, 11, NULL, NULL, 0, BFD_RELOC_NONE }, | |
1265 | ||
1266 | #define RIE_IMM4 (RIE_IMM5 + 1) | |
1267 | { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE }, | |
1268 | ||
1269 | #define VECTOR8 (RIE_IMM4 + 1) | |
1270 | { 0, 0, insert_VECTOR8, extract_VECTOR8, 0, BFD_RELOC_NONE }, | |
1271 | ||
1272 | #define VECTOR5 (VECTOR8 + 1) | |
1273 | { 0, 0, insert_VECTOR5, extract_VECTOR5, 0, BFD_RELOC_NONE }, | |
1274 | ||
1275 | #define VR1 (VECTOR5 + 1) | |
1276 | { 5, 0, NULL, NULL, V850_OPERAND_VREG, BFD_RELOC_NONE }, | |
1277 | ||
1278 | #define VR2 (VR1 + 1) | |
1279 | { 5, 11, NULL, NULL, V850_OPERAND_VREG, BFD_RELOC_NONE }, | |
1280 | ||
1281 | #define CACHEOP (VR2 + 1) | |
1282 | { 0, 0, insert_CACHEOP, extract_CACHEOP, V850_OPERAND_CACHEOP, BFD_RELOC_NONE }, | |
1283 | ||
1284 | #define PREFOP (CACHEOP + 1) | |
1285 | { 0, 0, insert_PREFOP, extract_PREFOP, V850_OPERAND_PREFOP, BFD_RELOC_NONE }, | |
1286 | ||
1287 | #define IMM10U (PREFOP + 1) | |
1288 | { 0, 0, insert_IMM10U, extract_IMM10U, 0, BFD_RELOC_NONE }, | |
1cd986c5 NC |
1289 | }; |
1290 | ||
1291 | \f | |
1292 | /* Reg - Reg instruction format (Format I). */ | |
1293 | #define IF1 {R1, R2} | |
1294 | ||
1295 | /* Imm - Reg instruction format (Format II). */ | |
1296 | #define IF2 {I5, R2} | |
1297 | ||
1298 | /* Conditional branch instruction format (Format III). */ | |
1299 | #define IF3 {D9_RELAX} | |
252b5132 | 1300 | |
8ad30312 | 1301 | /* 3 operand instruction (Format VI). */ |
252b5132 RH |
1302 | #define IF6 {I16, R1, R2} |
1303 | ||
8ad30312 | 1304 | /* 3 operand instruction (Format VI). */ |
252b5132 RH |
1305 | #define IF6U {I16U, R1, R2} |
1306 | ||
1cd986c5 NC |
1307 | /* Conditional branch instruction format (Format VII). */ |
1308 | #define IF7 {D17_16} | |
252b5132 RH |
1309 | |
1310 | \f | |
1311 | /* The opcode table. | |
1312 | ||
1313 | The format of the opcode table is: | |
1314 | ||
1315 | NAME OPCODE MASK { OPERANDS } MEMOP PROCESSOR | |
1316 | ||
1317 | NAME is the name of the instruction. | |
1318 | OPCODE is the instruction opcode. | |
1319 | MASK is the opcode mask; this is used to tell the disassembler | |
1320 | which bits in the actual opcode must match OPCODE. | |
1321 | OPERANDS is the list of operands. | |
1322 | MEMOP specifies which operand (if any) is a memory operand. | |
1323 | PROCESSORS specifies which CPU(s) support the opcode. | |
47b0e7ad | 1324 | |
252b5132 RH |
1325 | The disassembler reads the table in order and prints the first |
1326 | instruction which matches, so this table is sorted to put more | |
1327 | specific instructions before more general instructions. It is also | |
1328 | sorted by major opcode. | |
1329 | ||
1330 | The table is also sorted by name. This is used by the assembler. | |
1331 | When parsing an instruction the assembler finds the first occurance | |
1332 | of the name of the instruciton in this table and then attempts to | |
1333 | match the instruction's arguments with description of the operands | |
1334 | associated with the entry it has just found in this table. If the | |
1335 | match fails the assembler looks at the next entry in this table. | |
1336 | If that entry has the same name as the previous entry, then it | |
1337 | tries to match the instruction against that entry and so on. This | |
1338 | is how the assembler copes with multiple, different formats of the | |
1339 | same instruction. */ | |
1340 | ||
1341 | const struct v850_opcode v850_opcodes[] = | |
1342 | { | |
1cd986c5 | 1343 | /* Standard instructions. */ |
252b5132 RH |
1344 | { "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
1345 | { "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL }, | |
1cd986c5 | 1346 | |
252b5132 | 1347 | { "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL }, |
47b0e7ad | 1348 | |
78c8d46c | 1349 | { "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
252b5132 | 1350 | |
252b5132 | 1351 | { "and", OP (0x0a), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
1cd986c5 | 1352 | |
252b5132 | 1353 | { "andi", OP (0x36), OP_MASK, IF6U, 0, PROCESSOR_ALL }, |
252b5132 | 1354 | |
8ad30312 | 1355 | /* Signed integer. */ |
252b5132 | 1356 | { "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1cd986c5 | 1357 | { "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
252b5132 | 1358 | { "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1cd986c5 | 1359 | { "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
8ad30312 | 1360 | /* Unsigned integer. */ |
252b5132 | 1361 | { "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
252b5132 | 1362 | { "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1cd986c5 | 1363 | { "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
252b5132 | 1364 | { "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
8ad30312 | 1365 | /* Common. */ |
252b5132 RH |
1366 | { "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1367 | { "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
8ad30312 | 1368 | /* Others. */ |
252b5132 | 1369 | { "bc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1cd986c5 NC |
1370 | { "bf", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1371 | { "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
252b5132 | 1372 | { "bnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1cd986c5 | 1373 | { "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
252b5132 | 1374 | { "bnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1cd986c5 | 1375 | { "bp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
252b5132 RH |
1376 | { "br", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1377 | { "bsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
1cd986c5 NC |
1378 | { "bt", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1379 | { "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
1380 | { "bz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
252b5132 | 1381 | |
78c8d46c NC |
1382 | /* Signed integer. */ |
1383 | { "bge", two (0x07ee, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1384 | { "bgt", two (0x07ef, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1385 | { "ble", two (0x07e7, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1386 | { "blt", two (0x07e6, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1387 | /* Unsigned integer. */ | |
1388 | { "bh", two (0x07eb, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1389 | { "bl", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1390 | { "bnh", two (0x07e3, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1391 | { "bnl", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1392 | /* Common. */ | |
1393 | { "be", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1394 | { "bne", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1395 | /* Others. */ | |
1396 | { "bc", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1397 | { "bf", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1398 | { "bn", two (0x07e4, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1399 | { "bnc", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1400 | { "bnv", two (0x07e8, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1401 | { "bnz", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1402 | { "bp", two (0x07ec, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1403 | { "br", two (0x07e5, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1404 | { "bsa", two (0x07ed, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1405 | { "bt", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1406 | { "bv", two (0x07e0, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1407 | { "bz", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP }, | |
1408 | /* Bcond disp17 Gas local alias(not defined in spec). */ | |
1409 | ||
1410 | /* Signed integer. */ | |
1411 | { "bge17", two (0x07ee, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1412 | { "bgt17", two (0x07ef, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1413 | { "ble17", two (0x07e7, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1414 | { "blt17", two (0x07e6, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1415 | /* Unsigned integer. */ | |
1416 | { "bh17", two (0x07eb, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1417 | { "bl17", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1418 | { "bnh17", two (0x07e3, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1419 | { "bnl17", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1420 | /* Common. */ | |
1421 | { "be17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1422 | { "bne17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1423 | /* Others. */ | |
1424 | { "bc17", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1425 | { "bf17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1426 | { "bn17", two (0x07e4, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1427 | { "bnc17", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1428 | { "bnv17", two (0x07e8, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1429 | { "bnz17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1430 | { "bp17", two (0x07ec, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1431 | { "br17", two (0x07e5, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1432 | { "bsa17", two (0x07ed, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1433 | { "bt17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1434 | { "bv17", two (0x07e0, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1435 | { "bz17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1436 | ||
1cd986c5 | 1437 | { "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, |
252b5132 | 1438 | |
1cd986c5 | 1439 | { "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, |
252b5132 | 1440 | |
78c8d46c NC |
1441 | /* v850e3v5 bitfield instructions. */ |
1442 | { "bins", two (0x07e0, 0x0090), two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 0, PROCESSOR_V850E3V5_UP }, | |
1443 | { "bins", two (0x07e0, 0x00b0), two (0x07e0, 0x07f1), {R1, POS_M, WIDTH_M, R2}, 0, PROCESSOR_V850E3V5_UP }, | |
1444 | { "bins", two (0x07e0, 0x00d0), two (0x07e0, 0x07f1), {R1, POS_L, WIDTH_L, R2}, 0, PROCESSOR_V850E3V5_UP }, | |
1445 | /* Gas local alias(not defined in spec). */ | |
1446 | { "binsu",two (0x07e0, 0x0090), two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1447 | { "binsm",two (0x07e0, 0x00b0), two (0x07e0, 0x07f1), {R1, POS_M, WIDTH_M, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1448 | { "binsl",two (0x07e0, 0x00d0), two (0x07e0, 0x07f1), {R1, POS_L, WIDTH_L, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1449 | ||
1450 | { "cache", two (0xe7e0, 0x0160), two (0xe7e0, 0x07ff), {CACHEOP, R1}, 2, PROCESSOR_V850E3V5_UP }, | |
1451 | ||
1cd986c5 NC |
1452 | { "callt", one (0x0200), one (0xffc0), {IMM6}, 0, PROCESSOR_NOT_V850 }, |
1453 | ||
78c8d46c | 1454 | { "caxi", two (0x07e0, 0x00ee), two (0x07e0, 0x07ff), {R1, R2, R3}, 1, PROCESSOR_V850E2_UP }, |
1cd986c5 NC |
1455 | |
1456 | { "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, | |
1457 | { "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, | |
1458 | ||
1459 | { "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
1460 | { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
1461 | ||
1462 | { "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
1463 | { "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL }, | |
1464 | ||
1465 | { "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, | |
1466 | ||
78c8d46c NC |
1467 | { "dbcp", one (0xe840), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
1468 | ||
1469 | { "dbhvtrap", one (0xe040), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, | |
1470 | ||
1471 | { "dbpush", two (0x5fe0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP }, | |
1472 | ||
1cd986c5 NC |
1473 | { "dbret", two (0x07e0, 0x0146), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, |
1474 | ||
78c8d46c NC |
1475 | { "dbtag", two (0xcfe0, 0x0160), two (0xffe0, 0x07ff), {IMM10U}, 0, PROCESSOR_V850E3V5_UP }, |
1476 | ||
1cd986c5 NC |
1477 | { "dbtrap", one (0xf840), one (0xffff), {0}, 0, PROCESSOR_NOT_V850 }, |
1478 | ||
1479 | { "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, | |
1480 | ||
1481 | { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x0000), {IMM5, LIST12, R2_DISPOSE},3, PROCESSOR_NOT_V850 }, | |
1482 | { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 }, | |
1483 | ||
1484 | { "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
1485 | ||
1486 | { "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
1487 | { "divh", OP (0x02), OP_MASK, {R1_NOTR0, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
1488 | ||
1489 | { "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, | |
1490 | ||
1491 | { "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
1492 | ||
1493 | { "divhun", two (0x07e0, 0x0282), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, | |
1494 | { "divn", two (0x07e0, 0x02c0), two (0x07e0, 0x07c3), {I5DIV2, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, | |
1495 | ||
78c8d46c | 1496 | { "divq", two (0x07e0, 0x02fc), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1cd986c5 | 1497 | |
78c8d46c | 1498 | { "divqu", two (0x07e0, 0x02fe), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1cd986c5 NC |
1499 | |
1500 | { "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
1501 | ||
1502 | { "divun", two (0x07e0, 0x02c2), two (0x07e0, 0x07c3), {I5DIV2, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, | |
1503 | ||
78c8d46c NC |
1504 | { "dst", two (0x07e0, 0x0134), two (0xfffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
1505 | ||
1cd986c5 NC |
1506 | { "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, |
1507 | ||
78c8d46c NC |
1508 | { "eiret", two (0x07e0, 0x0148), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP }, |
1509 | ||
1510 | { "est", two (0x07e0, 0x0132), two (0xfffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, | |
1cd986c5 | 1511 | |
78c8d46c | 1512 | { "feret", two (0x07e0, 0x014a), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP }, |
1cd986c5 | 1513 | |
78c8d46c | 1514 | { "fetrap", one (0x0040), one (0x87ff), {I4U_NOTIMM0}, 0, PROCESSOR_V850E2_UP }, |
1cd986c5 NC |
1515 | |
1516 | { "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, | |
1517 | ||
78c8d46c | 1518 | { "hsh", two (0x07e0, 0x0346), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1cd986c5 NC |
1519 | |
1520 | { "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
1521 | ||
78c8d46c NC |
1522 | { "hvcall", two (0xd7e0, 0x4160), two (0xffe0, 0x41ff), {VECTOR8}, 0, PROCESSOR_V850E3V5_UP }, |
1523 | { "hvtrap", two (0x07e0, 0x0110), two (0xffe0, 0xffff), {VECTOR5}, 0, PROCESSOR_V850E3V5_UP }, | |
1524 | ||
1525 | { "jarl", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, PROCESSOR_V850E3V5_UP}, | |
1cd986c5 | 1526 | { "jarl", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL}, |
78c8d46c NC |
1527 | { "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP }, |
1528 | /* Gas local alias (not defined in spec). */ | |
1529 | { "jarlr", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS}, | |
1530 | /* Gas local alias of jarl imm22 (not defined in spec). */ | |
1cd986c5 | 1531 | { "jarl22", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS}, |
78c8d46c NC |
1532 | /* Gas local alias of jarl imm32 (not defined in spec). */ |
1533 | { "jarl32", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
1534 | { "jarlw", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
1cd986c5 | 1535 | |
78c8d46c NC |
1536 | { "jmp", two (0x06e0, 0x0000), two (0xffe0, 0x0001), {D32_31, R1}, 2, PROCESSOR_V850E3V5_UP }, |
1537 | { "jmp", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2 | PROCESSOR_V850E2V3 }, | |
1cd986c5 NC |
1538 | { "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL }, |
1539 | /* Gas local alias of jmp disp22(not defined in spec). */ | |
1540 | { "jmp22", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS }, | |
1541 | /* Gas local alias of jmp disp32(not defined in spec). */ | |
78c8d46c NC |
1542 | { "jmp32", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
1543 | { "jmpw", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
1cd986c5 NC |
1544 | |
1545 | { "jr", two (0x0780, 0x0000), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL }, | |
78c8d46c | 1546 | { "jr", one (0x02e0), one (0xffff), {D32_31_PCREL}, 0, PROCESSOR_V850E2_UP }, |
1cd986c5 NC |
1547 | /* Gas local alias of mov imm22(not defined in spec). */ |
1548 | { "jr22", two (0x0780, 0x0000), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS }, | |
1549 | /* Gas local alias of mov imm32(not defined in spec). */ | |
78c8d46c | 1550 | { "jr32", one (0x02e0), one (0xffff), {D32_31_PCREL}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, |
1cd986c5 NC |
1551 | |
1552 | /* Alias of bcond (same as CA850). */ | |
252b5132 RH |
1553 | { "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1554 | { "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
1555 | { "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
1556 | { "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
8ad30312 | 1557 | /* Unsigned integer. */ |
252b5132 RH |
1558 | { "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1559 | { "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
1560 | { "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
1561 | { "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
8ad30312 | 1562 | /* Common. */ |
252b5132 RH |
1563 | { "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1564 | { "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
8ad30312 | 1565 | /* Others. */ |
252b5132 RH |
1566 | { "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
1567 | { "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
1568 | { "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
1569 | { "jp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
1570 | { "jc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
1571 | { "jnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
1572 | { "jz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
1573 | { "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, | |
252b5132 | 1574 | { "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
47b0e7ad | 1575 | |
252b5132 | 1576 | |
78c8d46c | 1577 | { "ldacc", two (0x07e0, 0x0bc4), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, |
1cd986c5 NC |
1578 | |
1579 | { "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 2, PROCESSOR_ALL }, | |
78c8d46c NC |
1580 | { "ld.b", two (0x0780, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP }, |
1581 | { "ld.b23", two (0x0780, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
1cd986c5 NC |
1582 | |
1583 | { "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, | |
78c8d46c NC |
1584 | { "ld.bu", two (0x07a0, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP }, |
1585 | { "ld.bu23", two (0x07a0, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
1586 | ||
1587 | { "ld.dw", two (0x07a0, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3_EVEN}, 2, PROCESSOR_V850E3V5_UP }, | |
1588 | { "ld.dw23", two (0x07a0, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3_EVEN}, 2, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1cd986c5 NC |
1589 | |
1590 | { "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, PROCESSOR_ALL }, | |
78c8d46c NC |
1591 | { "ld.h", two (0x0780, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP }, |
1592 | { "ld.h23", two (0x0780, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
1cd986c5 NC |
1593 | |
1594 | { "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, | |
78c8d46c NC |
1595 | { "ld.hu", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP }, |
1596 | { "ld.hu23", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
1cd986c5 NC |
1597 | |
1598 | { "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, PROCESSOR_ALL }, | |
78c8d46c NC |
1599 | { "ld.w", two (0x0780, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP }, |
1600 | { "ld.w23", two (0x0780, 0x0009), two (0x07e0, 0x001f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
252b5132 | 1601 | |
78c8d46c | 1602 | { "ldl.w", two (0x07e0, 0x0378), two (0xffe0, 0x07ff), {R1, R3}, 1, PROCESSOR_V850E3V5_UP }, |
1cd986c5 | 1603 | |
78c8d46c NC |
1604 | { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP }, |
1605 | { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP }, | |
1606 | { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, OLDSR2}, 0, (PROCESSOR_ALL & (~ PROCESSOR_V850E3V5_UP)) }, | |
1cd986c5 | 1607 | |
78c8d46c NC |
1608 | { "ldtc.gr", two (0x07e0, 0x0032), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E3V5_UP }, |
1609 | { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP }, | |
1610 | { "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP }, | |
1cd986c5 | 1611 | |
78c8d46c NC |
1612 | { "ldtc.vr", two (0x07e0, 0x0832), two (0x07e0, 0xffff), {R1, VR2}, 0, PROCESSOR_V850E3V5_UP }, |
1613 | { "ldtc.pc", two (0x07e0, 0xf832), two (0x07e0, 0xffff), {R1}, 0, PROCESSOR_V850E3V5_UP }, | |
1cd986c5 | 1614 | |
78c8d46c NC |
1615 | { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP }, |
1616 | { "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP }, | |
1617 | ||
1618 | { "loop", two (0x06e0, 0x0001), two (0xffe0, 0x0001), {R1, D16_LOOP}, 0, PROCESSOR_V850E3V5_UP }, | |
1619 | ||
1620 | { "macacc", two (0x07e0, 0x0bc0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, | |
1621 | ||
1622 | { "mac", two (0x07e0, 0x03c0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, PROCESSOR_V850E2_UP }, | |
1623 | ||
1624 | { "macu", two (0x07e0, 0x03e0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, PROCESSOR_V850E2_UP }, | |
1625 | ||
1626 | { "macuacc", two (0x07e0, 0x0bc2), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, | |
1cd986c5 NC |
1627 | |
1628 | { "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
1629 | { "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
1630 | { "mov", one (0x0620), one (0xffe0), {IMM32, R1}, 0, PROCESSOR_NOT_V850 }, | |
1631 | /* Gas local alias of mov imm32(not defined in spec). */ | |
1632 | { "movl", one (0x0620), one (0xffe0), {IMM32, R1}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_ALIAS }, | |
1633 | ||
1634 | { "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
1635 | ||
1636 | { "movhi", OP (0x32), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
1637 | ||
1638 | { "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
1639 | { "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
1640 | ||
1641 | { "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
1642 | { "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
1643 | ||
1644 | { "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
1645 | ||
1646 | { "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
1647 | { "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0, PROCESSOR_NOT_V850 }, | |
1648 | ||
1649 | { "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL }, | |
1650 | ||
1651 | { "not", OP (0x01), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
1652 | ||
1653 | { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, | |
1654 | { "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, | |
1655 | ||
1656 | { "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
1657 | ||
1658 | { "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL }, | |
1659 | ||
78c8d46c NC |
1660 | { "popsp", two (0x67e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP }, |
1661 | ||
1662 | { "pref", two (0xdfe0, 0x0160), two (0xffe0, 0x07ff), {PREFOP, R1}, 2, PROCESSOR_V850E3V5_UP }, | |
1663 | ||
1cd986c5 NC |
1664 | { "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 }, |
1665 | { "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16LO},0, PROCESSOR_NOT_V850 }, | |
1666 | { "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16HI},0, PROCESSOR_NOT_V850 }, | |
1667 | { "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0, PROCESSOR_NOT_V850 }, | |
1668 | { "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0, PROCESSOR_NOT_V850 }, | |
1669 | ||
78c8d46c NC |
1670 | { "pushsp", two (0x47e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP }, |
1671 | ||
1672 | { "rotl", two (0x07e0, 0x00c6), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, | |
1673 | { "rotl", two (0x07e0, 0x00c4), two (0x07e0, 0x07ff), {I5U, R2, R3}, 0, PROCESSOR_V850E3V5_UP }, | |
1674 | ||
1cd986c5 NC |
1675 | { "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, |
1676 | ||
78c8d46c | 1677 | { "sar", two (0x07e0, 0x00a2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1cd986c5 NC |
1678 | { "sar", OP (0x15), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, |
1679 | { "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, | |
1680 | ||
1681 | { "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 }, | |
1682 | ||
78c8d46c | 1683 | { "satadd", two (0x07e0, 0x03ba), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1cd986c5 NC |
1684 | { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, |
1685 | { "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
1686 | ||
78c8d46c | 1687 | { "satsub", two (0x07e0, 0x039a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1cd986c5 NC |
1688 | { "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
1689 | ||
1690 | { "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
1691 | ||
1692 | { "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, | |
1693 | ||
78c8d46c | 1694 | { "sbf", two (0x07e0, 0x0380), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1cd986c5 | 1695 | |
78c8d46c | 1696 | { "sch0l", two (0x07e0, 0x0364), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1cd986c5 | 1697 | |
78c8d46c | 1698 | { "sch0r", two (0x07e0, 0x0360), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1cd986c5 | 1699 | |
78c8d46c | 1700 | { "sch1l", two (0x07e0, 0x0366), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1cd986c5 | 1701 | |
78c8d46c | 1702 | { "sch1r", two (0x07e0, 0x0362), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1cd986c5 NC |
1703 | |
1704 | { "sdivhn", two (0x07e0, 0x0180), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, | |
1705 | { "sdivhun", two (0x07e0, 0x0182), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, | |
1706 | { "sdivn", two (0x07e0, 0x01c0), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, | |
1707 | { "sdivun", two (0x07e0, 0x01c2), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION }, | |
1708 | ||
1709 | { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, | |
1710 | { "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, | |
1711 | ||
1712 | { "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL }, | |
1713 | ||
78c8d46c | 1714 | { "shl", two (0x07e0, 0x00c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1cd986c5 NC |
1715 | { "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, |
1716 | { "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, | |
1717 | ||
78c8d46c | 1718 | { "shr", two (0x07e0, 0x0082), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP }, |
1cd986c5 NC |
1719 | { "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, |
1720 | { "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, | |
1721 | ||
1722 | { "sld.b", one (0x0300), one (0x0780), {D7U, EP, R2}, 2, PROCESSOR_ALL }, | |
1723 | ||
1724 | { "sld.bu", one (0x0060), one (0x07f0), {D4U, EP, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, | |
1725 | ||
1726 | { "sld.h", one (0x0400), one (0x0780), {D8_7U,EP, R2}, 2, PROCESSOR_ALL }, | |
1727 | ||
1728 | { "sld.hu", one (0x0070), one (0x07f0), {D5_4U,EP, R2_NOTR0}, 2, PROCESSOR_NOT_V850 }, | |
1729 | ||
1730 | { "sld.w", one (0x0500), one (0x0781), {D8_6U,EP, R2}, 2, PROCESSOR_ALL }, | |
1731 | ||
78c8d46c NC |
1732 | { "snooze", two (0x0fe0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
1733 | ||
1cd986c5 NC |
1734 | { "sst.b", one (0x0380), one (0x0780), {R2, D7U, EP}, 3, PROCESSOR_ALL }, |
1735 | ||
1736 | { "sst.h", one (0x0480), one (0x0780), {R2, D8_7U,EP}, 3, PROCESSOR_ALL }, | |
1737 | ||
1738 | { "sst.w", one (0x0501), one (0x0781), {R2, D8_6U,EP}, 3, PROCESSOR_ALL }, | |
1739 | ||
78c8d46c NC |
1740 | { "stacch", two (0x07e0, 0x0bca), two (0x07ff, 0xffff), {R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, |
1741 | { "staccl", two (0x07e0, 0x0bc8), two (0x07ff, 0xffff), {R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION }, | |
1cd986c5 NC |
1742 | |
1743 | { "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 3, PROCESSOR_ALL }, | |
78c8d46c NC |
1744 | { "st.b", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_UP }, |
1745 | { "st.b23", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
1746 | ||
1747 | { "st.dw", two (0x07a0, 0x000f), two (0xffe0, 0x001f), {R3_EVEN, D23_ALIGN1, R1}, 3, PROCESSOR_V850E3V5_UP }, | |
1748 | { "st.dw23", two (0x07a0, 0x000f), two (0xffe0, 0x001f), {R3_EVEN, D23_ALIGN1, R1}, 3, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS }, | |
1cd986c5 NC |
1749 | |
1750 | { "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, PROCESSOR_ALL }, | |
78c8d46c NC |
1751 | { "st.h", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP }, |
1752 | { "st.h23", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
1cd986c5 NC |
1753 | |
1754 | { "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, PROCESSOR_ALL }, | |
78c8d46c NC |
1755 | { "st.w", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP }, |
1756 | { "st.w23", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS }, | |
1757 | ||
1758 | { "stc.w", two (0x07e0, 0x037a), two (0xffe0, 0x07ff), {R3, R1}, 2, PROCESSOR_V850E3V5_UP }, | |
1759 | ||
1760 | { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, | |
1761 | { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, | |
1762 | { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {OLDSR1, R2}, 0, (PROCESSOR_ALL & (~ PROCESSOR_V850E3V5_UP)) }, | |
1763 | ||
1764 | { "sttc.gr", two (0x07e0, 0x0052), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E3V5_UP }, | |
1765 | { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, | |
1766 | { "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, | |
1767 | { "sttc.vr", two (0x07e0, 0x0852), two (0x07e0, 0xffff), {VR1, R2}, 0, PROCESSOR_V850E3V5_UP }, | |
1768 | { "sttc.pc", two (0x07e0, 0xf852), two (0x07e0, 0xffff), {R2}, 0, PROCESSOR_V850E3V5_UP }, | |
1cd986c5 | 1769 | |
78c8d46c NC |
1770 | { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP }, |
1771 | { "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP }, | |
252b5132 | 1772 | |
1cd986c5 NC |
1773 | { "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
1774 | ||
1775 | { "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
1776 | ||
1777 | { "switch", one (0x0040), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, | |
1778 | ||
1779 | { "sxb", one (0x00a0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, | |
1780 | ||
1781 | { "sxh", one (0x00e0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, | |
1782 | ||
78c8d46c NC |
1783 | { "tlbai", two (0x87e0, 0x8960), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
1784 | { "tlbr", two (0x87e0, 0xe960), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, | |
1785 | { "tlbs", two (0x87e0, 0xc160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, | |
1786 | { "tlbvi", two (0x87e0, 0x8160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, | |
1787 | { "tlbw", two (0x87e0, 0xe160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, | |
1788 | ||
1cd986c5 NC |
1789 | { "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL }, |
1790 | ||
1791 | { "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
1792 | ||
1793 | { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL }, | |
1794 | { "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 }, | |
1795 | ||
1796 | { "xor", OP (0x09), OP_MASK, IF1, 0, PROCESSOR_ALL }, | |
1797 | ||
1798 | { "xori", OP (0x35), OP_MASK, IF6U, 0, PROCESSOR_ALL }, | |
1799 | ||
1800 | { "zxb", one (0x0080), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, | |
1801 | ||
1802 | { "zxh", one (0x00c0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 }, | |
1803 | ||
1804 | /* Floating point operation. */ | |
78c8d46c NC |
1805 | { "absf.d", two (0x07e0, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, |
1806 | { "absf.s", two (0x07e0, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1807 | { "addf.d", two (0x07e0, 0x0470), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1808 | { "addf.s", two (0x07e0, 0x0460), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1809 | { "ceilf.dl", two (0x07e2, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1810 | { "ceilf.dul", two (0x07f2, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1811 | { "ceilf.duw", two (0x07f2, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1812 | { "ceilf.dw", two (0x07e2, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1813 | { "ceilf.sl", two (0x07e2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1814 | { "ceilf.sul", two (0x07f2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1815 | { "ceilf.suw", two (0x07f2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1816 | { "ceilf.sw", two (0x07e2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1817 | { "ceilf.sw", two (0x07e2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1818 | { "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0ff1), {FFF, R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP }, | |
1cd986c5 | 1819 | /* Default value for FFF is 0(not defined in spec). */ |
78c8d46c NC |
1820 | { "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP }, |
1821 | { "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07f1), {FFF, R1, R2, R3_NOTR0}, 0, PROCESSOR_V850E2V3_UP }, | |
1cd986c5 | 1822 | /* Default value for FFF is 0(not defined in spec). */ |
78c8d46c NC |
1823 | { "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07ff), {R1, R2, R3_NOTR0}, 0, PROCESSOR_V850E2V3_UP }, |
1824 | { "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87f1), {FLOAT_CCCC, R2_EVEN, R1_EVEN, FFF}, 0, PROCESSOR_V850E2V3_UP }, | |
1825 | { "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87ff), {FLOAT_CCCC, R2_EVEN, R1_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1826 | { "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87f1), {FLOAT_CCCC, R2, R1, FFF}, 0, PROCESSOR_V850E2V3_UP }, | |
1827 | { "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87ff), {FLOAT_CCCC, R2, R1}, 0, PROCESSOR_V850E2V3_UP }, | |
1828 | { "cvtf.dl", two (0x07e4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1829 | { "cvtf.ds", two (0x07e3, 0x0452), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1830 | { "cvtf.dul", two (0x07f4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1831 | { "cvtf.duw", two (0x07f4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1832 | { "cvtf.dw", two (0x07e4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1833 | { "cvtf.ld", two (0x07e1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1834 | { "cvtf.ls", two (0x07e1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1835 | { "cvtf.sd", two (0x07e2, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1836 | { "cvtf.sl", two (0x07e4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1837 | { "cvtf.sul", two (0x07f4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1838 | { "cvtf.suw", two (0x07f4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1839 | { "cvtf.sw", two (0x07e4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1840 | { "cvtf.uld", two (0x07f1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1841 | { "cvtf.uls", two (0x07f1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1842 | { "cvtf.uwd", two (0x07f0, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1843 | { "cvtf.uws", two (0x07f0, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1844 | { "cvtf.wd", two (0x07e0, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1845 | { "cvtf.ws", two (0x07e0, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1846 | { "divf.d", two (0x07e0, 0x047e), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1847 | { "divf.s", two (0x07e0, 0x046e), two (0x07e0, 0x07ff), {R1_NOTR0, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1848 | { "floorf.dl", two (0x07e3, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1849 | { "floorf.dul", two (0x07f3, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1850 | { "floorf.duw", two (0x07f3, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1851 | { "floorf.dw", two (0x07e3, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1852 | { "floorf.sl", two (0x07e3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1853 | { "floorf.sul", two (0x07f3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1854 | { "floorf.suw", two (0x07f3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1855 | { "floorf.sw", two (0x07e3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1856 | { "maddf.s", two (0x07e0, 0x0500), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3_UP }, | |
1857 | { "maxf.d", two (0x07e0, 0x0478), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1858 | { "maxf.s", two (0x07e0, 0x0468), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1859 | { "minf.d", two (0x07e0, 0x047a), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1860 | { "minf.s", two (0x07e0, 0x046a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1861 | { "msubf.s", two (0x07e0, 0x0520), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3_UP }, | |
1862 | { "mulf.d", two (0x07e0, 0x0474), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1863 | { "mulf.s", two (0x07e0, 0x0464), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1864 | { "negf.d", two (0x07e1, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1865 | { "negf.s", two (0x07e1, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1866 | { "nmaddf.s", two (0x07e0, 0x0540), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3_UP }, | |
1867 | { "nmsubf.s", two (0x07e0, 0x0560), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3_UP }, | |
1868 | { "recipf.d", two (0x07e1, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1869 | { "recipf.s", two (0x07e1, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1870 | ||
1871 | { "roundf.dl", two (0x07e0, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, | |
1872 | { "roundf.dul", two (0x07f0, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, | |
1873 | { "roundf.duw", two (0x07f0, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, | |
1874 | { "roundf.dw", two (0x07e0, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, | |
1875 | { "roundf.sl", two (0x07e0, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, | |
1876 | { "roundf.sul", two (0x07f0, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, | |
1877 | { "roundf.suw", two (0x07f0, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, | |
1878 | { "roundf.sw", two (0x07e0, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION }, | |
1879 | ||
1880 | { "rsqrtf.d", two (0x07e2, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1881 | { "rsqrtf.s", two (0x07e2, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1882 | { "sqrtf.d", two (0x07e0, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1883 | { "sqrtf.s", two (0x07e0, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1884 | { "subf.d", two (0x07e0, 0x0472), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1885 | { "subf.s", two (0x07e0, 0x0462), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1886 | { "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xfff1), {FFF}, 0, PROCESSOR_V850E2V3_UP }, | |
1887 | { "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, | |
1888 | { "trncf.dl", two (0x07e1, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1889 | { "trncf.dul", two (0x07f1, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1890 | { "trncf.duw", two (0x07f1, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1891 | { "trncf.dw", two (0x07e1, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1892 | { "trncf.sl", two (0x07e1, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP }, | |
1893 | { "trncf.sul", two (0x07f1, 0x0444), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1894 | { "trncf.suw", two (0x07f1, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1895 | { "trncf.sw", two (0x07e1, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP }, | |
1cd986c5 NC |
1896 | |
1897 | /* Special instruction (from gdb) mov 1, r0. */ | |
1898 | { "breakpoint", one (0x0001), one (0xffff), {UNUSED}, 0, PROCESSOR_ALL }, | |
1899 | ||
78c8d46c | 1900 | { "synci", one (0x001c), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP }, |
1cd986c5 | 1901 | |
78c8d46c NC |
1902 | { "synce", one (0x001d), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, |
1903 | { "syncm", one (0x001e), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, | |
1904 | { "syncp", one (0x001f), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, | |
1905 | { "syscall", two (0xd7e0, 0x0160), two (0xffe0, 0xc7ff), {V8}, 0, PROCESSOR_V850E2V3_UP }, | |
1906 | /* Alias of syncp. */ | |
1907 | { "sync", one (0x001f), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_ALIAS }, | |
1908 | { "rmtrap", one (0xf040), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, | |
1909 | { "rie", one (0x0040), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP }, | |
1910 | { "rie", two (0x07f0, 0x0000), two (0x07f0, 0xffff), {RIE_IMM5,RIE_IMM4}, 0, PROCESSOR_V850E2V3_UP }, | |
1cd986c5 NC |
1911 | |
1912 | { 0, 0, 0, {0}, 0, 0 }, | |
252b5132 RH |
1913 | } ; |
1914 | ||
1915 | const int v850_num_opcodes = | |
1916 | sizeof (v850_opcodes) / sizeof (v850_opcodes[0]); |