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6d1e1ee8 C |
1 | #include "ansidecl.h" |
2 | #include "opcode/v850.h" | |
3 | ||
4 | /* regular opcode */ | |
5 | #define OP(x) ((x & 0x3f) << 5) | |
6 | #define OP_MASK OP(0x3f) | |
7 | ||
8 | /* conditional branch opcode */ | |
9 | #define BOP(x) ((0x0b << 7) | (x & 0x0f)) | |
10 | #define BOP_MASK ((0x0b << 7) | 0x0f) | |
11 | ||
12 | /* one-word opcodes */ | |
13 | #define one(x) ((unsigned int) (x)) | |
14 | ||
15 | /* two-word opcodes */ | |
16 | #define two(x,y) ((unsigned int) (y) | ((unsigned int) (x) << 16)) | |
17 | ||
18 | ||
19 | \f | |
20 | const struct v850_operand v850_operands[] = { | |
21 | #define UNUSED 0 | |
22 | { 0, 0 }, | |
23 | ||
24 | /* The R1 field in a format 1, 6, 7, or 9 insn. */ | |
25 | #define R1 (UNUSED+1) | |
26 | { 5, 0 }, | |
27 | ||
28 | /* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */ | |
29 | #define R2 (R1+1) | |
30 | { 5, 11 }, | |
31 | ||
32 | /* The IMM5 field in a format 2 insn. */ | |
33 | #define I5 (R2+1) | |
34 | { 5, 0 }, | |
35 | ||
36 | #define IMM16 field in a format 6 insn. */ | |
37 | #define I16 (I5+1) | |
38 | { 16, 0 }, | |
39 | ||
40 | /* The DISP6 field in a format 4 insn. */ | |
41 | #define D6 (I16+1) | |
42 | { 6, 1 }, | |
43 | ||
44 | /* The DISP8 field in a format 3 insn. */ | |
45 | #define D8 (D6+1) | |
46 | { 9, 0 }, | |
47 | ||
48 | /* The DISP16 field in a format 6 insn. */ | |
49 | #define D16 (D8+1) | |
50 | { 16, 0 }, | |
51 | ||
52 | /* The DISP22 field in a format 4 insn. */ | |
53 | #define D22 (D16+1) | |
54 | { 16, 0 } | |
55 | } ; | |
56 | ||
57 | \f | |
58 | /* reg-reg instruction format (Format I) */ | |
59 | #define IF1 {R1, R2} | |
60 | ||
61 | /* imm-reg instruction format (Format II) */ | |
62 | #define IF2 {I5, R2} | |
63 | ||
64 | /* conditional branch instruction format (Format III) */ | |
65 | #define IF3 {D8} | |
66 | ||
67 | /* 16-bit load/store instruction (Format IV) */ | |
68 | #define IF4 {D6} | |
69 | ||
70 | /* Jump instruction (Format V) */ | |
71 | #define IF5 {D22} | |
72 | ||
73 | /* 3 operand instruction (Format VI) */ | |
74 | #define IF6 {R1, R2, I16} | |
75 | ||
76 | /* 32-bit load/store instruction (Format VII) */ | |
77 | #define IF7 {R1, R2, D16} | |
78 | ||
79 | /* Bit manipulation function | |
80 | ||
81 | ||
82 | \f | |
83 | /* The opcode table. | |
84 | ||
85 | The format of the opcode table is: | |
86 | ||
87 | NAME OPCODE MASK { OPERANDS } | |
88 | ||
89 | NAME is the name of the instruction. | |
90 | OPCODE is the instruction opcode. | |
91 | MASK is the opcode mask; this is used to tell the disassembler | |
92 | which bits in the actual opcode must match OPCODE. | |
93 | OPERANDS is the list of operands. | |
94 | ||
95 | The disassembler reads the table in order and prints the first | |
96 | instruction which matches, so this table is sorted to put more | |
97 | specific instructions before more general instructions. It is also | |
98 | sorted by major opcode. */ | |
99 | ||
100 | const struct v850_opcode v850_opcodes[] = { | |
101 | /* load/store instructions */ | |
102 | /* XXX */ | |
103 | ||
104 | /* arithmetic operation instructions */ | |
105 | { "add", OP(0x0e), OP_MASK, IF1 }, | |
106 | { "add", OP(0x12), OP_MASK, IF2 }, | |
107 | { "addi", OP(0x30), OP_MASK, IF6 }, | |
108 | { "sub", OP(0x0d), OP_MASK, IF1 }, | |
109 | { "subr", OP(0x0c), OP_MASK, IF1 }, | |
110 | { "mulh", OP(0x07), OP_MASK, IF1 }, | |
111 | { "mulh", OP(0x17), OP_MASK, IF2 }, | |
112 | { "mulhi", OP(0x37), OP_MASK, IF6 }, | |
113 | { "divh", OP(0x02), OP_MASK, IF1 }, | |
114 | { "cmp", OP(0x0f), OP_MASK, IF1 }, | |
115 | { "cmp", OP(0x13), OP_MASK, IF2 }, | |
116 | /* XXX missing setf */ | |
117 | ||
118 | /* saturated operation instructions */ | |
119 | { "satadd", OP(0x06), OP_MASK, IF1 }, | |
120 | { "satadd", OP(0x11), OP_MASK, IF2 }, | |
121 | { "satsub", OP(0x05), OP_MASK, IF1 }, | |
122 | { "satsubi", OP(0x33), OP_MASK, IF6 }, | |
123 | { "satsubr", OP(0x04), OP_MASK, IF1 }, | |
124 | ||
125 | /* logical operation instructions */ | |
126 | { "tst", OP(0x0b), OP_MASK, IF1 }, | |
127 | { "or", OP(0x08), OP_MASK, IF1 }, | |
128 | { "ori", OP(0x34), OP_MASK, IF6 }, | |
129 | { "and", OP(0x0a), OP_MASK, IF1 }, | |
130 | { "andi", OP(0x36), OP_MASK, IF6 }, | |
131 | { "xor", OP(0x09), OP_MASK, IF1 }, | |
132 | { "xori", OP(0x35), OP_MASK, IF6 }, | |
133 | { "not", OP(0x01), OP_MASK, IF1 }, | |
134 | { "sar", OP(0x15), OP_MASK, IF2 }, | |
135 | { "sar", two(0x07e0,0x00a0), two(0x07e0,0xffff), {R1,R2} }, | |
136 | { "shl", OP(0x16), OP_MASK, IF2 }, | |
137 | { "shl", two(0x07e0,0x00c0), two(0x07e0,0xffff), {R1,R2} }, | |
138 | { "shr", OP(0x14), OP_MASK, IF2 }, | |
139 | { "shr", two(0x07e0,0x0080), two(0x07e0,0xffff), {R1,R2} }, | |
140 | ||
141 | /* branch instructions */ | |
142 | { "bv", BOP(0x0), BOP_MASK, IF3 }, | |
143 | { "bnv", BOP(0x8), BOP_MASK, IF3 }, | |
144 | { "bc", BOP(0x1), BOP_MASK, IF3 }, | |
145 | { "bl", BOP(0x1), BOP_MASK, IF3 }, | |
146 | { "bnc", BOP(0x9), BOP_MASK, IF3 }, | |
147 | { "bnl", BOP(0x9), BOP_MASK, IF3 }, | |
148 | { "bz", BOP(0x2), BOP_MASK, IF3 }, | |
149 | { "be", BOP(0x2), BOP_MASK, IF3 }, | |
150 | { "bnz", BOP(0xa), BOP_MASK, IF3 }, | |
151 | { "bne", BOP(0xa), BOP_MASK, IF3 }, | |
152 | { "bnh", BOP(0x3), BOP_MASK, IF3 }, | |
153 | { "bh", BOP(0xb), BOP_MASK, IF3 }, | |
154 | { "bn", BOP(0x4), BOP_MASK, IF3 }, | |
155 | { "bp", BOP(0xc), BOP_MASK, IF3 }, | |
156 | { "bt", BOP(0x5), BOP_MASK, IF3 }, | |
157 | { "bsa", BOP(0xd), BOP_MASK, IF3 }, | |
158 | { "blt", BOP(0x6), BOP_MASK, IF3 }, | |
159 | { "bge", BOP(0xe), BOP_MASK, IF3 }, | |
160 | { "ble", BOP(0x7), BOP_MASK, IF3 }, | |
161 | { "bgt", BOP(0xf), BOP_MASK, IF3 }, | |
162 | ||
163 | { "jmp", one(0x0060), one(0xffe0), IF1 }, | |
164 | { "jarl", one(0x0780), one(0xf83f), { R2,D22 } }, | |
165 | { "jr", one(0x0780), one(0xffe0), { D22 } }, | |
166 | ||
167 | #if 0 | |
168 | /* bit manipulation instructions */ | |
169 | { "set1", one(0x07c0), one(0xc7e0), {B3, R1, D16} }, | |
170 | { "not1", one(0x47c0), one(0xc7e0), {B3, R1, D16} }, | |
171 | { "clr1", one(0x87c0), one(0xc7e0), {B3, R1, D16} }, | |
172 | { "tst1", one(0xc7c0), one(0xc7e0), {B3, R1, D16} }, | |
173 | #endif | |
174 | ||
175 | /* special instructions */ | |
176 | { "di", two(0x07e0,0x0160), two(0xffff,0xffff), {0} }, | |
177 | { "ei", two(0x87e0,0x0160), two(0xffff,0xffff), {0} }, | |
178 | { "halt", two(0x07e0,0x0120), two(0xffff,0xffff), {0} }, | |
179 | { "reti", two(0x07e0,0x0140), two(0xffff,0xffff), {0} }, | |
180 | #if 0 | |
181 | { "trap", two(0x07e0,0x0100), two(0xffe0,0xffff), {I5} }, | |
182 | #endif | |
183 | { "ldsr", two(0x07e0,0x0020), two(0x07e0,0xffff), {0} }, | |
184 | { "stsr", two(0x07e0,0x0040), two(0x07e0,0xffff), {0} }, | |
185 | { "nop", one(0x00), one(0xff), {0} }, | |
186 | ||
187 | } ; | |
188 | ||
189 | const int v850_num_opcodes = | |
190 | sizeof (v850_opcodes) / sizeof (v850_opcodes[0]); | |
191 |