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x86/Intel: extend MOVDIRI testing
[deliverable/binutils-gdb.git] / opcodes / v850-opc.c
CommitLineData
252b5132 1/* Assemble V850 instructions.
82704155 2 Copyright (C) 1996-2019 Free Software Foundation, Inc.
252b5132 3
9b201bb5
NC		 4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
8ad30312 7 it under the terms of the GNU General Public License as published by
9b201bb5
NC		 8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
252b5132 10
9b201bb5
NC		 11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
252b5132 15
8ad30312
NC		 16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
47b0e7ad
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
0d8dfecf 21#include "sysdep.h"
df7b86aa 22#include <stdio.h>
252b5132 23#include "opcode/v850.h"
1cd986c5 24#include "bfd.h"
252b5132
RH		 25#include "opintl.h"
26
8ad30312 27/* Regular opcodes. */
252b5132
RH		 28#define OP(x) ((x & 0x3f) << 5)
29#define OP_MASK OP (0x3f)
30
1cd986c5
NC		 31/* Conditional branch opcodes (Format III). */
32#define BOP(x) ((0x58 << 4) | (x & 0x0f))
33#define BOP_MASK ((0x78 << 4) | 0x0f)
34
35/* Conditional branch opcodes (Format VII). */
36#define BOP7(x) (0x107e0 | (x & 0xf))
37#define BOP7_MASK (0x1ffe0 | 0xf)
252b5132 38
8ad30312 39/* One-word opcodes. */
252b5132
RH		 40#define one(x) ((unsigned int) (x))
41
8ad30312 42/* Two-word opcodes. */
252b5132 43#define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16))
1cd986c5 44
252b5132
RH		 45\f
46/* The functions used to insert and extract complicated operands. */
47
48/* Note: There is a conspiracy between these functions and
49 v850_insert_operand() in gas/config/tc-v850.c. Error messages
50 containing the string 'out of range' will be ignored unless a
51 specific command line option is given to GAS. */
52
53static const char * not_valid = N_ ("displacement value is not in range and is not aligned");
54static const char * out_of_range = N_ ("displacement value is out of range");
55static const char * not_aligned = N_ ("displacement value is not aligned");
56
57static const char * immediate_out_of_range = N_ ("immediate value is out of range");
1cd986c5
NC		 58static const char * branch_out_of_range = N_ ("branch value out of range");
59static const char * branch_out_of_range_and_odd_offset = N_ ("branch value not in range and to odd offset");
60static const char * branch_to_odd_offset = N_ ("branch to odd offset");
78c8d46c
NC		 61static const char * pos_out_of_range = N_ ("position value is out of range");
62static const char * width_out_of_range = N_ ("width value is out of range");
63static const char * selid_out_of_range = N_ ("SelID is out of range");
64static const char * vector8_out_of_range = N_ ("vector8 is out of range");
65static const char * vector5_out_of_range = N_ ("vector5 is out of range");
66static const char * imm10_out_of_range = N_ ("imm10 is out of range");
67static const char * sr_selid_out_of_range = N_ ("SR/SelID is out of range");
1cd986c5
NC		 68
69int
70v850_msg_is_out_of_range (const char* msg)
71{
72 return msg == out_of_range
73 || msg == immediate_out_of_range
74 || msg == branch_out_of_range;
75}
252b5132
RH		 76
77static unsigned long
1cd986c5 78insert_i5div1 (unsigned long insn, long value, const char ** errmsg)
252b5132 79{
1cd986c5 80 if (value > 30 || value < 2)
252b5132 81 {
1cd986c5
NC		 82 if (value & 1)
83 * errmsg = _(not_valid);
252b5132 84 else
1cd986c5 85 * errmsg = _(out_of_range);
252b5132 86 }
1cd986c5
NC		 87 else if (value & 1)
88 * errmsg = _(not_aligned);
252b5132 89
1cd986c5
NC		 90 value = (32 - value)/2;
91
92 return (insn | ((value << (2+16)) & 0x3c0000));
252b5132
RH		 93}
94
95static unsigned long
1cd986c5 96extract_i5div1 (unsigned long insn, int * invalid)
252b5132 97{
1cd986c5
NC		 98 unsigned long ret = (insn & 0x003c0000) >> (16+2);
99 ret = 32 - (ret * 2);
252b5132 100
1cd986c5
NC		 101 if (invalid != 0)
102 *invalid = (ret > 30 || ret < 2) ? 1 : 0;
252b5132
RH		 103 return ret;
104}
105
106static unsigned long
1cd986c5 107insert_i5div2 (unsigned long insn, long value, const char ** errmsg)
252b5132 108{
1cd986c5 109 if (value > 30 || value < 4)
252b5132 110 {
1cd986c5
NC		 111 if (value & 1)
112 * errmsg = _(not_valid);
252b5132 113 else
1cd986c5 114 * errmsg = _(out_of_range);
252b5132 115 }
1cd986c5
NC		 116 else if (value & 1)
117 * errmsg = _(not_aligned);
252b5132 118
1cd986c5
NC		 119 value = (32 - value)/2;
120
78c8d46c 121 return insn | ((value << (2 + 16)) & 0x3c0000);
252b5132
RH		 122}
123
124static unsigned long
1cd986c5 125extract_i5div2 (unsigned long insn, int * invalid)
252b5132 126{
1cd986c5
NC		 127 unsigned long ret = (insn & 0x003c0000) >> (16+2);
128 ret = 32 - (ret * 2);
252b5132 129
1cd986c5
NC		 130 if (invalid != 0)
131 *invalid = (ret > 30 || ret < 4) ? 1 : 0;
132 return ret;
252b5132
RH		 133}
134
135static unsigned long
1cd986c5 136insert_i5div3 (unsigned long insn, long value, const char ** errmsg)
252b5132 137{
1cd986c5 138 if (value > 32 || value < 2)
252b5132 139 {
1cd986c5 140 if (value & 1)
252b5132
RH		 141 * errmsg = _(not_valid);
142 else
143 * errmsg = _(out_of_range);
144 }
1cd986c5 145 else if (value & 1)
252b5132
RH		 146 * errmsg = _(not_aligned);
147
1cd986c5
NC		 148 value = (32 - value)/2;
149
78c8d46c 150 return insn | ((value << (2+16)) & 0x3c0000);
252b5132
RH		 151}
152
153static unsigned long
1cd986c5 154extract_i5div3 (unsigned long insn, int * invalid)
252b5132 155{
1cd986c5
NC		 156 unsigned long ret = (insn & 0x003c0000) >> (16+2);
157 ret = 32 - (ret * 2);
252b5132 158
1cd986c5
NC		 159 if (invalid != 0)
160 *invalid = (ret > 32 || ret < 2) ? 1 : 0;
161 return ret;
252b5132
RH		 162}
163
164static unsigned long
1cd986c5 165insert_d5_4 (unsigned long insn, long value, const char ** errmsg)
252b5132 166{
1cd986c5 167 if (value > 0x1f || value < 0)
252b5132 168 {
1cd986c5 169 if (value & 1)
252b5132
RH		 170 * errmsg = _(not_valid);
171 else
172 * errmsg = _(out_of_range);
173 }
1cd986c5 174 else if (value & 1)
252b5132
RH		 175 * errmsg = _(not_aligned);
176
177 value >>= 1;
178
1cd986c5 179 return insn | (value & 0x0f);
252b5132
RH		 180}
181
182static unsigned long
1cd986c5 183extract_d5_4 (unsigned long insn, int * invalid)
252b5132 184{
1cd986c5
NC		 185 unsigned long ret = (insn & 0x0f);
186
187 ret <<= 1;
252b5132 188
1cd986c5
NC		 189 if (invalid != 0)
190 *invalid = 0;
191 return ret;
252b5132
RH		 192}
193
194static unsigned long
47b0e7ad 195insert_d8_6 (unsigned long insn, long value, const char ** errmsg)
252b5132
RH		 196{
197 if (value > 0xff || value < 0)
198 {
199 if ((value % 4) != 0)
1cd986c5 200 * errmsg = _(not_valid);
252b5132
RH		 201 else
202 * errmsg = _(out_of_range);
203 }
204 else if ((value % 4) != 0)
205 * errmsg = _(not_aligned);
206
207 value >>= 1;
208
47b0e7ad 209 return insn | (value & 0x7e);
252b5132
RH		 210}
211
212static unsigned long
1cd986c5 213extract_d8_6 (unsigned long insn, int * invalid)
252b5132
RH		 214{
215 unsigned long ret = (insn & 0x7e);
216
1cd986c5
NC		 217 ret <<= 1;
218
219 if (invalid != 0)
220 *invalid = 0;
221 return ret;
252b5132
RH		 222}
223
224static unsigned long
1cd986c5 225insert_d8_7 (unsigned long insn, long value, const char ** errmsg)
252b5132 226{
1cd986c5 227 if (value > 0xff || value < 0)
252b5132 228 {
1cd986c5 229 if ((value % 2) != 0)
252b5132
RH		 230 * errmsg = _(not_valid);
231 else
1cd986c5 232 * errmsg = _(out_of_range);
252b5132 233 }
1cd986c5 234 else if ((value % 2) != 0)
252b5132
RH		 235 * errmsg = _(not_aligned);
236
237 value >>= 1;
238
1cd986c5 239 return insn | (value & 0x7f);
252b5132
RH		 240}
241
242static unsigned long
1cd986c5 243extract_d8_7 (unsigned long insn, int * invalid)
252b5132 244{
1cd986c5
NC		 245 unsigned long ret = (insn & 0x7f);
246
247 ret <<= 1;
248
249 if (invalid != 0)
250 *invalid = 0;
251 return ret;
252}
253
254static unsigned long
255insert_v8 (unsigned long insn, long value, const char ** errmsg)
256{
257 if (value > 0xff || value < 0)
258 * errmsg = _(immediate_out_of_range);
259
260 return insn | (value & 0x1f) | ((value & 0xe0) << (27-5));
261}
262
263static unsigned long
264extract_v8 (unsigned long insn, int * invalid)
265{
3f26eb3a 266 unsigned long ret = (insn & 0x1f) | ((insn >> (27-5)) & 0xe0);
1cd986c5
NC		 267
268 if (invalid != 0)
269 *invalid = 0;
270 return ret;
271}
272
273static unsigned long
274insert_d9 (unsigned long insn, long value, const char ** errmsg)
275{
276 if (value > 0xff || value < -0x100)
277 {
278 if ((value % 2) != 0)
279 * errmsg = branch_out_of_range_and_odd_offset;
280 else
281 * errmsg = branch_out_of_range;
282 }
283 else if ((value % 2) != 0)
284 * errmsg = branch_to_odd_offset;
285
286 return insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3);
287}
288
289static unsigned long
290extract_d9 (unsigned long insn, int * invalid)
291{
3f26eb3a 292 signed long ret = ((insn >> 7) & 0x1f0) | ((insn >> 3) & 0x0e);
1cd986c5 293
3f26eb3a 294 ret = (ret ^ 0x100) - 0x100;
1cd986c5
NC		 295
296 if (invalid != 0)
297 *invalid = 0;
298 return ret;
299}
300
301static unsigned long
302insert_u16_loop (unsigned long insn, long value, const char ** errmsg)
303{
41702d50
NC		 304 /* Loop displacement is encoded as a positive value,
305 even though the instruction branches backwards. */
306 if (value < 0 || value > 0xffff)
1cd986c5
NC		 307 {
308 if ((value % 2) != 0)
309 * errmsg = branch_out_of_range_and_odd_offset;
310 else
311 * errmsg = branch_out_of_range;
312 }
313 else if ((value % 2) != 0)
314 * errmsg = branch_to_odd_offset;
315
41702d50 316 return insn | ((value & 0xfffe) << 16);
1cd986c5
NC		 317}
318
319static unsigned long
320extract_u16_loop (unsigned long insn, int * invalid)
321{
322 long ret = (insn >> 16) & 0xfffe;
1cd986c5
NC		 323
324 if (invalid != 0)
325 *invalid = 0;
326 return ret;
327}
328
329static unsigned long
330insert_d16_15 (unsigned long insn, long value, const char ** errmsg)
331{
332 if (value > 0x7fff || value < -0x8000)
333 {
334 if ((value % 2) != 0)
335 * errmsg = _(not_valid);
336 else
337 * errmsg = _(out_of_range);
338 }
339 else if ((value % 2) != 0)
340 * errmsg = _(not_aligned);
341
342 return insn | ((value & 0xfffe) << 16);
343}
344
345static unsigned long
346extract_d16_15 (unsigned long insn, int * invalid)
347{
3f26eb3a
AM		 348 signed long ret = (insn >> 16) & 0xfffe;
349
350 ret = (ret ^ 0x8000) - 0x8000;
252b5132 351
1cd986c5
NC		 352 if (invalid != 0)
353 *invalid = 0;
354 return ret;
252b5132
RH		 355}
356
357static unsigned long
47b0e7ad 358insert_d16_16 (unsigned long insn, signed long value, const char ** errmsg)
252b5132
RH		 359{
360 if (value > 0x7fff || value < -0x8000)
361 * errmsg = _(out_of_range);
362
47b0e7ad 363 return insn | ((value & 0xfffe) << 16) | ((value & 1) << 5);
252b5132
RH		 364}
365
366static unsigned long
1cd986c5 367extract_d16_16 (unsigned long insn, int * invalid)
252b5132 368{
3f26eb3a
AM		 369 signed long ret = ((insn >> 16) & 0xfffe) | ((insn >> 5) & 1);
370
371 ret = (ret ^ 0x8000) - 0x8000;
47b0e7ad 372
1cd986c5
NC		 373 if (invalid != 0)
374 *invalid = 0;
252b5132
RH		 375 return ret;
376}
377
1cd986c5
NC		 378static unsigned long
379insert_d17_16 (unsigned long insn, long value, const char ** errmsg)
380{
381 if (value > 0xffff || value < -0x10000)
382 * errmsg = _(out_of_range);
383
384 return insn | ((value & 0xfffe) << 16) | ((value & 0x10000) >> (16 - 4));
385}
386
387static unsigned long
388extract_d17_16 (unsigned long insn, int * invalid)
389{
3f26eb3a
AM		 390 signed long ret = ((insn >> 16) & 0xfffe) | ((insn << (16 - 4)) & 0x10000);
391
392 ret = (ret ^ 0x10000) - 0x10000;
1cd986c5
NC		 393
394 if (invalid != 0)
395 *invalid = 0;
396 return (unsigned long)ret;
397}
398
399static unsigned long
400insert_d22 (unsigned long insn, long value, const char ** errmsg)
401{
402 if (value > 0x1fffff || value < -0x200000)
403 {
404 if ((value % 2) != 0)
405 * errmsg = branch_out_of_range_and_odd_offset;
406 else
407 * errmsg = branch_out_of_range;
408 }
409 else if ((value % 2) != 0)
410 * errmsg = branch_to_odd_offset;
411
412 return insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16);
413}
414
415static unsigned long
416extract_d22 (unsigned long insn, int * invalid)
417{
3f26eb3a 418 signed long ret = ((insn >> 16) & 0xfffe) | ((insn << 16) & 0x3f0000);
1cd986c5 419
3f26eb3a 420 ret = (ret ^ 0x200000) - 0x200000;
1cd986c5
NC		 421
422 if (invalid != 0)
423 *invalid = 0;
424 return (unsigned long) ret;
425}
426
427static unsigned long
428insert_d23 (unsigned long insn, long value, const char ** errmsg)
429{
430 if (value > 0x3fffff || value < -0x400000)
3f26eb3a 431 * errmsg = out_of_range;
1cd986c5
NC		 432
433 return insn | ((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7));
434}
435
78c8d46c
NC		 436static unsigned long
437insert_d23_align1 (unsigned long insn, long value, const char ** errmsg)
438{
439 if (value > 0x3fffff || value < -0x400000)
440 {
441 if (value & 0x1)
442 * errmsg = _(not_valid);
443 else
444 * errmsg = _(out_of_range);
445 }
446 else if (value & 0x1)
447 * errmsg = _(not_aligned);
448
449 return insn | ((value & 0x7e) << 4) | ((value & 0x7fff80) << (16 - 7));
450}
451
1cd986c5
NC		 452static unsigned long
453extract_d23 (unsigned long insn, int * invalid)
454{
3f26eb3a 455 signed long ret = ((insn >> 4) & 0x7f) | ((insn >> (16-7)) & 0x7fff80);
1cd986c5 456
3f26eb3a 457 ret = (ret ^ 0x400000) - 0x400000;
1cd986c5
NC		 458
459 if (invalid != 0)
460 *invalid = 0;
461 return (unsigned long) ret;
462}
463
252b5132 464static unsigned long
47b0e7ad 465insert_i9 (unsigned long insn, signed long value, const char ** errmsg)
252b5132
RH		 466{
467 if (value > 0xff || value < -0x100)
468 * errmsg = _(immediate_out_of_range);
469
470 return insn | ((value & 0x1e0) << 13) | (value & 0x1f);
471}
472
473static unsigned long
1cd986c5 474extract_i9 (unsigned long insn, int * invalid)
252b5132 475{
3f26eb3a 476 signed long ret = ((insn >> 13) & 0x1e0) | (insn & 0x1f);
252b5132 477
3f26eb3a 478 ret = (ret ^ 0x100) - 0x100;
47b0e7ad 479
1cd986c5
NC		 480 if (invalid != 0)
481 *invalid = 0;
252b5132
RH		 482 return ret;
483}
484
485static unsigned long
47b0e7ad 486insert_u9 (unsigned long insn, long v, const char ** errmsg)
252b5132 487{
fc05c67f 488 unsigned long value = (unsigned long) v;
47b0e7ad 489
252b5132
RH		 490 if (value > 0x1ff)
491 * errmsg = _(immediate_out_of_range);
492
493 return insn | ((value & 0x1e0) << 13) | (value & 0x1f);
494}
495
496static unsigned long
1cd986c5 497extract_u9 (unsigned long insn, int * invalid)
252b5132 498{
3f26eb3a 499 unsigned long ret = ((insn >> 13) & 0x1e0) | (insn & 0x1f);
47b0e7ad 500
1cd986c5
NC		 501 if (invalid != 0)
502 *invalid = 0;
252b5132
RH		 503 return ret;
504}
505
506static unsigned long
47b0e7ad 507insert_spe (unsigned long insn, long v, const char ** errmsg)
252b5132 508{
fc05c67f
NC		 509 unsigned long value = (unsigned long) v;
510
252b5132
RH		 511 if (value != 3)
512 * errmsg = _("invalid register for stack adjustment");
513
3f26eb3a 514 return insn & ~0x180000;
252b5132
RH		 515}
516
517static unsigned long
1cd986c5 518extract_spe (unsigned long insn ATTRIBUTE_UNUSED, int * invalid)
252b5132 519{
1cd986c5
NC		 520 if (invalid != 0)
521 *invalid = 0;
522
252b5132
RH		 523 return 3;
524}
525
526static unsigned long
1cd986c5 527insert_r4 (unsigned long insn, long v, const char ** errmsg)
252b5132 528{
fc05c67f
NC		 529 unsigned long value = (unsigned long) v;
530
1cd986c5 531 if (value >= 32)
78c8d46c 532 * errmsg = _("invalid register name");
47b0e7ad 533
78c8d46c 534 return insn | ((value & 0x01) << 23) | ((value & 0x1e) << 16);
252b5132
RH		 535}
536
537static unsigned long
1cd986c5 538extract_r4 (unsigned long insn, int * invalid)
252b5132 539{
78c8d46c
NC		 540 unsigned long r4;
541 unsigned long insn2;
542
543 insn2 = insn >> 16;
544 r4 = (((insn2 & 0x0080) >> 7) | (insn2 & 0x001e));
545
546 if (invalid != 0)
547 *invalid = 0;
548
549 return r4;
550}
551
552static unsigned long G_pos;
553
554static unsigned long
555insert_POS (unsigned long insn, long pos, const char ** errmsg)
556{
557 if (pos > 0x1f || pos < 0)
558 * errmsg = _(pos_out_of_range);
559
560 G_pos = (unsigned long) pos;
561
562 return insn; /* Not an oparaton until WIDTH. */
563}
564
565static unsigned long
566extract_POS_U (unsigned long insn, int * invalid)
567{
568 unsigned long pos,lsb;
569 unsigned long insn2;
570 insn2 = insn >> 16;
571
572 lsb = ((insn2 & 0x0800) >> 8)
573 | ((insn2 & 0x000e) >> 1);
574 lsb += 16;
575 pos = lsb;
576
577 if (invalid != 0)
578 *invalid = 0;
579
580 return pos;
581}
582
583static unsigned long
584extract_POS_L (unsigned long insn, int * invalid)
585{
586 unsigned long pos,lsb;
587 unsigned long insn2;
588 insn2 = insn >> 16;
589
590 lsb = ((insn2 & 0x0800) >> 8)
591 | ((insn2 & 0x000e) >> 1);
592 pos = lsb;
593
594 if (invalid != 0)
595 *invalid = 0;
596
597 return pos;
598}
599
600static unsigned long
601insert_WIDTH (unsigned long insn, long width, const char ** errmsg)
602{
603 unsigned long msb, lsb, opc, ret;
604 unsigned long msb_expand, lsb_expand;
605
606 msb = (unsigned long)width + G_pos - 1;
607 lsb = G_pos;
608 opc = 0;
609 G_pos = 0;
610
611 if (width > 0x20 || width < 0)
612 * errmsg = _(width_out_of_range);
613
614 if ((msb >= 16) && (lsb >= 16))
615 opc = 0x0090;
616 else if ((msb >= 16) && (lsb < 16))
617 opc = 0x00b0;
618 else if ((msb < 16) && (lsb < 16))
619 opc = 0x00d0;
620 else
621 * errmsg = _(width_out_of_range);
622
623 msb &= 0x0f;
624 msb_expand = msb << 12;
625 lsb &= 0x0f;
626 lsb_expand = ((lsb & 0x8) << 8)|((lsb & 0x7) << 1);
627
628 ret = (insn & 0x0000ffff) | ((opc | msb_expand | lsb_expand) << 16);
629
630 return ret;
631}
632
633static unsigned long
634extract_WIDTH_U (unsigned long insn, int * invalid)
635{
636 unsigned long width, msb, lsb;
637 unsigned long insn2;
638 insn2 = insn >> 16;
639
640 msb = ((insn2 & 0xf000) >> 12);
641 msb += 16;
642 lsb = ((insn2 & 0x0800) >> 8)
643 | ((insn2 & 0x000e) >> 1);
644 lsb += 16;
645
646 if (invalid != 0)
647 *invalid = 0;
648
649 width = msb - lsb + 1;
650
651 return width;
652}
653
654static unsigned long
655extract_WIDTH_M (unsigned long insn, int * invalid)
656{
657 unsigned long width, msb, lsb;
658 unsigned long insn2;
659 insn2 = insn >> 16;
660
661 msb = ((insn2 & 0xf000) >> 12) ;
662 msb += 16;
663 lsb = ((insn2 & 0x0800) >> 8)
664 | ((insn2 & 0x000e) >> 1);
665
666 if (invalid != 0)
667 *invalid = 0;
668
669 width = msb - lsb + 1;
670
671 return width;
672}
673
674static unsigned long
675extract_WIDTH_L (unsigned long insn, int * invalid)
676{
677 unsigned long width, msb, lsb;
678 unsigned long insn2;
679 insn2 = insn >> 16;
680
681 msb = ((insn2 & 0xf000) >> 12) ;
682 lsb = ((insn2 & 0x0800) >> 8)
683 | ((insn2 & 0x000e) >> 1);
684
685 if (invalid != 0)
686 *invalid = 0;
687
688 width = msb - lsb + 1;
689
690 return width;
691}
692
693static unsigned long
694insert_SELID (unsigned long insn, long selid, const char ** errmsg)
695{
696 unsigned long ret;
697
698 if (selid > 0x1f || selid < 0)
699 * errmsg = _(selid_out_of_range);
700
701 ret = (insn | ((selid & 0x1f) << 27));
702
703 return ret;
704}
705
706static unsigned long
707extract_SELID (unsigned long insn, int * invalid)
708{
709 unsigned long selid;
710 unsigned long insn2;
711
712 insn2 = insn >> 16;
713
714 selid = ((insn2 & 0xf800) >> 11);
715
716 if (invalid != 0)
717 *invalid = 0;
718
719 return selid;
720}
721
722static unsigned long
723insert_VECTOR8 (unsigned long insn, long vector8, const char ** errmsg)
724{
725 unsigned long ret;
726 unsigned long VVV,vvvvv;
727
728 if (vector8 > 0xff || vector8 < 0)
729 * errmsg = _(vector8_out_of_range);
730
731 VVV = (vector8 & 0xe0) >> 5;
732 vvvvv = (vector8 & 0x1f);
733
734 ret = (insn | (VVV << 27) | vvvvv);
735
736 return ret;
737}
738
739static unsigned long
740extract_VECTOR8 (unsigned long insn, int * invalid)
741{
742 unsigned long vector8;
743 unsigned long VVV,vvvvv;
744 unsigned long insn2;
745
746 insn2 = insn >> 16;
747 VVV = ((insn2 & 0x3800) >> 11);
748 vvvvv = (insn & 0x001f);
749 vector8 = VVV << 5 | vvvvv;
750
751 if (invalid != 0)
752 *invalid = 0;
753
754 return vector8;
755}
756
757static unsigned long
758insert_VECTOR5 (unsigned long insn, long vector5, const char ** errmsg)
759{
760 unsigned long ret;
761 unsigned long vvvvv;
762
763 if (vector5 > 0x1f || vector5 < 0)
764 * errmsg = _(vector5_out_of_range);
765
766 vvvvv = (vector5 & 0x1f);
767
768 ret = (insn | vvvvv);
769
770 return ret;
771}
772
773static unsigned long
774extract_VECTOR5 (unsigned long insn, int * invalid)
775{
776 unsigned long vector5;
777
778 vector5 = (insn & 0x001f);
779
780 if (invalid != 0)
781 *invalid = 0;
782
783 return vector5;
784}
785
786static unsigned long
787insert_CACHEOP (unsigned long insn, long cacheop, const char ** errmsg ATTRIBUTE_UNUSED)
788{
789 unsigned long ret;
790 unsigned long pp,PPPPP;
791
792 pp = (cacheop & 0x60) >> 5;
793 PPPPP = (cacheop & 0x1f);
794
795 ret = insn | (pp << 11) | (PPPPP << 27);
796
797 return ret;
798}
799
800static unsigned long
801extract_CACHEOP (unsigned long insn, int * invalid)
802{
803 unsigned long ret;
804 unsigned long pp,PPPPP;
805 unsigned long insn2;
806
807 insn2 = insn >> 16;
808
809 PPPPP = ((insn2 & 0xf800) >> 11);
810 pp = ((insn & 0x1800) >> 11);
811
812 ret = (pp << 5) | PPPPP;
813
814 if (invalid != 0)
815 *invalid = 0;
816
817 return ret;
818}
819
820static unsigned long
821insert_PREFOP (unsigned long insn, long prefop, const char ** errmsg ATTRIBUTE_UNUSED)
822{
823 unsigned long ret;
824 unsigned long PPPPP;
825
826 PPPPP = (prefop & 0x1f);
827
828 ret = insn | (PPPPP << 27);
829
830 return ret;
831}
832
833static unsigned long
834extract_PREFOP (unsigned long insn, int * invalid)
835{
836 unsigned long ret;
837 unsigned long PPPPP;
838 unsigned long insn2;
839
840 insn2 = insn >> 16;
841
842 PPPPP = (insn2 & 0xf800) >> 11;
843
844 ret = PPPPP;
845
846 if (invalid != 0)
847 *invalid = 0;
848
849 return ret;
850}
851
852static unsigned long
853insert_IMM10U (unsigned long insn, long value, const char ** errmsg)
854{
855 unsigned long imm10, ret;
856 unsigned long iiiii,IIIII;
857
858 if (value > 0x3ff || value < 0)
859 * errmsg = _(imm10_out_of_range);
860
861 imm10 = ((unsigned long) value) & 0x3ff;
862 IIIII = (imm10 >> 5) & 0x1f;
863 iiiii = imm10 & 0x1f;
864
865 ret = insn | IIIII << 27 | iiiii;
866
867 return ret;
868}
869
870static unsigned long
871extract_IMM10U (unsigned long insn, int * invalid)
872{
873 unsigned long ret;
874 unsigned long iiiii,IIIII;
875 unsigned long insn2;
876 insn2 = insn >> 16;
877
878 IIIII = ((insn2 & 0xf800) >> 11);
879 iiiii = (insn & 0x001f);
880
881 ret = (IIIII << 5) | iiiii;
882
883 if (invalid != 0)
884 *invalid = 0;
885
886 return ret;
887}
888
889static unsigned long
890insert_SRSEL1 (unsigned long insn, long value, const char ** errmsg)
891{
892 unsigned long imm10, ret;
893 unsigned long sr,selid;
894
895 if (value > 0x3ff || value < 0)
896 * errmsg = _(sr_selid_out_of_range);
897
898 imm10 = (unsigned long) value;
899 selid = (imm10 & 0x3e0) >> 5;
900 sr = imm10 & 0x1f;
901
902 ret = insn | selid << 27 | sr;
903
904 return ret;
905}
906
907static unsigned long
908extract_SRSEL1 (unsigned long insn, int * invalid)
909{
910 unsigned long ret;
911 unsigned long sr, selid;
912 unsigned long insn2;
913
914 insn2 = insn >> 16;
915
916 selid = ((insn2 & 0xf800) >> 11);
917 sr = (insn & 0x001f);
918
919 ret = (selid << 5) | sr;
920
921 if (invalid != 0)
922 *invalid = 0;
923
924 return ret;
925}
926
927static unsigned long
928insert_SRSEL2 (unsigned long insn, long value, const char ** errmsg)
929{
930 unsigned long imm10, ret;
931 unsigned long sr, selid;
932
933 if (value > 0x3ff || value < 0)
934 * errmsg = _(sr_selid_out_of_range);
935
936 imm10 = (unsigned long) value;
937 selid = (imm10 & 0x3e0) >> 5;
938 sr = imm10 & 0x1f;
939
940 ret = insn | selid << 27 | sr << 11;
941
942 return ret;
943}
944
945static unsigned long
946extract_SRSEL2 (unsigned long insn, int * invalid)
947{
948 unsigned long ret;
949 unsigned long sr, selid;
950 unsigned long insn2;
951
952 insn2 = insn >> 16;
953
954 selid = ((insn2 & 0xf800) >> 11);
955 sr = ((insn & 0xf800) >> 11);
956
957 ret = (selid << 5) | sr;
47b0e7ad 958
1cd986c5
NC		 959 if (invalid != 0)
960 *invalid = 0;
78c8d46c 961
252b5132
RH		 962 return ret;
963}
252b5132
RH		 964\f
965/* Warning: code in gas/config/tc-v850.c examines the contents of this array.
966 If you change any of the values here, be sure to look for side effects in
fc05c67f 967 that code. */
252b5132
RH		 968const struct v850_operand v850_operands[] =
969{
970#define UNUSED 0
1cd986c5 971 { 0, 0, NULL, NULL, 0, BFD_RELOC_NONE },
252b5132 972
1cd986c5 973/* The R1 field in a format 1, 6, 7, 9, C insn. */
252b5132 974#define R1 (UNUSED + 1)
1cd986c5 975 { 5, 0, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE },
252b5132
RH		 976
977/* As above, but register 0 is not allowed. */
978#define R1_NOTR0 (R1 + 1)
1cd986c5
NC		 979 { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
980
981/* Even register is allowed. */
982#define R1_EVEN (R1_NOTR0 + 1)
983 { 4, 1, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
984
985/* Bang (bit reverse). */
986#define R1_BANG (R1_EVEN + 1)
987 { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_BANG, BFD_RELOC_NONE },
988
989/* Percent (modulo). */
990#define R1_PERCENT (R1_BANG + 1)
991 { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_PERCENT, BFD_RELOC_NONE },
252b5132 992
1cd986c5
NC		 993/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9, C insn. */
994#define R2 (R1_PERCENT + 1)
995 { 5, 11, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE },
252b5132
RH		 996
997/* As above, but register 0 is not allowed. */
998#define R2_NOTR0 (R2 + 1)
1cd986c5 999 { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
252b5132 1000
1cd986c5
NC		 1001/* Even register is allowed. */
1002#define R2_EVEN (R2_NOTR0 + 1)
1003 { 4, 12, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
252b5132 1004
1cd986c5
NC		 1005/* Reg2 in dispose instruction. */
1006#define R2_DISPOSE (R2_EVEN + 1)
1007 { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
252b5132 1008
1cd986c5
NC		 1009/* The R3 field in a format 11, 12, C insn. */
1010#define R3 (R2_DISPOSE + 1)
1011 { 5, 27, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE },
252b5132 1012
1cd986c5
NC		 1013/* As above, but register 0 is not allowed. */
1014#define R3_NOTR0 (R3 + 1)
1015 { 5, 27, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
252b5132 1016
1cd986c5
NC		 1017/* As above, but odd number registers are not allowed. */
1018#define R3_EVEN (R3_NOTR0 + 1)
1019 { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
252b5132 1020
1cd986c5
NC		 1021/* As above, but register 0 is not allowed. */
1022#define R3_EVEN_NOTR0 (R3_EVEN + 1)
1023 { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN | V850_NOT_R0, BFD_RELOC_NONE },
252b5132 1024
1cd986c5
NC		 1025/* Forth register in FPU Instruction. */
1026#define R4 (R3_EVEN_NOTR0 + 1)
1027 { 5, 0, insert_r4, extract_r4, V850_OPERAND_REG, BFD_RELOC_NONE },
252b5132 1028
1cd986c5
NC		 1029/* As above, but odd number registers are not allowed. */
1030#define R4_EVEN (R4 + 1)
1031 { 4, 17, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
252b5132 1032
1cd986c5
NC		 1033/* Stack pointer in prepare instruction. */
1034#define SP (R4_EVEN + 1)
1035 { 2, 0, insert_spe, extract_spe, V850_OPERAND_REG, BFD_RELOC_NONE },
252b5132
RH		 1036
1037/* EP Register. */
1cd986c5
NC		 1038#define EP (SP + 1)
1039 { 0, 0, NULL, NULL, V850_OPERAND_EP, BFD_RELOC_NONE },
1040
1041/* A list of registers in a prepare/dispose instruction. */
1042#define LIST12 (EP + 1)
1043 { -1, 0xffe00001, NULL, NULL, V850E_OPERAND_REG_LIST, BFD_RELOC_NONE },
252b5132 1044
1cd986c5 1045/* System register operands. */
78c8d46c 1046#define OLDSR1 (LIST12 + 1)
1cd986c5 1047 { 5, 0, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE },
252b5132 1048
78c8d46c
NC		 1049#define SR1 (OLDSR1 + 1)
1050 { 0, 0, insert_SRSEL1, extract_SRSEL1, V850_OPERAND_SRG, BFD_RELOC_NONE },
1051
252b5132 1052/* The R2 field as a system register. */
78c8d46c 1053#define OLDSR2 (SR1 + 1)
1cd986c5 1054 { 5, 11, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE },
252b5132 1055
78c8d46c
NC		 1056#define SR2 (OLDSR2 + 1)
1057 { 0, 0, insert_SRSEL2, extract_SRSEL2, V850_OPERAND_SRG, BFD_RELOC_NONE },
1058
1cd986c5
NC		 1059/* FPU CC bit position. */
1060#define FFF (SR2 + 1)
1061 { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE },
252b5132 1062
1cd986c5
NC		 1063/* The 4 bit condition code in a setf instruction. */
1064#define CCCC (FFF + 1)
1065 { 4, 0, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE },
252b5132 1066
1cd986c5
NC		 1067/* Condition code in adf,sdf. */
1068#define CCCC_NOTSA (CCCC + 1)
1069 { 4, 17, NULL, NULL, V850_OPERAND_CC|V850_NOT_SA, BFD_RELOC_NONE },
252b5132 1070
1cd986c5
NC		 1071/* Condition code in conditional moves. */
1072#define MOVCC (CCCC_NOTSA + 1)
1073 { 4, 17, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE },
252b5132 1074
1cd986c5
NC		 1075/* Condition code in FPU. */
1076#define FLOAT_CCCC (MOVCC + 1)
1077 { 4, 27, NULL, NULL, V850_OPERAND_FLOAT_CC, BFD_RELOC_NONE },
252b5132 1078
1cd986c5
NC		 1079/* The 1 bit immediate field in format C insn. */
1080#define VI1 (FLOAT_CCCC + 1)
1081 { 1, 3, NULL, NULL, 0, BFD_RELOC_NONE },
252b5132 1082
1cd986c5
NC		 1083/* The 1 bit immediate field in format C insn. */
1084#define VC1 (VI1 + 1)
1085 { 1, 0, NULL, NULL, 0, BFD_RELOC_NONE },
252b5132 1086
1cd986c5
NC		 1087/* The 2 bit immediate field in format C insn. */
1088#define DI2 (VC1 + 1)
1089 { 2, 17, NULL, NULL, 0, BFD_RELOC_NONE },
252b5132 1090
1cd986c5
NC		 1091/* The 2 bit immediate field in format C insn. */
1092#define VI2 (DI2 + 1)
1093 { 2, 0, NULL, NULL, 0, BFD_RELOC_NONE },
252b5132 1094
1cd986c5
NC		 1095/* The 2 bit immediate field in format C - DUP insn. */
1096#define VI2DUP (VI2 + 1)
1097 { 2, 2, NULL, NULL, 0, BFD_RELOC_NONE },
252b5132 1098
1cd986c5
NC		 1099/* The 3 bit immediate field in format 8 insn. */
1100#define B3 (VI2DUP + 1)
1101 { 3, 11, NULL, NULL, 0, BFD_RELOC_NONE },
252b5132 1102
1cd986c5
NC		 1103/* The 3 bit immediate field in format C insn. */
1104#define DI3 (B3 + 1)
1105 { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE },
252b5132 1106
1cd986c5
NC		 1107/* The 3 bit immediate field in format C insn. */
1108#define I3U (DI3 + 1)
1109 { 3, 0, NULL, NULL, 0, BFD_RELOC_NONE },
252b5132 1110
1cd986c5
NC		 1111/* The 4 bit immediate field in format C insn. */
1112#define I4U (I3U + 1)
1113 { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE },
252b5132 1114
1cd986c5
NC		 1115/* The 4 bit immediate field in fetrap. */
1116#define I4U_NOTIMM0 (I4U + 1)
1117 { 4, 11, NULL, NULL, V850_NOT_IMM0, BFD_RELOC_NONE },
252b5132 1118
1cd986c5
NC		 1119/* The unsigned disp4 field in a sld.bu. */
1120#define D4U (I4U_NOTIMM0 + 1)
1121 { 4, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_4_OFFSET },
252b5132 1122
1cd986c5
NC		 1123/* The imm5 field in a format 2 insn. */
1124#define I5 (D4U + 1)
1125 { 5, 0, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_NONE },
252b5132 1126
1cd986c5
NC		 1127/* The imm5 field in a format 11 insn. */
1128#define I5DIV1 (I5 + 1)
1129 { 5, 0, insert_i5div1, extract_i5div1, 0, BFD_RELOC_NONE },
252b5132 1130
1cd986c5
NC		 1131#define I5DIV2 (I5DIV1 + 1)
1132 { 5, 0, insert_i5div2, extract_i5div2, 0, BFD_RELOC_NONE },
252b5132 1133
1cd986c5
NC		 1134#define I5DIV3 (I5DIV2 + 1)
1135 { 5, 0, insert_i5div3, extract_i5div3, 0, BFD_RELOC_NONE },
252b5132 1136
1cd986c5
NC		 1137/* The unsigned imm5 field in a format 2 insn. */
1138#define I5U (I5DIV3 + 1)
1139 { 5, 0, NULL, NULL, 0, BFD_RELOC_NONE },
252b5132 1140
1cd986c5
NC		 1141/* The imm5 field in a prepare/dispose instruction. */
1142#define IMM5 (I5U + 1)
1143 { 5, 1, NULL, NULL, 0, BFD_RELOC_NONE },
252b5132 1144
1cd986c5
NC		 1145/* The unsigned disp5 field in a sld.hu. */
1146#define D5_4U (IMM5 + 1)
1147 { 5, 0, insert_d5_4, extract_d5_4, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_5_OFFSET },
1148
1149/* The IMM6 field in a callt instruction. */
1150#define IMM6 (D5_4U + 1)
1151 { 6, 0, NULL, NULL, 0, BFD_RELOC_V850_CALLT_6_7_OFFSET },
1152
1153/* The signed disp7 field in a format 4 insn. */
1154#define D7U (IMM6 + 1)
1155 { 7, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_7_OFFSET },
1156
1157/* The unsigned DISP8 field in a format 4 insn. */
1158#define D8_7U (D7U + 1)
1159 { 8, 0, insert_d8_7, extract_d8_7, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_8_OFFSET },
1160
1161/* The unsigned DISP8 field in a format 4 insn. */
1162#define D8_6U (D8_7U + 1)
1163 { 8, 0, insert_d8_6, extract_d8_6, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_6_8_OFFSET },
1164
1165/* The unsigned DISP8 field in a format 4 insn. */
1166#define V8 (D8_6U + 1)
1167 { 8, 0, insert_v8, extract_v8, 0, BFD_RELOC_NONE },
1168
1169/* The imm9 field in a multiply word. */
1170#define I9 (V8 + 1)
1171 { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED, BFD_RELOC_NONE },
1172
1173/* The unsigned imm9 field in a multiply word. */
1174#define U9 (I9 + 1)
1175 { 9, 0, insert_u9, extract_u9, 0, BFD_RELOC_NONE },
1176
1177/* The DISP9 field in a format 3 insn. */
1178#define D9 (U9 + 1)
1179 { 9, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL },
1180
1181/* The DISP9 field in a format 3 insn, relaxable. */
1182#define D9_RELAX (D9 + 1)
1183 { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL },
1184
1185/* The imm16 field in a format 6 insn. */
1186#define I16 (D9_RELAX + 1)
1187 { 16, 16, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_16 },
1188
dd42f060 1189/* The signed 16 bit immediate following a prepare instruction. */
78c8d46c 1190#define IMM16LO (I16 + 1)
dd42f060 1191 { 16, 32, NULL, NULL, V850E_IMMEDIATE16 | V850_OPERAND_SIGNED, BFD_RELOC_LO16 },
1cd986c5
NC		 1192
1193/* The hi 16 bit immediate following a 32 bit instruction. */
1194#define IMM16HI (IMM16LO + 1)
1195 { 16, 16, NULL, NULL, V850E_IMMEDIATE16HI, BFD_RELOC_HI16 },
1196
1197/* The unsigned imm16 in a format 6 insn. */
1198#define I16U (IMM16HI + 1)
1199 { 16, 16, NULL, NULL, 0, BFD_RELOC_16 },
1200
1201/* The disp16 field in a format 8 insn. */
1202#define D16 (I16U + 1)
1203 { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_16 },
1204
1205/* The disp16 field in an format 7 unsigned byte load insn. */
1206#define D16_16 (D16 + 1)
1207 { 16, 0, insert_d16_16, extract_d16_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_16_SPLIT_OFFSET },
1208
1209/* The disp16 field in a format 6 insn. */
1210#define D16_15 (D16_16 + 1)
1211 { 16, 0, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED | V850_OPERAND_DISP , BFD_RELOC_V850_16_S1 },
1212
1213/* The unsigned DISP16 field in a format 7 insn. */
1214#define D16_LOOP (D16_15 + 1)
41702d50 1215 { 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_RELAX | V850_OPERAND_DISP | V850_PCREL | V850_INVERSE_PCREL, BFD_RELOC_V850_16_PCREL },
1cd986c5
NC		 1216
1217/* The DISP17 field in a format 7 insn. */
1218#define D17_16 (D16_LOOP + 1)
1219 { 17, 0, insert_d17_16, extract_d17_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_17_PCREL },
1220
1221/* The DISP22 field in a format 4 insn, relaxable.
1222 This _must_ follow D9_RELAX; the assembler assumes that the longer
1223 version immediately follows the shorter version for relaxing. */
1224#define D22 (D17_16 + 1)
1225 { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_22_PCREL },
1226
1227#define D23 (D22 + 1)
1228 { 23, 0, insert_d23, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 },
1229
78c8d46c
NC		 1230#define D23_ALIGN1 (D23 + 1)
1231 { 23, 0, insert_d23_align1, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 },
1232
1cd986c5 1233/* The 32 bit immediate following a 32 bit instruction. */
78c8d46c 1234#define IMM32 (D23_ALIGN1 + 1)
1cd986c5
NC		 1235 { 32, 32, NULL, NULL, V850E_IMMEDIATE32, BFD_RELOC_32 },
1236
1237#define D32_31 (IMM32 + 1)
1238 { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_32_ABS },
1239
1240#define D32_31_PCREL (D32_31 + 1)
1241 { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_32_PCREL },
1242
78c8d46c
NC		 1243#define POS_U (D32_31_PCREL + 1)
1244 { 0, 0, insert_POS, extract_POS_U, 0, BFD_RELOC_NONE },
1245
1246#define POS_M (POS_U + 1)
1247 { 0, 0, insert_POS, extract_POS_L, 0, BFD_RELOC_NONE },
1248
1249#define POS_L (POS_M + 1)
1250 { 0, 0, insert_POS, extract_POS_L, 0, BFD_RELOC_NONE },
1251
1252#define WIDTH_U (POS_L + 1)
1253 { 0, 0, insert_WIDTH, extract_WIDTH_U, 0, BFD_RELOC_NONE },
1254
1255#define WIDTH_M (WIDTH_U + 1)
1256 { 0, 0, insert_WIDTH, extract_WIDTH_M, 0, BFD_RELOC_NONE },
1257
1258#define WIDTH_L (WIDTH_M + 1)
1259 { 0, 0, insert_WIDTH, extract_WIDTH_L, 0, BFD_RELOC_NONE },
1260
1261#define SELID (WIDTH_L + 1)
1262 { 5, 27, insert_SELID, extract_SELID, 0, BFD_RELOC_NONE },
1263
1264#define RIE_IMM5 (SELID + 1)
1265 { 5, 11, NULL, NULL, 0, BFD_RELOC_NONE },
1266
1267#define RIE_IMM4 (RIE_IMM5 + 1)
1268 { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE },
1269
1270#define VECTOR8 (RIE_IMM4 + 1)
1271 { 0, 0, insert_VECTOR8, extract_VECTOR8, 0, BFD_RELOC_NONE },
1272
1273#define VECTOR5 (VECTOR8 + 1)
1274 { 0, 0, insert_VECTOR5, extract_VECTOR5, 0, BFD_RELOC_NONE },
1275
1276#define VR1 (VECTOR5 + 1)
1277 { 5, 0, NULL, NULL, V850_OPERAND_VREG, BFD_RELOC_NONE },
1278
1279#define VR2 (VR1 + 1)
1280 { 5, 11, NULL, NULL, V850_OPERAND_VREG, BFD_RELOC_NONE },
1281
1282#define CACHEOP (VR2 + 1)
1283 { 0, 0, insert_CACHEOP, extract_CACHEOP, V850_OPERAND_CACHEOP, BFD_RELOC_NONE },
1284
1285#define PREFOP (CACHEOP + 1)
1286 { 0, 0, insert_PREFOP, extract_PREFOP, V850_OPERAND_PREFOP, BFD_RELOC_NONE },
1287
1288#define IMM10U (PREFOP + 1)
1289 { 0, 0, insert_IMM10U, extract_IMM10U, 0, BFD_RELOC_NONE },
1cd986c5
NC		 1290};
1291
1292\f
1293/* Reg - Reg instruction format (Format I). */
1294#define IF1 {R1, R2}
1295
1296/* Imm - Reg instruction format (Format II). */
1297#define IF2 {I5, R2}
1298
1299/* Conditional branch instruction format (Format III). */
1300#define IF3 {D9_RELAX}
252b5132 1301
8ad30312 1302/* 3 operand instruction (Format VI). */
252b5132
RH		 1303#define IF6 {I16, R1, R2}
1304
8ad30312 1305/* 3 operand instruction (Format VI). */
252b5132
RH		 1306#define IF6U {I16U, R1, R2}
1307
1cd986c5
NC		 1308/* Conditional branch instruction format (Format VII). */
1309#define IF7 {D17_16}
252b5132
RH		 1310
1311\f
1312/* The opcode table.
1313
1314 The format of the opcode table is:
1315
1316 NAME OPCODE MASK { OPERANDS } MEMOP PROCESSOR
1317
1318 NAME is the name of the instruction.
1319 OPCODE is the instruction opcode.
1320 MASK is the opcode mask; this is used to tell the disassembler
1321 which bits in the actual opcode must match OPCODE.
1322 OPERANDS is the list of operands.
1323 MEMOP specifies which operand (if any) is a memory operand.
1324 PROCESSORS specifies which CPU(s) support the opcode.
47b0e7ad 1325
252b5132
RH		 1326 The disassembler reads the table in order and prints the first
1327 instruction which matches, so this table is sorted to put more
1328 specific instructions before more general instructions. It is also
1329 sorted by major opcode.
1330
1331 The table is also sorted by name. This is used by the assembler.
1332 When parsing an instruction the assembler finds the first occurance
1333 of the name of the instruciton in this table and then attempts to
1334 match the instruction's arguments with description of the operands
1335 associated with the entry it has just found in this table. If the
1336 match fails the assembler looks at the next entry in this table.
1337 If that entry has the same name as the previous entry, then it
1338 tries to match the instruction against that entry and so on. This
1339 is how the assembler copes with multiple, different formats of the
1340 same instruction. */
1341
1342const struct v850_opcode v850_opcodes[] =
1343{
1cd986c5 1344/* Standard instructions. */
252b5132
RH		 1345{ "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL },
1346{ "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL },
1cd986c5 1347
252b5132 1348{ "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL },
47b0e7ad 1349
78c8d46c 1350{ "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
252b5132 1351
252b5132 1352{ "and", OP (0x0a), OP_MASK, IF1, 0, PROCESSOR_ALL },
1cd986c5 1353
252b5132 1354{ "andi", OP (0x36), OP_MASK, IF6U, 0, PROCESSOR_ALL },
252b5132 1355
8ad30312 1356 /* Signed integer. */
252b5132 1357{ "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1cd986c5 1358{ "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL },
252b5132 1359{ "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1cd986c5 1360{ "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL },
8ad30312 1361 /* Unsigned integer. */
252b5132 1362{ "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL },
252b5132 1363{ "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1cd986c5 1364{ "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL },
252b5132 1365{ "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
8ad30312 1366 /* Common. */
252b5132
RH		 1367{ "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1368{ "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
8ad30312 1369 /* Others. */
252b5132 1370{ "bc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1cd986c5
NC		 1371{ "bf", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1372{ "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL },
252b5132 1373{ "bnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1cd986c5 1374{ "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL },
252b5132 1375{ "bnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1cd986c5 1376{ "bp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL },
252b5132
RH		 1377{ "br", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1378{ "bsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1cd986c5
NC		 1379{ "bt", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1380{ "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1381{ "bz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
252b5132 1382
78c8d46c
NC		 1383/* Signed integer. */
1384{ "bge", two (0x07ee, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1385{ "bgt", two (0x07ef, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1386{ "ble", two (0x07e7, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1387{ "blt", two (0x07e6, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
43e65147 1388/* Unsigned integer. */
78c8d46c
NC		 1389{ "bh", two (0x07eb, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1390{ "bl", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1391{ "bnh", two (0x07e3, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1392{ "bnl", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
43e65147 1393/* Common. */
78c8d46c
NC		 1394{ "be", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1395{ "bne", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
43e65147 1396/* Others. */
78c8d46c
NC		 1397{ "bc", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1398{ "bf", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1399{ "bn", two (0x07e4, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1400{ "bnc", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1401{ "bnv", two (0x07e8, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1402{ "bnz", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1403{ "bp", two (0x07ec, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1404{ "br", two (0x07e5, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1405{ "bsa", two (0x07ed, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1406{ "bt", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1407{ "bv", two (0x07e0, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1408{ "bz", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP },
1409/* Bcond disp17 Gas local alias(not defined in spec). */
1410
1411/* Signed integer. */
1412{ "bge17", two (0x07ee, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1413{ "bgt17", two (0x07ef, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1414{ "ble17", two (0x07e7, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1415{ "blt17", two (0x07e6, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1416/* Unsigned integer. */
1417{ "bh17", two (0x07eb, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1418{ "bl17", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1419{ "bnh17", two (0x07e3, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1420{ "bnl17", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1421/* Common. */
1422{ "be17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1423{ "bne17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1424/* Others. */
1425{ "bc17", two (0x07e1, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1426{ "bf17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1427{ "bn17", two (0x07e4, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1428{ "bnc17", two (0x07e9, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1429{ "bnv17", two (0x07e8, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1430{ "bnz17", two (0x07ea, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1431{ "bp17", two (0x07ec, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1432{ "br17", two (0x07e5, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1433{ "bsa17", two (0x07ed, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1434{ "bt17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1435{ "bv17", two (0x07e0, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1436{ "bz17", two (0x07e2, 0x0001), two (0xffef, 0x0001), IF7, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1437
1cd986c5 1438{ "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
252b5132 1439
1cd986c5 1440{ "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
252b5132 1441
78c8d46c
NC		 1442/* v850e3v5 bitfield instructions. */
1443{ "bins", two (0x07e0, 0x0090), two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 0, PROCESSOR_V850E3V5_UP },
1444{ "bins", two (0x07e0, 0x00b0), two (0x07e0, 0x07f1), {R1, POS_M, WIDTH_M, R2}, 0, PROCESSOR_V850E3V5_UP },
1445{ "bins", two (0x07e0, 0x00d0), two (0x07e0, 0x07f1), {R1, POS_L, WIDTH_L, R2}, 0, PROCESSOR_V850E3V5_UP },
1446/* Gas local alias(not defined in spec). */
1447{ "binsu",two (0x07e0, 0x0090), two (0x07e0, 0x07f1), {R1, POS_U, WIDTH_U, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1448{ "binsm",two (0x07e0, 0x00b0), two (0x07e0, 0x07f1), {R1, POS_M, WIDTH_M, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1449{ "binsl",two (0x07e0, 0x00d0), two (0x07e0, 0x07f1), {R1, POS_L, WIDTH_L, R2}, 0, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1450
1451{ "cache", two (0xe7e0, 0x0160), two (0xe7e0, 0x07ff), {CACHEOP, R1}, 2, PROCESSOR_V850E3V5_UP },
1452
1cd986c5
NC		 1453{ "callt", one (0x0200), one (0xffc0), {IMM6}, 0, PROCESSOR_NOT_V850 },
1454
78c8d46c 1455{ "caxi", two (0x07e0, 0x00ee), two (0x07e0, 0x07ff), {R1, R2, R3}, 1, PROCESSOR_V850E2_UP },
1cd986c5
NC		 1456
1457{ "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1458{ "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 },
1459
1460{ "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1461{ "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 },
1462
1463{ "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL },
1464{ "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL },
1465
1466{ "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 },
1467
78c8d46c
NC		 1468{ "dbcp", one (0xe840), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1469
1470{ "dbhvtrap", one (0xe040), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1471
1472{ "dbpush", two (0x5fe0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP },
1473
1cd986c5
NC		 1474{ "dbret", two (0x07e0, 0x0146), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 },
1475
78c8d46c
NC		 1476{ "dbtag", two (0xcfe0, 0x0160), two (0xffe0, 0x07ff), {IMM10U}, 0, PROCESSOR_V850E3V5_UP },
1477
1cd986c5
NC		 1478{ "dbtrap", one (0xf840), one (0xffff), {0}, 0, PROCESSOR_NOT_V850 },
1479
1480{ "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
1481
1482{ "dispose", two (0x0640, 0x0000), two (0xffc0, 0x0000), {IMM5, LIST12, R2_DISPOSE},3, PROCESSOR_NOT_V850 },
1483{ "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 },
1484
1485{ "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1486
1487{ "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1488{ "divh", OP (0x02), OP_MASK, {R1_NOTR0, R2_NOTR0}, 0, PROCESSOR_ALL },
1489
1490{ "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1491
1492{ "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1493
1494{ "divhun", two (0x07e0, 0x0282), two (0x07e0, 0x07c3), {I5DIV1, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1495{ "divn", two (0x07e0, 0x02c0), two (0x07e0, 0x07c3), {I5DIV2, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1496
78c8d46c 1497{ "divq", two (0x07e0, 0x02fc), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1cd986c5 1498
78c8d46c 1499{ "divqu", two (0x07e0, 0x02fe), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1cd986c5
NC		 1500
1501{ "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1502
1503{ "divun", two (0x07e0, 0x02c2), two (0x07e0, 0x07c3), {I5DIV2, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1504
78c8d46c
NC		 1505{ "dst", two (0x07e0, 0x0134), two (0xfffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1506
1cd986c5
NC		 1507{ "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
1508
78c8d46c
NC		 1509{ "eiret", two (0x07e0, 0x0148), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP },
1510
1511{ "est", two (0x07e0, 0x0132), two (0xfffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1cd986c5 1512
78c8d46c 1513{ "feret", two (0x07e0, 0x014a), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2_UP },
1cd986c5 1514
78c8d46c 1515{ "fetrap", one (0x0040), one (0x87ff), {I4U_NOTIMM0}, 0, PROCESSOR_V850E2_UP },
1cd986c5
NC		 1516
1517{ "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
1518
78c8d46c 1519{ "hsh", two (0x07e0, 0x0346), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1cd986c5
NC		 1520
1521{ "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
1522
78c8d46c
NC		 1523{ "hvcall", two (0xd7e0, 0x4160), two (0xffe0, 0x41ff), {VECTOR8}, 0, PROCESSOR_V850E3V5_UP },
1524{ "hvtrap", two (0x07e0, 0x0110), two (0xffe0, 0xffff), {VECTOR5}, 0, PROCESSOR_V850E3V5_UP },
43e65147 1525
78c8d46c 1526{ "jarl", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, PROCESSOR_V850E3V5_UP},
1cd986c5 1527{ "jarl", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL},
78c8d46c
NC		 1528{ "jarl", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP },
1529/* Gas local alias (not defined in spec). */
1530{ "jarlr", two (0xc7e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3_NOTR0}, 1, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS},
1531/* Gas local alias of jarl imm22 (not defined in spec). */
1cd986c5 1532{ "jarl22", two (0x0780, 0x0000), two (0x07c0, 0x0001), {D22, R2_NOTR0}, 0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS},
78c8d46c
NC		 1533/* Gas local alias of jarl imm32 (not defined in spec). */
1534{ "jarl32", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1535{ "jarlw", one (0x02e0), one (0xffe0), {D32_31_PCREL, R1_NOTR0}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1cd986c5 1536
78c8d46c
NC		 1537{ "jmp", two (0x06e0, 0x0000), two (0xffe0, 0x0001), {D32_31, R1}, 2, PROCESSOR_V850E3V5_UP },
1538{ "jmp", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2 | PROCESSOR_V850E2V3 },
1cd986c5
NC		 1539{ "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL },
1540/* Gas local alias of jmp disp22(not defined in spec). */
1541{ "jmp22", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS },
1542/* Gas local alias of jmp disp32(not defined in spec). */
78c8d46c
NC		 1543{ "jmp32", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1544{ "jmpw", one (0x06e0), one (0xffe0), {D32_31, R1}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1cd986c5
NC		 1545
1546{ "jr", two (0x0780, 0x0000), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL },
78c8d46c 1547{ "jr", one (0x02e0), one (0xffff), {D32_31_PCREL}, 0, PROCESSOR_V850E2_UP },
1cd986c5
NC		 1548/* Gas local alias of mov imm22(not defined in spec). */
1549{ "jr22", two (0x0780, 0x0000), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL | PROCESSOR_OPTION_ALIAS },
1550/* Gas local alias of mov imm32(not defined in spec). */
78c8d46c 1551{ "jr32", one (0x02e0), one (0xffff), {D32_31_PCREL}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1cd986c5
NC		 1552
1553/* Alias of bcond (same as CA850). */
252b5132
RH		 1554{ "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1555{ "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1556{ "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1557{ "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL },
8ad30312 1558 /* Unsigned integer. */
252b5132
RH		 1559{ "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1560{ "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1561{ "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1562{ "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
8ad30312 1563 /* Common. */
252b5132
RH		 1564{ "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1565{ "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
8ad30312 1566 /* Others. */
252b5132
RH		 1567{ "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1568{ "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1569{ "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1570{ "jp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1571{ "jc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1572{ "jnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1573{ "jz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
1574{ "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
252b5132 1575{ "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL },
47b0e7ad 1576
252b5132 1577
78c8d46c 1578{ "ldacc", two (0x07e0, 0x0bc4), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
1cd986c5
NC		 1579
1580{ "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 2, PROCESSOR_ALL },
accc0180 1581{ "ld.b", two (0x0780, 0x0005), two (0xffe0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP },
78c8d46c 1582{ "ld.b23", two (0x0780, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1cd986c5
NC		 1583
1584{ "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 },
accc0180 1585{ "ld.bu", two (0x07a0, 0x0005), two (0xffe0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP },
78c8d46c
NC		 1586{ "ld.bu23", two (0x07a0, 0x0005), two (0x07e0, 0x000f), {D23, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1587
1588{ "ld.dw", two (0x07a0, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3_EVEN}, 2, PROCESSOR_V850E3V5_UP },
1589{ "ld.dw23", two (0x07a0, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3_EVEN}, 2, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1cd986c5
NC		 1590
1591{ "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, PROCESSOR_ALL },
78c8d46c
NC		 1592{ "ld.h", two (0x0780, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP },
1593{ "ld.h23", two (0x0780, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1cd986c5
NC		 1594
1595{ "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 2, PROCESSOR_NOT_V850 },
78c8d46c
NC		 1596{ "ld.hu", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP },
1597{ "ld.hu23", two (0x07a0, 0x0007), two (0x07e0, 0x000f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1cd986c5
NC		 1598
1599{ "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 2, PROCESSOR_ALL },
78c8d46c
NC		 1600{ "ld.w", two (0x0780, 0x0009), two (0xffe0, 0x001f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP },
1601{ "ld.w23", two (0x0780, 0x0009), two (0x07e0, 0x001f), {D23_ALIGN1, R1, R3}, 2, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
252b5132 1602
78c8d46c 1603{ "ldl.w", two (0x07e0, 0x0378), two (0xffe0, 0x07ff), {R1, R3}, 1, PROCESSOR_V850E3V5_UP },
1cd986c5 1604
78c8d46c
NC		 1605{ "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1606{ "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
1607{ "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0x07ff), {R1, OLDSR2}, 0, (PROCESSOR_ALL & (~ PROCESSOR_V850E3V5_UP)) },
1cd986c5 1608
78c8d46c
NC		 1609{ "ldtc.gr", two (0x07e0, 0x0032), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E3V5_UP },
1610{ "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1611{ "ldtc.sr", two (0x07e0, 0x0030), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
1cd986c5 1612
78c8d46c
NC		 1613{ "ldtc.vr", two (0x07e0, 0x0832), two (0x07e0, 0xffff), {R1, VR2}, 0, PROCESSOR_V850E3V5_UP },
1614{ "ldtc.pc", two (0x07e0, 0xf832), two (0x07e0, 0xffff), {R1}, 0, PROCESSOR_V850E3V5_UP },
1cd986c5 1615
78c8d46c
NC		 1616{ "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1617{ "ldvc.sr", two (0x07e0, 0x0034), two (0x07e0, 0x07ff), {R1, SR2}, 0, PROCESSOR_V850E3V5_UP },
1618
1619{ "loop", two (0x06e0, 0x0001), two (0xffe0, 0x0001), {R1, D16_LOOP}, 0, PROCESSOR_V850E3V5_UP },
1620
1621{ "macacc", two (0x07e0, 0x0bc0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
1622
1623{ "mac", two (0x07e0, 0x03c0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, PROCESSOR_V850E2_UP },
1624
1625{ "macu", two (0x07e0, 0x03e0), two (0x07e0, 0x0fe1), {R1, R2, R3_EVEN, R4_EVEN}, 0, PROCESSOR_V850E2_UP },
1626
1627{ "macuacc", two (0x07e0, 0x0bc2), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
1cd986c5
NC		 1628
1629{ "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1630{ "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
1631{ "mov", one (0x0620), one (0xffe0), {IMM32, R1}, 0, PROCESSOR_NOT_V850 },
1632/* Gas local alias of mov imm32(not defined in spec). */
1633{ "movl", one (0x0620), one (0xffe0), {IMM32, R1}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_ALIAS },
1634
1635{ "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1636
1637{ "movhi", OP (0x32), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1638
1639{ "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1640{ "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 },
1641
1642{ "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
1643{ "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1644
1645{ "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1646
1647{ "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
1648{ "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0, PROCESSOR_NOT_V850 },
1649
1650{ "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL },
1651
1652{ "not", OP (0x01), OP_MASK, IF1, 0, PROCESSOR_ALL },
1653
1654{ "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1655{ "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 },
1656
1657{ "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL },
1658
1659{ "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL },
1660
78c8d46c
NC		 1661{ "popsp", two (0x67e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP },
1662
1663{ "pref", two (0xdfe0, 0x0160), two (0xffe0, 0x07ff), {PREFOP, R1}, 2, PROCESSOR_V850E3V5_UP },
1664
1cd986c5
NC		 1665{ "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 },
1666{ "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16LO},0, PROCESSOR_NOT_V850 },
1667{ "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16HI},0, PROCESSOR_NOT_V850 },
1668{ "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0, PROCESSOR_NOT_V850 },
1669{ "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0, PROCESSOR_NOT_V850 },
1670
78c8d46c
NC		 1671{ "pushsp", two (0x47e0, 0x0160), two (0xffe0, 0x07ff), {R1, R3}, 0, PROCESSOR_V850E3V5_UP },
1672
1673{ "rotl", two (0x07e0, 0x00c6), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1674{ "rotl", two (0x07e0, 0x00c4), two (0x07e0, 0x07ff), {I5U, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1675
1cd986c5
NC		 1676{ "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
1677
78c8d46c 1678{ "sar", two (0x07e0, 0x00a2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1cd986c5
NC		 1679{ "sar", OP (0x15), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL },
1680{ "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
1681
1682{ "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 },
1683
78c8d46c 1684{ "satadd", two (0x07e0, 0x03ba), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1cd986c5
NC		 1685{ "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
1686{ "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1687
78c8d46c 1688{ "satsub", two (0x07e0, 0x039a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1cd986c5
NC		 1689{ "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1690
1691{ "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1692
1693{ "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
1694
78c8d46c 1695{ "sbf", two (0x07e0, 0x0380), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1cd986c5 1696
78c8d46c 1697{ "sch0l", two (0x07e0, 0x0364), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1cd986c5 1698
78c8d46c 1699{ "sch0r", two (0x07e0, 0x0360), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1cd986c5 1700
78c8d46c 1701{ "sch1l", two (0x07e0, 0x0366), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1cd986c5 1702
78c8d46c 1703{ "sch1r", two (0x07e0, 0x0362), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2_UP },
1cd986c5
NC		 1704
1705{ "sdivhn", two (0x07e0, 0x0180), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1706{ "sdivhun", two (0x07e0, 0x0182), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1707{ "sdivn", two (0x07e0, 0x01c0), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1708{ "sdivun", two (0x07e0, 0x01c2), two (0x07e0, 0x07c3), {I5DIV3, R1, R2, R3}, 0, PROCESSOR_NOT_V850 | PROCESSOR_OPTION_EXTENSION },
1709
1710{ "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1711{ "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 },
1712
1713{ "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL },
1714
78c8d46c 1715{ "shl", two (0x07e0, 0x00c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1cd986c5
NC		 1716{ "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL },
1717{ "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
1718
78c8d46c 1719{ "shr", two (0x07e0, 0x0082), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2_UP },
1cd986c5
NC		 1720{ "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL },
1721{ "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
1722
1723{ "sld.b", one (0x0300), one (0x0780), {D7U, EP, R2}, 2, PROCESSOR_ALL },
1724
1725{ "sld.bu", one (0x0060), one (0x07f0), {D4U, EP, R2_NOTR0}, 2, PROCESSOR_NOT_V850 },
1726
1727{ "sld.h", one (0x0400), one (0x0780), {D8_7U,EP, R2}, 2, PROCESSOR_ALL },
1728
1729{ "sld.hu", one (0x0070), one (0x07f0), {D5_4U,EP, R2_NOTR0}, 2, PROCESSOR_NOT_V850 },
1730
1731{ "sld.w", one (0x0500), one (0x0781), {D8_6U,EP, R2}, 2, PROCESSOR_ALL },
1732
78c8d46c
NC		 1733{ "snooze", two (0x0fe0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1734
1cd986c5
NC		 1735{ "sst.b", one (0x0380), one (0x0780), {R2, D7U, EP}, 3, PROCESSOR_ALL },
1736
1737{ "sst.h", one (0x0480), one (0x0780), {R2, D8_7U,EP}, 3, PROCESSOR_ALL },
1738
1739{ "sst.w", one (0x0501), one (0x0781), {R2, D8_6U,EP}, 3, PROCESSOR_ALL },
1740
78c8d46c
NC		 1741{ "stacch", two (0x07e0, 0x0bca), two (0x07ff, 0xffff), {R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
1742{ "staccl", two (0x07e0, 0x0bc8), two (0x07ff, 0xffff), {R2}, 0, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_EXTENSION },
1cd986c5
NC		 1743
1744{ "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 3, PROCESSOR_ALL },
78c8d46c
NC		 1745{ "st.b", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_UP },
1746{ "st.b23", two (0x0780, 0x000d), two (0x07e0, 0x000f), {R3, D23, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1747
1748{ "st.dw", two (0x07a0, 0x000f), two (0xffe0, 0x001f), {R3_EVEN, D23_ALIGN1, R1}, 3, PROCESSOR_V850E3V5_UP },
1749{ "st.dw23", two (0x07a0, 0x000f), two (0xffe0, 0x001f), {R3_EVEN, D23_ALIGN1, R1}, 3, PROCESSOR_V850E3V5_UP | PROCESSOR_OPTION_ALIAS },
1cd986c5
NC		 1750
1751{ "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, PROCESSOR_ALL },
78c8d46c
NC		 1752{ "st.h", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP },
1753{ "st.h23", two (0x07a0, 0x000d), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1cd986c5
NC		 1754
1755{ "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 3, PROCESSOR_ALL },
78c8d46c
NC		 1756{ "st.w", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP },
1757{ "st.w23", two (0x0780, 0x000f), two (0x07e0, 0x000f), {R3, D23_ALIGN1, R1}, 3, PROCESSOR_V850E2_UP | PROCESSOR_OPTION_ALIAS },
1758
1759{ "stc.w", two (0x07e0, 0x037a), two (0xffe0, 0x07ff), {R3, R1}, 2, PROCESSOR_V850E3V5_UP },
1760
1761{ "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1762{ "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP },
1763{ "stsr", two (0x07e0, 0x0040), two (0x07e0, 0x07ff), {OLDSR1, R2}, 0, (PROCESSOR_ALL & (~ PROCESSOR_V850E3V5_UP)) },
1764
1765{ "sttc.gr", two (0x07e0, 0x0052), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_V850E3V5_UP },
1766{ "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1767{ "sttc.sr", two (0x07e0, 0x0050), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP },
1768{ "sttc.vr", two (0x07e0, 0x0852), two (0x07e0, 0xffff), {VR1, R2}, 0, PROCESSOR_V850E3V5_UP },
1769{ "sttc.pc", two (0x07e0, 0xf852), two (0x07e0, 0xffff), {R2}, 0, PROCESSOR_V850E3V5_UP },
1cd986c5 1770
78c8d46c
NC		 1771{ "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2, SELID}, 0, PROCESSOR_V850E3V5_UP },
1772{ "stvc.sr", two (0x07e0, 0x0054), two (0x07e0, 0x07ff), {SR1, R2}, 0, PROCESSOR_V850E3V5_UP },
252b5132 1773
1cd986c5
NC		 1774{ "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL },
1775
1776{ "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL },
1777
1778{ "switch", one (0x0040), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 },
1779
1780{ "sxb", one (0x00a0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 },
1781
1782{ "sxh", one (0x00e0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 },
1783
78c8d46c
NC		 1784{ "tlbai", two (0x87e0, 0x8960), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1785{ "tlbr", two (0x87e0, 0xe960), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1786{ "tlbs", two (0x87e0, 0xc160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1787{ "tlbvi", two (0x87e0, 0x8160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1788{ "tlbw", two (0x87e0, 0xe160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1789
1cd986c5
NC		 1790{ "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL },
1791
1792{ "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL },
1793
1794{ "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 3, PROCESSOR_ALL },
1795{ "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 3, PROCESSOR_NOT_V850 },
1796
1797{ "xor", OP (0x09), OP_MASK, IF1, 0, PROCESSOR_ALL },
1798
1799{ "xori", OP (0x35), OP_MASK, IF6U, 0, PROCESSOR_ALL },
1800
1801{ "zxb", one (0x0080), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 },
1802
1803{ "zxh", one (0x00c0), one (0xffe0), {R1}, 0, PROCESSOR_NOT_V850 },
1804
1805/* Floating point operation. */
78c8d46c
NC		 1806{ "absf.d", two (0x07e0, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1807{ "absf.s", two (0x07e0, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1808{ "addf.d", two (0x07e0, 0x0470), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1809{ "addf.s", two (0x07e0, 0x0460), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1810{ "ceilf.dl", two (0x07e2, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1811{ "ceilf.dul", two (0x07f2, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1812{ "ceilf.duw", two (0x07f2, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1813{ "ceilf.dw", two (0x07e2, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1814{ "ceilf.sl", two (0x07e2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1815{ "ceilf.sul", two (0x07f2, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1816{ "ceilf.suw", two (0x07f2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1817{ "ceilf.sw", two (0x07e2, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
78c8d46c 1818{ "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0ff1), {FFF, R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP },
1cd986c5 1819/* Default value for FFF is 0(not defined in spec). */
78c8d46c
NC		 1820{ "cmovf.d", two (0x07e0, 0x0410), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN_NOTR0}, 0, PROCESSOR_V850E2V3_UP },
1821{ "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07f1), {FFF, R1, R2, R3_NOTR0}, 0, PROCESSOR_V850E2V3_UP },
1cd986c5 1822/* Default value for FFF is 0(not defined in spec). */
78c8d46c
NC		 1823{ "cmovf.s", two (0x07e0, 0x0400), two (0x07e0, 0x07ff), {R1, R2, R3_NOTR0}, 0, PROCESSOR_V850E2V3_UP },
1824{ "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87f1), {FLOAT_CCCC, R2_EVEN, R1_EVEN, FFF}, 0, PROCESSOR_V850E2V3_UP },
1825{ "cmpf.d", two (0x07e0, 0x0430), two (0x0fe1, 0x87ff), {FLOAT_CCCC, R2_EVEN, R1_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1826{ "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87f1), {FLOAT_CCCC, R2, R1, FFF}, 0, PROCESSOR_V850E2V3_UP },
1827{ "cmpf.s", two (0x07e0, 0x0420), two (0x07e0, 0x87ff), {FLOAT_CCCC, R2, R1}, 0, PROCESSOR_V850E2V3_UP },
1828{ "cvtf.dl", two (0x07e4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1829{ "cvtf.ds", two (0x07e3, 0x0452), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1830{ "cvtf.dul", two (0x07f4, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1831{ "cvtf.duw", two (0x07f4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1832{ "cvtf.dw", two (0x07e4, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
41702d50 1833{ "cvtf.hs", two (0x07e2, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E3V5_UP },
78c8d46c
NC		 1834{ "cvtf.ld", two (0x07e1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1835{ "cvtf.ls", two (0x07e1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1836{ "cvtf.sd", two (0x07e2, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1837{ "cvtf.sl", two (0x07e4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
41702d50 1838{ "cvtf.sh", two (0x07e3, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E3V5_UP },
78c8d46c
NC		 1839{ "cvtf.sul", two (0x07f4, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1840{ "cvtf.suw", two (0x07f4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1841{ "cvtf.sw", two (0x07e4, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1842{ "cvtf.uld", two (0x07f1, 0x0452), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1843{ "cvtf.uls", two (0x07f1, 0x0442), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1844{ "cvtf.uwd", two (0x07f0, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1845{ "cvtf.uws", two (0x07f0, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1846{ "cvtf.wd", two (0x07e0, 0x0452), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1847{ "cvtf.ws", two (0x07e0, 0x0442), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1848{ "divf.d", two (0x07e0, 0x047e), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1849{ "divf.s", two (0x07e0, 0x046e), two (0x07e0, 0x07ff), {R1_NOTR0, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1850{ "floorf.dl", two (0x07e3, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1851{ "floorf.dul", two (0x07f3, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1852{ "floorf.duw", two (0x07f3, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1853{ "floorf.dw", two (0x07e3, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1854{ "floorf.sl", two (0x07e3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1855{ "floorf.sul", two (0x07f3, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1856{ "floorf.suw", two (0x07f3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1857{ "floorf.sw", two (0x07e3, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
41702d50
NC		 1858{ "maddf.s", two (0x07e0, 0x0500), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
1859{ "fmaf.s", two (0x07e0, 0x04e0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
78c8d46c
NC		 1860{ "maxf.d", two (0x07e0, 0x0478), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1861{ "maxf.s", two (0x07e0, 0x0468), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1862{ "minf.d", two (0x07e0, 0x047a), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1863{ "minf.s", two (0x07e0, 0x046a), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
41702d50
NC		 1864{ "msubf.s", two (0x07e0, 0x0520), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
1865{ "fmsf.s", two (0x07e0, 0x04e2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
78c8d46c
NC		 1866{ "mulf.d", two (0x07e0, 0x0474), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1867{ "mulf.s", two (0x07e0, 0x0464), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1868{ "negf.d", two (0x07e1, 0x0458), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1869{ "negf.s", two (0x07e1, 0x0448), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
41702d50
NC		 1870{ "nmaddf.s", two (0x07e0, 0x0540), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
1871{ "fnmaf.s", two (0x07e0, 0x04e4), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
1872{ "nmsubf.s", two (0x07e0, 0x0560), two (0x07e0, 0x0761), {R1, R2, R3, R4}, 0, PROCESSOR_V850E2V3 },
1873{ "fnmsf.s", two (0x07e0, 0x04e6), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E3V5_UP },
78c8d46c
NC		 1874{ "recipf.d", two (0x07e1, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1875{ "recipf.s", two (0x07e1, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1876
1877{ "roundf.dl", two (0x07e0, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1878{ "roundf.dul", two (0x07f0, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1879{ "roundf.duw", two (0x07f0, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1880{ "roundf.dw", two (0x07e0, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1881{ "roundf.sl", two (0x07e0, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1882{ "roundf.sul", two (0x07f0, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1883{ "roundf.suw", two (0x07f0, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1884{ "roundf.sw", two (0x07e0, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_EXTENSION },
1885
1886{ "rsqrtf.d", two (0x07e2, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1887{ "rsqrtf.s", two (0x07e2, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1888{ "sqrtf.d", two (0x07e0, 0x045e), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1889{ "sqrtf.s", two (0x07e0, 0x044e), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1890{ "subf.d", two (0x07e0, 0x0472), two (0x0fe1, 0x0fff), {R1_EVEN, R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1891{ "subf.s", two (0x07e0, 0x0462), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1892{ "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xfff1), {FFF}, 0, PROCESSOR_V850E2V3_UP },
1893{ "trfsr", two (0x07e0, 0x0400), two (0xffff, 0xffff), {0}, 0, PROCESSOR_V850E2V3_UP },
1894{ "trncf.dl", two (0x07e1, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1895{ "trncf.dul", two (0x07f1, 0x0454), two (0x0fff, 0x0fff), {R2_EVEN, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1896{ "trncf.duw", two (0x07f1, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1897{ "trncf.dw", two (0x07e1, 0x0450), two (0x0fff, 0x07ff), {R2_EVEN, R3}, 0, PROCESSOR_V850E2V3_UP },
1898{ "trncf.sl", two (0x07e1, 0x0444), two (0x07ff, 0x0fff), {R2, R3_EVEN}, 0, PROCESSOR_V850E2V3_UP },
1899{ "trncf.sul", two (0x07f1, 0x0444), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1900{ "trncf.suw", two (0x07f1, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1901{ "trncf.sw", two (0x07e1, 0x0440), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_V850E2V3_UP },
1cd986c5
NC		 1902
1903 /* Special instruction (from gdb) mov 1, r0. */
1904{ "breakpoint", one (0x0001), one (0xffff), {UNUSED}, 0, PROCESSOR_ALL },
1905
78c8d46c 1906{ "synci", one (0x001c), one (0xffff), {0}, 0, PROCESSOR_V850E3V5_UP },
1cd986c5 1907
78c8d46c
NC		 1908{ "synce", one (0x001d), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP },
1909{ "syncm", one (0x001e), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP },
1910{ "syncp", one (0x001f), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP },
1911{ "syscall", two (0xd7e0, 0x0160), two (0xffe0, 0xc7ff), {V8}, 0, PROCESSOR_V850E2V3_UP },
1912 /* Alias of syncp. */
1913{ "sync", one (0x001f), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP | PROCESSOR_OPTION_ALIAS },
1914{ "rmtrap", one (0xf040), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP },
1915{ "rie", one (0x0040), one (0xffff), {0}, 0, PROCESSOR_V850E2V3_UP },
1916{ "rie", two (0x07f0, 0x0000), two (0x07f0, 0xffff), {RIE_IMM5,RIE_IMM4}, 0, PROCESSOR_V850E2V3_UP },
1cd986c5
NC		 1917
1918{ 0, 0, 0, {0}, 0, 0 },
252b5132
RH		 1919} ;
1920
1921const int v850_num_opcodes =
1922 sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
GDB Binutils - Deliverables
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