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Moved divh opcodes next to each other.
[deliverable/binutils-gdb.git] / opcodes / v850-opc.c
CommitLineData
072b27ea
JL		 1/* Assemble V850 instructions.
2 Copyright (C) 1996 Free Software Foundation, Inc.
3
4This program is free software; you can redistribute it and/or modify
5it under the terms of the GNU General Public License as published by
6the Free Software Foundation; either version 2 of the License, or
7(at your option) any later version.
8
9This program is distributed in the hope that it will be useful,
10but WITHOUT ANY WARRANTY; without even the implied warranty of
11MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12GNU General Public License for more details.
13
14You should have received a copy of the GNU General Public License
15along with this program; if not, write to the Free Software
16Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17
6d1e1ee8
C		 18#include "ansidecl.h"
19#include "opcode/v850.h"
0c519399 20#include <stdio.h>
4f235110 21
6d1e1ee8
C		 22/* regular opcode */
23#define OP(x) ((x & 0x3f) << 5)
0c519399 24#define OP_MASK OP (0x3f)
6d1e1ee8
C		 25
26/* conditional branch opcode */
27#define BOP(x) ((0x0b << 7) | (x & 0x0f))
502535cf 28#define BOP_MASK ((0x0f << 7) | 0x0f)
6d1e1ee8
C		 29
30/* one-word opcodes */
31#define one(x) ((unsigned int) (x))
32
33/* two-word opcodes */
b1e897a9 34#define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16))
6d1e1ee8
C		 35
36
0c519399
NC		 37\f
38/* The functions used to insert and extract complicated operands. */
39
40static unsigned long
41insert_d9 (insn, value, errmsg)
42 unsigned long insn;
43 long value;
44 const char **errmsg;
45{
46 if (value > 0xff || value < -0x100)
47 *errmsg = "branch value out of range";
48
49 if ((value % 2) != 0)
50 *errmsg = "branch to odd offset";
51
52 return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
53}
54
55static unsigned long
56extract_d9 (insn, invalid)
57 unsigned long insn;
58 int *invalid;
59{
60 unsigned long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);
61
62 if ((insn & 0x8000) != 0)
63 ret -= 0x0200;
64
65 return ret;
66}
67
68static unsigned long
69insert_d22 (insn, value, errmsg)
70 unsigned long insn;
71 long value;
72 const char **errmsg;
73{
74 if (value > 0x1fffff || value < -0x200000)
75 *errmsg = "branch value out of range";
76
77 if ((value % 2) != 0)
78 *errmsg = "branch to odd offset";
79
80 return (insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16));
81}
82
83static unsigned long
84extract_d22 (insn, invalid)
85 unsigned long insn;
86 int *invalid;
87{
88 unsigned long ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16);
89
90 return ((ret << 10) >> 10);
91}
92
93static unsigned long
94insert_d16_15 (insn, value, errmsg)
95 unsigned long insn;
96 long value;
97 const char **errmsg;
98{
99 if (value > 0x7fff || value < -0x8000)
100 *errmsg = "value out of range";
101
102 if ((value % 2) != 0)
103 *errmsg = "load/store half/word at odd offset";
104
105 return insn | ((value & 0xfffe) << 16);
106}
107
108static unsigned long
109extract_d16_15 (insn, invalid)
110 unsigned long insn;
111 int *invalid;
112{
113 signed long ret = (insn & 0xfffe0000);
114
115 return ret >> 16;
116}
117
118static unsigned long
119insert_d8_7 (insn, value, errmsg)
120 unsigned long insn;
121 long value;
122 const char **errmsg;
123{
124 if (value > 0xff || value < 0)
125 *errmsg = "short load/store half value out of range";
126
127 if ((value % 2) != 0)
128 *errmsg = "short load/store half at odd offset";
129
130 value >>= 1;
131
132 return (insn | (value & 0x7f));
133}
134
135static unsigned long
136extract_d8_7 (insn, invalid)
137 unsigned long insn;
138 int *invalid;
139{
140 unsigned long ret = (insn & 0x7f);
141
142 return ret << 1;
143}
144
145static unsigned long
146insert_d8_6 (insn, value, errmsg)
147 unsigned long insn;
148 long value;
149 const char **errmsg;
150{
151 if (value > 0xff || value < 0)
152 *errmsg = "short load/store word value out of range";
153
154 if ((value % 4) != 0)
155 *errmsg = "short load/store word at odd offset";
156
157 value >>= 1;
158
159 return (insn | (value & 0x7e));
160}
161
162static unsigned long
163extract_d8_6 (insn, invalid)
164 unsigned long insn;
165 int *invalid;
166{
167 unsigned long ret = (insn & 0x7e);
168
169 return ret << 1;
170}
171
172/* start-sanitize-v850e */
173
174static unsigned long
175insert_d5_4 (insn, value, errmsg)
176 unsigned long insn;
177 long value;
178 const char ** errmsg;
179{
180 if (value > 0x1f || value < 0)
181 *errmsg = "unsigned short load half value out of range";
182
183 if (value & 1)
184 *errmsg = "unsigned short load half at odd offset";
185
186 value >>= 1;
187
188 return (insn | (value & 0x0f));
189}
190
191static unsigned long
192extract_d5_4 (insn, invalid)
193 unsigned long insn;
194 int * invalid;
195{
196 unsigned long ret = (insn & 0x0f);
197
198 return ret << 1;
199}
200
201static unsigned long
202insert_d16_16 (insn, value, errmsg)
203 unsigned long insn;
204 signed long value;
205 const char ** errmsg;
206{
207 if (value > 0x7fff || value < -0x8000)
208 *errmsg = "value out of range";
209
210 return (insn | ((value & 0xfffe) << 16) | ((value & 1) << 5));
211}
212
213static unsigned long
214extract_d16_16 (insn, invalid)
215 unsigned long insn;
216 int * invalid;
217{
218 signed long ret = insn & 0xfffe0000;
219
220 ret >>= 16;
221
222 ret |= ((insn & 0x20) >> 5);
223
224 return ret;
225}
226
227static unsigned long
228insert_i9 (insn, value, errmsg)
229 unsigned long insn;
230 signed long value;
231 const char ** errmsg;
232{
233 if (value > 0xff || value < -0x100)
234 *errmsg = "value out of range";
235
236 return insn | ((value & 0x1e0) << 13) | (value & 0x1f);
237}
238
239static unsigned long
240extract_i9 (insn, invalid)
241 unsigned long insn;
242 int * invalid;
243{
244 signed long ret = insn & 0x003c0000;
245
246 ret <<= 10;
247 ret >>= 23;
248
249 ret |= (insn & 0x1f);
250
251 return ret;
252}
253
254static unsigned long
255insert_u9 (insn, value, errmsg)
256 unsigned long insn;
257 unsigned long value;
258 const char ** errmsg;
259{
260 if (value > 0x1ff)
261 *errmsg = "value out of range";
262
263 return insn | ((value & 0x1e0) << 13) | (value & 0x1f);
264}
265
266static unsigned long
267extract_u9 (insn, invalid)
268 unsigned long insn;
269 int * invalid;
270{
271 unsigned long ret = insn & 0x003c0000;
272
273 ret >>= 13;
274
275 ret |= (insn & 0x1f);
276
277 return ret;
278}
279
280/* start-sanitize-v850e */
281static unsigned long
282insert_spe (insn, value, errmsg)
283 unsigned long insn;
284 unsigned long value;
285 const char ** errmsg;
286{
287 if (value != 3)
288 *errmsg = "invalid register for stack adjustment";
289
290 return insn & (~ 0x180000);
291}
292
293static unsigned long
294extract_spe (insn, invalid)
295 unsigned long insn;
296 int * invalid;
297{
298 return 3;
299}
300
301/* end-sanitize-v850e */
302/* start-sanitize-v850eq */
303
304static unsigned long
305insert_i5div (insn, value, errmsg)
306 unsigned long insn;
307 unsigned long value;
308 const char ** errmsg;
309{
310 if (value > 0x1ff)
311 *errmsg = "value out of range";
312
313 if (value & 1)
314 *errmsg = "value must be even";
315
316 value = 32 - value;
317
318 return insn | ((value & 0x1e) << 17);
319}
320
321static unsigned long
322extract_i5div (insn, invalid)
323 unsigned long insn;
324 int * invalid;
325{
326 unsigned long ret = insn & 0x3c0000;
327
328 ret >>= 17;
329
330 ret = 32 - ret;
331
332 return ret;
333}
334
335/* end-sanitize-v850eq */
336
6d1e1ee8
C		 337\f
338const struct v850_operand v850_operands[] = {
339#define UNUSED 0
69463cbb 340 { 0, 0, 0, 0, 0 },
6d1e1ee8
C		 341
342/* The R1 field in a format 1, 6, 7, or 9 insn. */
343#define R1 (UNUSED+1)
69463cbb 344 { 5, 0, 0, 0, V850_OPERAND_REG },
6d1e1ee8
C		 345
346/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
347#define R2 (R1+1)
69463cbb 348 { 5, 11, 0, 0, V850_OPERAND_REG },
6d1e1ee8
C		 349
350/* The IMM5 field in a format 2 insn. */
351#define I5 (R2+1)
dbc6a8f6
C		 352 { 5, 0, 0, 0, V850_OPERAND_SIGNED },
353
354#define I5U (I5+1)
355 { 5, 0, 0, 0, 0 },
6d1e1ee8 356
4f235110 357/* The IMM16 field in a format 6 insn. */
dbc6a8f6 358#define I16 (I5U+1)
e7dd7775 359 { 16, 16, 0, 0, V850_OPERAND_SIGNED },
6d1e1ee8 360
4be84c49 361/* The signed DISP7 field in a format 4 insn. */
b2194164
JL		 362#define D7 (I16+1)
363 { 7, 0, 0, 0, 0},
6d1e1ee8 364
6d1e1ee8 365/* The DISP16 field in a format 6 insn. */
244558e3 366#define D16_15 (D7+1)
c6b9c135 367 { 16, 16, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED },
6d1e1ee8 368
244558e3 369#define B3 (D16_15+1)
7c8157dd 370/* The 3 bit immediate field in format 8 insn. */
3c72ab70 371 { 3, 11, 0, 0, 0 },
69463cbb
C		 372
373#define CCCC (B3+1)
374/* The 4 bit condition code in a setf instruction */
4be84c49
JL		 375 { 4, 0, 0, 0, V850_OPERAND_CC },
376
b2194164
JL		 377/* The unsigned DISP8_7 field in a format 4 insn. */
378#define D8_7 (CCCC+1)
0068e79c 379 { 8, 0, insert_d8_7, extract_d8_7, V850_OPERAND_ADJUST_SHORT_MEMORY },
b2194164
JL		 380
381/* The unsigned DISP8_6 field in a format 4 insn. */
382#define D8_6 (D8_7+1)
0068e79c 383 { 8, 0, insert_d8_6, extract_d8_6, V850_OPERAND_ADJUST_SHORT_MEMORY },
4be84c49 384
e41c99bd 385/* System register operands. */
b2194164 386#define SR1 (D8_6+1)
d3edb57f
JL		 387 { 5, 0, 0, 0, V850_OPERAND_SRG },
388
389/* EP Register. */
390#define EP (SR1+1)
e7dd7775
JL		 391 { 0, 0, 0, 0, V850_OPERAND_EP },
392
393/* The IMM16 field (unsigned0 in a format 6 insn. */
394#define I16U (EP+1)
395 { 16, 16, 0, 0, 0},
e9ebb364
JL		 396
397/* The R2 field as a system register. */
398#define SR2 (I16U+1)
399 { 5, 11, 0, 0, V850_OPERAND_SRG },
400
c6b9c135
JL		 401/* The DISP16 field in a format 8 insn. */
402#define D16 (SR2+1)
403 { 16, 16, 0, 0, V850_OPERAND_SIGNED },
404
244558e3
JL		 405/* The DISP22 field in a format 4 insn, relaxable. */
406#define D9_RELAX (D16+1)
407 { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP },
408
409/* The DISP22 field in a format 4 insn.
410
411 This _must_ follow D9_RELAX; the assembler assumes that the longer
412 version immediately follows the shorter version for relaxing. */
413#define D22 (D9_RELAX+1)
414 { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP },
415
0c519399
NC		 416/* start-sanitize-v850e */
417
418/* The signed DISP4 field in a format 4 insn. */
419#define D4 (D22+1)
420 { 4, 0, 0, 0, 0},
421
422/* The unsigned DISP5_4 field in a format 4 insn. */
423#define D5_4 (D4 + 1)
424 { 5, 0, insert_d5_4, extract_d5_4, V850_OPERAND_ADJUST_SHORT_MEMORY },
425
426/* The DISP16 field in an unsigned format 7 byte load insn. */
427#define D16_16 (D5_4 + 1)
428 { 16, 16, insert_d16_16, extract_d16_16, 0 },
429
430/* Third register in conditional moves. */
431#define R3 (D16_16 + 1)
432 { 5, 27, 0, 0, V850_OPERAND_REG },
433
434/* Condition code in conditional moves. */
435#define MOVCC (R3 + 1)
436 { 4, 17, 0, 0, V850_OPERAND_CC },
437
438/* The IMM9 field in a multiply word. */
439#define I9 (MOVCC + 1)
440 { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED },
441
442/* The IMM9 field in a multiply word. */
443#define U9 (I9 + 1)
444 { 9, 0, insert_u9, extract_u9, 0 },
445
446/* A list of registers in a prepare/dispose instruction. */
447#define LIST12 (U9 + 1)
448 { -1, 0xffe00001, 0, 0, V850E_PUSH_POP },
449
450/* The IMM6 field in a call instruction. */
451#define I6 (LIST12 + 1)
452 { 6, 0, 0, 0, 0 },
453
454/* The 16 bit immediate following a 32 bit instruction. */
455#define IMM16 (I6 + 1)
456 { 16, 16, 0, 0, V850_OPERAND_SIGNED | V850E_IMMEDIATE16 },
457
458/* The 32 bit immediate following a 32 bit instruction. */
459#define IMM32 (IMM16 + 1)
460 { 0, 0, 0, 0, V850E_IMMEDIATE32 },
461
462/* The IMM5 field in a push/pop instruction. */
463#define IMM5 (IMM32 + 1)
464 { 5, 1, 0, 0, 0 },
465
466/* Reg2 in dispose instruction. */
467#define R2DISPOSE (IMM5 + 1)
468 { 5, 16, 0, 0, V850_OPERAND_REG },
469
470/* Stack pointer in prepare instruction. */
471#define SP (R2DISPOSE + 1)
472 { 2, 19, insert_spe, extract_spe, V850_OPERAND_REG },
473
474/* end-sanitize-v850e */
475/* start-sanitize-v850eq */
476
477/* The IMM5 field in a divide N step instruction. */
478#define I5DIV (SP + 1)
479 { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED },
480
481 /* The list of registers in a PUSHMH/POPMH instruction. */
482#define LIST18_H (I5DIV + 1)
483 { -1, 0xfff8000f, 0, 0, V850E_PUSH_POP },
484
485 /* The list of registers in a PUSHML/POPML instruction. */
486#define LIST18_L (LIST18_H + 1)
487 { -1, 0xfff8001f, 0, 0, V850E_PUSH_POP }, /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c */
488
489/* end-sanitize-v850eq */
6d1e1ee8
C		 490} ;
491
492\f
493/* reg-reg instruction format (Format I) */
494#define IF1 {R1, R2}
495
496/* imm-reg instruction format (Format II) */
497#define IF2 {I5, R2}
498
499/* conditional branch instruction format (Format III) */
244558e3 500#define IF3 {D9_RELAX}
6d1e1ee8 501
6d1e1ee8 502/* 3 operand instruction (Format VI) */
e89a42c1 503#define IF6 {I16, R1, R2}
6d1e1ee8 504
e7dd7775
JL		 505/* 3 operand instruction (Format VI) */
506#define IF6U {I16U, R1, R2}
507
6d1e1ee8
C		 508
509\f
510/* The opcode table.
511
512 The format of the opcode table is:
513
0c519399 514 NAME OPCODE MASK { OPERANDS } MEMOP
6d1e1ee8
C		 515
516 NAME is the name of the instruction.
517 OPCODE is the instruction opcode.
518 MASK is the opcode mask; this is used to tell the disassembler
519 which bits in the actual opcode must match OPCODE.
520 OPERANDS is the list of operands.
0c519399
NC		 521 MEMOP specifies which operand (if any) is a memory operand.
522
6d1e1ee8
C		 523 The disassembler reads the table in order and prints the first
524 instruction which matches, so this table is sorted to put more
525 specific instructions before more general instructions. It is also
526 sorted by major opcode. */
527
0c519399
NC		 528const struct v850_opcode v850_opcodes[] =
529{
530{ "breakpoint", 0xffff, 0xffff, {UNUSED}, 0 },
531
532{ "jmp", one (0x0060), one (0xffe0), {R1}, 1 },
533
6d1e1ee8 534/* load/store instructions */
0c519399
NC		 535#ifdef ARCH_v850eq
536{ "sld.bu", one (0x0300), one (0x0780), {D7, EP, R2}, 1 },
537{ "sld.hu", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1 },
538{ "sld.b", one (0x0060), one (0x07f0), {D4, EP, R2}, 1 },
539{ "sld.h", one (0x0070), one (0x07f0), {D5_4, EP, R2}, 1 },
540#else
541{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1 },
542{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1 },
543{ "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2}, 1 },
544{ "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2}, 1 },
545#endif
546{ "sld.w", one (0x0500), one (0x0781), {D8_6, EP, R2}, 1 },
547{ "sst.b", one (0x0380), one (0x0780), {R2, D7, EP}, 2 },
548{ "sst.h", one (0x0480), one (0x0780), {R2, D8_7, EP}, 2 },
549{ "sst.w", one (0x0501), one (0x0781), {R2, D8_6, EP}, 2 },
550
551/* start-sanitize-v850eq */
552{ "pushml", two (0x07e0, 0x0001), two (0xfff0, 0x0007), {LIST18_L}, 0 },
553{ "pushmh", two (0x07e0, 0x0003), two (0xfff0, 0x0007), {LIST18_H}, 0 },
554{ "popml", two (0x07f0, 0x0001), two (0xfff0, 0x0007), {LIST18_L}, 0 },
555{ "popmh", two (0x07f0, 0x0003), two (0xfff0, 0x0007), {LIST18_H}, 0 },
556/* end-sanitize-v850e */
557
558/* start-sanitize-v850e */
559{ "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0 },
560{ "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0 },
561{ "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0 },
562{ "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0 },
563{ "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0 },
564{ "dispose", one (0x0640), one (0xffc0), {IMM5, LIST12, R2DISPOSE},0 },
565{ "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0 },
566/* end-sanitize-v850e */
567
568{ "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 1 },
569{ "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1 },
570{ "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1 },
571/* start-sanitize-v850e */
572{ "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2}, 1 },
573{ "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1 },
574/* end-sanitize-v850e */
575{ "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 2 },
576{ "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2 },
577{ "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2 },
578
579/* start-sanitize-v850e */
580/* byte swap/extend instructions */
581{ "zxb", one (0x0080), one (0xffe0), {R1}, 0 },
582{ "zxh", one (0x00c0), one (0xffe0), {R1}, 0 },
583{ "sxb", one (0x00a0), one (0xffe0), {R1}, 0 },
584{ "sxh", one (0x00e0), one (0xffe0), {R1}, 0 },
585{ "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0 },
586{ "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0 },
587{ "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0 },
588
589/* jump table instructions */
590{ "switch", one (0x0040), one (0xffe0), {R1}, 1 },
591{ "callt", one (0x0200), one (0xffc0), {I6}, 0 },
592{ "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0 },
593/* end-sanitize-v850e */
6d1e1ee8
C		 594
595/* arithmetic operation instructions */
0c519399
NC		 596{ "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0 },
597/* start-sanitize-v850e */
598{ "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R2, R1, R3}, 0 },
599{ "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0 },
600/* end-sanitize-v850e */
601{ "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0 },
602/* start-sanitize-v850e */
603{ "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0 },
604/* end-sanitize-v850e */
605{ "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0 },
606
607/* start-sanitize-v850e */
608{ "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0 },
609{ "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0 },
610{ "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0 },
611{ "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0 },
612{ "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0 },
613/* end-sanitize-v850e */
614{ "divh", OP (0x02), OP_MASK, IF1, 0 },
615
616/* start-sanitize-v850eq */
617{ "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0 },
618{ "divhun", two (0x07e0, 0x0282), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0 },
619{ "divn", two (0x07e0, 0x02c0), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0 },
620{ "divun", two (0x07e0, 0x02c2), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0 },
621{ "sdivhn", two (0x07e0, 0x0180), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0 },
622{ "sdivhun", two (0x07e0, 0x0182), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0 },
623{ "sdivn", two (0x07e0, 0x01c0), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0 },
624{ "sdivun", two (0x07e0, 0x01c2), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0 },
625/* end-sanitize-v850eq */
626
627{ "nop", one (0x00), one (0xffff), {0}, 0 },
628{ "mov", OP (0x00), OP_MASK, IF1, 0 },
629{ "mov", OP (0x10), OP_MASK, IF2, 0 },
630/* start-sanitize-v850e */
631{ "mov", one (0x0620), one (0xffe0), {IMM32, R1}, 0 },
632/* end-sanitize-v850e */
633{ "movea", OP (0x31), OP_MASK, IF6, 0 },
634{ "movhi", OP (0x32), OP_MASK, IF6, 0 },
635{ "add", OP (0x0e), OP_MASK, IF1, 0 },
636{ "add", OP (0x12), OP_MASK, IF2, 0 },
637{ "addi", OP (0x30), OP_MASK, IF6, 0 },
638{ "sub", OP (0x0d), OP_MASK, IF1, 0 },
639{ "subr", OP (0x0c), OP_MASK, IF1, 0 },
640{ "mulh", OP (0x07), OP_MASK, IF1, 0 },
641{ "mulh", OP (0x17), OP_MASK, IF2, 0 },
642{ "mulhi", OP (0x37), OP_MASK, IF6, 0 },
643{ "cmp", OP (0x0f), OP_MASK, IF1, 0 },
644{ "cmp", OP (0x13), OP_MASK, IF2, 0 },
645
6d1e1ee8 646/* saturated operation instructions */
0c519399
NC		 647{ "satadd", OP (0x06), OP_MASK, IF1, 0 },
648{ "satadd", OP (0x11), OP_MASK, IF2, 0 },
649{ "satsub", OP (0x05), OP_MASK, IF1, 0 },
650{ "satsubi", OP (0x33), OP_MASK, IF6, 0 },
651{ "satsubr", OP (0x04), OP_MASK, IF1, 0 },
6d1e1ee8
C		 652
653/* logical operation instructions */
0c519399
NC		 654{ "tst", OP (0x0b), OP_MASK, IF1, 0 },
655{ "or", OP (0x08), OP_MASK, IF1, 0 },
656{ "ori", OP (0x34), OP_MASK, IF6U, 0 },
657{ "and", OP (0x0a), OP_MASK, IF1, 0 },
658{ "andi", OP (0x36), OP_MASK, IF6U, 0 },
659{ "xor", OP (0x09), OP_MASK, IF1, 0 },
660{ "xori", OP (0x35), OP_MASK, IF6U, 0 },
661{ "not", OP (0x01), OP_MASK, IF1, 0 },
662{ "sar", OP (0x15), OP_MASK, {I5U, R2}, 0 },
663{ "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0 },
664{ "shl", OP (0x16), OP_MASK, {I5U, R2}, 0 },
665{ "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0 },
666{ "shr", OP (0x14), OP_MASK, {I5U, R2}, 0 },
667{ "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0 },
668/* start-sanitize-v850e */
669{ "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0 },
670/* end-sanitize-v850e */
6d1e1ee8
C		 671
672/* branch instructions */
6bc33c7f 673 /* signed integer */
0c519399
NC		 674{ "bgt", BOP (0xf), BOP_MASK, IF3, 0 },
675{ "bge", BOP (0xe), BOP_MASK, IF3, 0 },
676{ "blt", BOP (0x6), BOP_MASK, IF3, 0 },
677{ "ble", BOP (0x7), BOP_MASK, IF3, 0 },
6bc33c7f 678 /* unsigned integer */
0c519399
NC		 679{ "bh", BOP (0xb), BOP_MASK, IF3, 0 },
680{ "bnh", BOP (0x3), BOP_MASK, IF3, 0 },
681{ "bl", BOP (0x1), BOP_MASK, IF3, 0 },
682{ "bnl", BOP (0x9), BOP_MASK, IF3, 0 },
6bc33c7f 683 /* common */
0c519399
NC		 684{ "be", BOP (0x2), BOP_MASK, IF3, 0 },
685{ "bne", BOP (0xa), BOP_MASK, IF3, 0 },
6bc33c7f 686 /* others */
0c519399
NC		 687{ "bv", BOP (0x0), BOP_MASK, IF3, 0 },
688{ "bnv", BOP (0x8), BOP_MASK, IF3, 0 },
689{ "bn", BOP (0x4), BOP_MASK, IF3, 0 },
690{ "bp", BOP (0xc), BOP_MASK, IF3, 0 },
691{ "bc", BOP (0x1), BOP_MASK, IF3, 0 },
692{ "bnc", BOP (0x9), BOP_MASK, IF3, 0 },
693{ "bz", BOP (0x2), BOP_MASK, IF3, 0 },
694{ "bnz", BOP (0xa), BOP_MASK, IF3, 0 },
695{ "br", BOP (0x5), BOP_MASK, IF3, 0 },
696{ "bsa", BOP (0xd), BOP_MASK, IF3, 0 },
09478dc3 697
244558e3
JL		 698/* Branch macros.
699
700 We use the short form in the opcode/mask fields. The assembler
701 will twiddle bits as necessary if the long form is needed. */
702
0f02ae6e 703 /* signed integer */
0c519399
NC		 704{ "jgt", BOP (0xf), BOP_MASK, IF3, 0 },
705{ "jge", BOP (0xe), BOP_MASK, IF3, 0 },
706{ "jlt", BOP (0x6), BOP_MASK, IF3, 0 },
707{ "jle", BOP (0x7), BOP_MASK, IF3, 0 },
0f02ae6e 708 /* unsigned integer */
0c519399
NC		 709{ "jh", BOP (0xb), BOP_MASK, IF3, 0 },
710{ "jnh", BOP (0x3), BOP_MASK, IF3, 0 },
711{ "jl", BOP (0x1), BOP_MASK, IF3, 0 },
712{ "jnl", BOP (0x9), BOP_MASK, IF3, 0 },
0f02ae6e 713 /* common */
0c519399
NC		 714{ "je", BOP (0x2), BOP_MASK, IF3, 0 },
715{ "jne", BOP (0xa), BOP_MASK, IF3, 0 },
0f02ae6e 716 /* others */
0c519399
NC		 717{ "jv", BOP (0x0), BOP_MASK, IF3, 0 },
718{ "jnv", BOP (0x8), BOP_MASK, IF3, 0 },
719{ "jn", BOP (0x4), BOP_MASK, IF3, 0 },
720{ "jp", BOP (0xc), BOP_MASK, IF3, 0 },
721{ "jc", BOP (0x1), BOP_MASK, IF3, 0 },
722{ "jnc", BOP (0x9), BOP_MASK, IF3, 0 },
723{ "jz", BOP (0x2), BOP_MASK, IF3, 0 },
724{ "jnz", BOP (0xa), BOP_MASK, IF3, 0 },
725{ "jsa", BOP (0xd), BOP_MASK, IF3, 0 },
726{ "jbr", BOP (0x5), BOP_MASK, IF3, 0 },
727
728{ "jr", one (0x0780), two (0xffc0, 0x0001), {D22}, 0 },
729{ "jarl", one (0x0780), two (0x07c0, 0x0001), {D22, R2}, 0 },
6d1e1ee8 730
6d1e1ee8 731/* bit manipulation instructions */
0c519399
NC		 732{ "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2 },
733/* start-sanitize-v850e */
734{ "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 2 },
735/* end-sanitize-v850e */
736{ "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2 },
737/* start-sanitize-v850e */
738{ "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 2 },
739/* end-sanitize-v850e */
740{ "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2 },
741/* start-sanitize-v850e */
742{ "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 2 },
743/* end-sanitize-v850e */
744{ "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2 },
745/* start-sanitize-v850e */
746{ "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 2 },
747/* end-sanitize-v850e */
6d1e1ee8
C		 748
749/* special instructions */
0c519399
NC		 750{ "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0 },
751{ "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0 },
752{ "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0 },
753{ "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0 },
754{ "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0 },
755{ "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0xffff), {R1, SR2}, 0 },
756{ "stsr", two (0x07e0, 0x0040), two (0x07e0, 0xffff), {SR1, R2}, 0 },
e7dd7775 757{ 0, 0, 0, {0}, 0 },
6d1e1ee8
C		 758
759} ;
760
761const int v850_num_opcodes =
762 sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
763
GDB Binutils - Deliverables
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