[deliverable/binutils-gdb.git] / opcodes / v850-opc.c

#include "ansidecl.h"
#include "opcode/v850.h"

/* Local insertion and extraction functions.  */
static unsigned long insert_d9 PARAMS ((unsigned long, long, const char **));
static long extract_d9 PARAMS ((unsigned long, int *));

/* regular opcode */
#define OP(x)		((x & 0x3f) << 5)
#define OP_MASK		OP(0x3f)

/* conditional branch opcode */
#define BOP(x)		((0x0b << 7) | (x & 0x0f))
#define BOP_MASK	((0x0b << 7) | 0x0f)

/* one-word opcodes */
#define one(x)		((unsigned int) (x))

/* two-word opcodes */
#define two(x,y)	((unsigned int) (y) | ((unsigned int) (x) << 16))


\f
const struct v850_operand v850_operands[] = {
#define UNUSED	0
  { 0, 0, 0, 0, 0 }, 

/* The R1 field in a format 1, 6, 7, or 9 insn. */
#define R1	(UNUSED+1)
  { 5, 0, 0, 0, V850_OPERAND_REG }, 

/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
#define R2	(R1+1)
  { 5, 11, 0, 0, V850_OPERAND_REG },

/* The IMM5 field in a format 2 insn. */
#define I5	(R2+1)
  { 5, 0, 0, 0, V850_OPERAND_SIGNED }, 

#define I5U	(I5+1)
  { 5, 0, 0, 0, 0 },

/* The IMM16 field in a format 6 insn. */
#define I16	(I5U+1)
  { 16, 0, 0, 0, 0 }, 

/* The DISP6 field in a format 4 insn. */
#define D6	(I16+1)
  { 6, 1, 0, 0, 0 },

/* The DISP9 field in a format 3 insn. */
#define D9	(D6+1)
  { 0, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED },

/* The DISP16 field in a format 6 insn. */
#define D16	(D9+1)
  { 16, 0, 0, 0, V850_OPERAND_SIGNED }, 

/* The DISP22 field in a format 4 insn. */
#define D22	(D16+1)
  { 16, 0, 0, 0, 0 },

#define B3	(D22+1)
/* The 3 bit immediate field in format 8 insn.  */
  { 3, 11, 0, 0, 0 },

#define CCCC	(B3+1)
/* The 4 bit condition code in a setf instruction */
  { 4, 0, 0, 0, V850_OPERAND_CC }
} ; 

\f
/* reg-reg instruction format (Format I) */
#define IF1	{R1, R2}

/* imm-reg instruction format (Format II) */
#define IF2	{I5, R2}

/* conditional branch instruction format (Format III) */
#define IF3	{D9}

/* 16-bit load/store instruction (Format IV) */
#define IF4A	{D6, R2}
#define IF4B	{R2, D6}

/* Jump instruction (Format V) */
#define IF5	{D22}

/* 3 operand instruction (Format VI) */
#define IF6	{I16, R1, R2}

/* 32-bit load/store instruction (Format VII) */
#define IF7A	{D16, R1, R2}
#define IF7B	{R2, D16, R1}

/* Bit manipulation function.  */


\f
/* The opcode table.

   The format of the opcode table is:

   NAME		OPCODE		MASK		{ OPERANDS }

   NAME is the name of the instruction.
   OPCODE is the instruction opcode.
   MASK is the opcode mask; this is used to tell the disassembler
     which bits in the actual opcode must match OPCODE.
   OPERANDS is the list of operands.

   The disassembler reads the table in order and prints the first
   instruction which matches, so this table is sorted to put more
   specific instructions before more general instructions.  It is also
   sorted by major opcode.  */

const struct v850_opcode v850_opcodes[] = {
/* load/store instructions */
{ "sld.b",	OP(0x00),		OP_MASK,	IF4A },
{ "sld.h",	OP(0x00),		OP_MASK,	IF4A },
{ "sld.w",	OP(0x00),		OP_MASK,	IF4A },
{ "sst.b",	OP(0x00),		OP_MASK,	IF4B },
{ "sst.h",	OP(0x00),		OP_MASK,	IF4B },
{ "sst.w",	OP(0x00),		OP_MASK,	IF4B },

{ "ld.b",	OP(0x00),		OP_MASK,	IF7A },
{ "ld.h",	OP(0x00),		OP_MASK,	IF7A },
{ "ld.w",	OP(0x00),		OP_MASK,	IF7A },
{ "st.b",	OP(0x00),		OP_MASK,	IF7B },
{ "st.h",	OP(0x00),		OP_MASK,	IF7B },
{ "st.w",	OP(0x00),		OP_MASK,	IF7B },

/* arithmetic operation instructions */
{ "mov",        OP(0x00),		OP_MASK,	IF1 },
{ "mov",	OP(0x08),		OP_MASK,	IF2 },
{ "movea",	OP(0x31),		OP_MASK,	IF6 },
{ "movhi",	OP(0x31),		OP_MASK,	IF6 },
{ "add",	OP(0x0e),		OP_MASK,	IF1 },
{ "add",	OP(0x12),		OP_MASK,	IF2 },
{ "addi",	OP(0x30),		OP_MASK,	IF6 },
{ "sub",	OP(0x0d),		OP_MASK,	IF1 },
{ "subr", 	OP(0x0c),		OP_MASK,	IF1 },
{ "mulh",	OP(0x07),		OP_MASK,	IF1 },
{ "mulh",	OP(0x17),		OP_MASK,	IF2 },
{ "mulhi",	OP(0x37),		OP_MASK,	IF6 },
{ "divh",	OP(0x02),		OP_MASK,	IF1 },
{ "cmp",	OP(0x0f),		OP_MASK,	IF1 },
{ "cmp",	OP(0x13),		OP_MASK,	IF2 },
{ "setf",	two(0x0000,0x0000),	two(0x0000,0xffff), {CCCC,R2} },

/* saturated operation instructions */
{ "satadd",	OP(0x06),		OP_MASK,	IF1 },
{ "satadd",	OP(0x11),		OP_MASK,	IF2 },
{ "satsub",	OP(0x05),		OP_MASK,	IF1 },
{ "satsubi",	OP(0x33),		OP_MASK,	IF6 },
{ "satsubr",	OP(0x04),		OP_MASK,	IF1 },

/* logical operation instructions */
{ "tst",	OP(0x0b),		OP_MASK,	IF1 },
{ "or",		OP(0x08),		OP_MASK,	IF1 },
{ "ori",	OP(0x34),		OP_MASK,	IF6 },
{ "and",	OP(0x0a),		OP_MASK,	IF1 },
{ "andi",	OP(0x36),		OP_MASK,	IF6 },
{ "xor",	OP(0x09),		OP_MASK,	IF1 },
{ "xori",	OP(0x35),		OP_MASK,	IF6 },
{ "not",	OP(0x01),		OP_MASK,	IF1 },
{ "sar",	OP(0x15),		OP_MASK,	{I5U, R2} },
{ "sar",	two(0x07e0,0x00a0),	two(0x07e0,0xffff),	{R1,R2} },
{ "shl",	OP(0x16),		OP_MASK,		{I5U, R2} },
{ "shl",	two(0x07e0,0x00c0),	two(0x07e0,0xffff),	{R1,R2} },
{ "shr",	OP(0x14),		OP_MASK,		{I5U, R2} },
{ "shr",	two(0x07e0,0x0080),	two(0x07e0,0xffff),	{R1,R2} },

/* branch instructions */
	/* signed integer */
{ "bgt",	BOP(0xf),		BOP_MASK,	IF3 },
{ "bge",	BOP(0xe),		BOP_MASK,	IF3 },
{ "blt",	BOP(0x6),		BOP_MASK,	IF3 },
{ "ble",	BOP(0x7),		BOP_MASK,	IF3 },
	/* unsigned integer */
{ "bh",		BOP(0xb),		BOP_MASK,	IF3 },
{ "bnh",	BOP(0x3),		BOP_MASK,	IF3 },
{ "bl",		BOP(0x1),		BOP_MASK,	IF3 },
{ "bnl",	BOP(0x9),		BOP_MASK,	IF3 },
	/* common */
{ "be",		BOP(0x2),		BOP_MASK,	IF3 },
{ "bne",	BOP(0xa),		BOP_MASK,	IF3 },
	/* others */
{ "bv",		BOP(0x0),		BOP_MASK,	IF3 },
{ "bnv",	BOP(0x8),		BOP_MASK,	IF3 },
{ "bn",		BOP(0x4),		BOP_MASK,	IF3 },
{ "bp",		BOP(0xc),		BOP_MASK,	IF3 },
{ "bc",		BOP(0x1),		BOP_MASK,	IF3 },
{ "bnc",	BOP(0x9),		BOP_MASK,	IF3 },
{ "bz",		BOP(0x2),		BOP_MASK,	IF3 },
{ "bnz",	BOP(0xa),		BOP_MASK,	IF3 },
{ "br",		BOP(0x5),		BOP_MASK,	IF3 },
{ "bsa",	BOP(0xd),		BOP_MASK,	IF3 },

{ "jmp",	one(0x0060),		one(0xffe0),	R1 },
{ "jarl",	one(0x0780),		one(0xf83f),	{ D22, R2 } }, 
{ "jr",		one(0x0780),		one(0xffe0),	{ D22 } },

/* bit manipulation instructions */
{ "set1",	two(0x07c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1} },
{ "not1",	two(0x47c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1} },
{ "clr1",	two(0x87c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1} },
{ "tst1",	two(0xc7c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1} },

/* special instructions */
{ "di",		two(0x07e0,0x0160),	two(0xffff,0xffff),	{0} },
{ "ei",		two(0x87e0,0x0160),	two(0xffff,0xffff),	{0} },
{ "halt",	two(0x07e0,0x0120),	two(0xffff,0xffff),	{0} },
{ "reti",	two(0x07e0,0x0140),	two(0xffff,0xffff),	{0} },
{ "trap",	two(0x07e0,0x0100),	two(0xffe0,0xffff),	{I5} },
{ "ldsr",	two(0x07e0,0x0020),	two(0x07e0,0xffff),	{0} },
{ "stsr",	two(0x07e0,0x0040),	two(0x07e0,0xffff),	{0} },
{ "nop",	one(0x00),		one(0xff),		{0} },

} ;

const int v850_num_opcodes =
  sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);

\f
/* The functions used to insert and extract complicated operands.  */

static unsigned long
insert_d9 (insn, value, errmsg)
     unsigned long insn;
     long value;
     const char **errmsg;
{
  if (value > 511 || value <= -512)
    *errmsg = "value out of range";

  return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
}

static long
extract_d9 (insn, invalid)
     unsigned long insn;
     int *invalid;
{
  long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);

  if ((insn & 0x8000) != 0)
    ret -= 0x0200;

  return ret;
}
Commit	Line	Data
6d1e1ee8 C	1	#include "ansidecl.h"
	2	#include "opcode/v850.h"
	3
4f235110 C	4	/* Local insertion and extraction functions. */
	5	static unsigned long insert_d9 PARAMS ((unsigned long, long, const char **));
	6	static long extract_d9 PARAMS ((unsigned long, int *));
	7
6d1e1ee8 C	8	/* regular opcode */
	9	#define OP(x) ((x & 0x3f) << 5)
	10	#define OP_MASK OP(0x3f)
	11
	12	/* conditional branch opcode */
	13	#define BOP(x) ((0x0b << 7) \| (x & 0x0f))
	14	#define BOP_MASK ((0x0b << 7) \| 0x0f)
	15
	16	/* one-word opcodes */
	17	#define one(x) ((unsigned int) (x))
	18
	19	/* two-word opcodes */
	20	#define two(x,y) ((unsigned int) (y) \| ((unsigned int) (x) << 16))
	21
	22
	23	\f
	24	const struct v850_operand v850_operands[] = {
	25	#define UNUSED 0
69463cbb	26	{ 0, 0, 0, 0, 0 },
6d1e1ee8 C	27
	28	/* The R1 field in a format 1, 6, 7, or 9 insn. */
	29	#define R1 (UNUSED+1)
69463cbb	30	{ 5, 0, 0, 0, V850_OPERAND_REG },
6d1e1ee8 C	31
	32	/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
	33	#define R2 (R1+1)
69463cbb	34	{ 5, 11, 0, 0, V850_OPERAND_REG },
6d1e1ee8 C	35
	36	/* The IMM5 field in a format 2 insn. */
	37	#define I5 (R2+1)
dbc6a8f6 C	38	{ 5, 0, 0, 0, V850_OPERAND_SIGNED },
	39
	40	#define I5U (I5+1)
	41	{ 5, 0, 0, 0, 0 },
6d1e1ee8	42
4f235110	43	/* The IMM16 field in a format 6 insn. */
dbc6a8f6	44	#define I16 (I5U+1)
69463cbb	45	{ 16, 0, 0, 0, 0 },
6d1e1ee8 C	46
	47	/* The DISP6 field in a format 4 insn. */
	48	#define D6 (I16+1)
69463cbb	49	{ 6, 1, 0, 0, 0 },
6d1e1ee8	50
4f235110 C	51	/* The DISP9 field in a format 3 insn. */
4f235110 C	52	#define D9 (D6+1)
dbc6a8f6	53	{ 0, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED },
6d1e1ee8 C	54
6d1e1ee8 C	55	/* The DISP16 field in a format 6 insn. */
4f235110	56	#define D16 (D9+1)
dbc6a8f6	57	{ 16, 0, 0, 0, V850_OPERAND_SIGNED },
6d1e1ee8 C	58
	59	/* The DISP22 field in a format 4 insn. */
	60	#define D22 (D16+1)
69463cbb	61	{ 16, 0, 0, 0, 0 },
7c8157dd JL	62
	63	#define B3 (D22+1)
	64	/* The 3 bit immediate field in format 8 insn. */
3c72ab70	65	{ 3, 11, 0, 0, 0 },
69463cbb C	66
	67	#define CCCC (B3+1)
	68	/* The 4 bit condition code in a setf instruction */
	69	{ 4, 0, 0, 0, V850_OPERAND_CC }
6d1e1ee8 C	70	} ;
	71
	72	\f
	73	/* reg-reg instruction format (Format I) */
	74	#define IF1 {R1, R2}
	75
	76	/* imm-reg instruction format (Format II) */
	77	#define IF2 {I5, R2}
	78
	79	/* conditional branch instruction format (Format III) */
4f235110	80	#define IF3 {D9}
6d1e1ee8 C	81
6d1e1ee8 C	82	/* 16-bit load/store instruction (Format IV) */
e89a42c1 C	83	#define IF4A {D6, R2}
e89a42c1 C	84	#define IF4B {R2, D6}
6d1e1ee8 C	85
	86	/* Jump instruction (Format V) */
	87	#define IF5 {D22}
	88
	89	/* 3 operand instruction (Format VI) */
e89a42c1	90	#define IF6 {I16, R1, R2}
6d1e1ee8 C	91
6d1e1ee8 C	92	/* 32-bit load/store instruction (Format VII) */
e89a42c1 C	93	#define IF7A {D16, R1, R2}
e89a42c1 C	94	#define IF7B {R2, D16, R1}
6d1e1ee8	95
b10e29f4	96	/* Bit manipulation function. */
6d1e1ee8 C	97
	98
	99	\f
	100	/* The opcode table.
	101
	102	The format of the opcode table is:
	103
	104	NAME OPCODE MASK { OPERANDS }
	105
	106	NAME is the name of the instruction.
	107	OPCODE is the instruction opcode.
	108	MASK is the opcode mask; this is used to tell the disassembler
	109	which bits in the actual opcode must match OPCODE.
	110	OPERANDS is the list of operands.
	111
	112	The disassembler reads the table in order and prints the first
	113	instruction which matches, so this table is sorted to put more
	114	specific instructions before more general instructions. It is also
	115	sorted by major opcode. */
	116
	117	const struct v850_opcode v850_opcodes[] = {
	118	/* load/store instructions */
e89a42c1 C	119	{ "sld.b", OP(0x00), OP_MASK, IF4A },
	120	{ "sld.h", OP(0x00), OP_MASK, IF4A },
	121	{ "sld.w", OP(0x00), OP_MASK, IF4A },
	122	{ "sst.b", OP(0x00), OP_MASK, IF4B },
cc6e50b5	123	{ "sst.h", OP(0x00), OP_MASK, IF4B },
e89a42c1	124	{ "sst.w", OP(0x00), OP_MASK, IF4B },
e89a42c1 C	125
	126	{ "ld.b", OP(0x00), OP_MASK, IF7A },
	127	{ "ld.h", OP(0x00), OP_MASK, IF7A },
	128	{ "ld.w", OP(0x00), OP_MASK, IF7A },
	129	{ "st.b", OP(0x00), OP_MASK, IF7B },
	130	{ "st.h", OP(0x00), OP_MASK, IF7B },
	131	{ "st.w", OP(0x00), OP_MASK, IF7B },
6d1e1ee8 C	132
6d1e1ee8 C	133	/* arithmetic operation instructions */
6bc33c7f C	134	{ "mov", OP(0x00), OP_MASK, IF1 },
	135	{ "mov", OP(0x08), OP_MASK, IF2 },
	136	{ "movea", OP(0x31), OP_MASK, IF6 },
	137	{ "movhi", OP(0x31), OP_MASK, IF6 },
6d1e1ee8 C	138	{ "add", OP(0x0e), OP_MASK, IF1 },
	139	{ "add", OP(0x12), OP_MASK, IF2 },
	140	{ "addi", OP(0x30), OP_MASK, IF6 },
	141	{ "sub", OP(0x0d), OP_MASK, IF1 },
	142	{ "subr", OP(0x0c), OP_MASK, IF1 },
	143	{ "mulh", OP(0x07), OP_MASK, IF1 },
	144	{ "mulh", OP(0x17), OP_MASK, IF2 },
	145	{ "mulhi", OP(0x37), OP_MASK, IF6 },
	146	{ "divh", OP(0x02), OP_MASK, IF1 },
	147	{ "cmp", OP(0x0f), OP_MASK, IF1 },
	148	{ "cmp", OP(0x13), OP_MASK, IF2 },
69463cbb	149	{ "setf", two(0x0000,0x0000), two(0x0000,0xffff), {CCCC,R2} },
6d1e1ee8 C	150
	151	/* saturated operation instructions */
	152	{ "satadd", OP(0x06), OP_MASK, IF1 },
	153	{ "satadd", OP(0x11), OP_MASK, IF2 },
	154	{ "satsub", OP(0x05), OP_MASK, IF1 },
	155	{ "satsubi", OP(0x33), OP_MASK, IF6 },
	156	{ "satsubr", OP(0x04), OP_MASK, IF1 },
	157
	158	/* logical operation instructions */
	159	{ "tst", OP(0x0b), OP_MASK, IF1 },
	160	{ "or", OP(0x08), OP_MASK, IF1 },
	161	{ "ori", OP(0x34), OP_MASK, IF6 },
	162	{ "and", OP(0x0a), OP_MASK, IF1 },
	163	{ "andi", OP(0x36), OP_MASK, IF6 },
	164	{ "xor", OP(0x09), OP_MASK, IF1 },
	165	{ "xori", OP(0x35), OP_MASK, IF6 },
	166	{ "not", OP(0x01), OP_MASK, IF1 },
dbc6a8f6	167	{ "sar", OP(0x15), OP_MASK, {I5U, R2} },
6d1e1ee8	168	{ "sar", two(0x07e0,0x00a0), two(0x07e0,0xffff), {R1,R2} },
dbc6a8f6	169	{ "shl", OP(0x16), OP_MASK, {I5U, R2} },
6d1e1ee8	170	{ "shl", two(0x07e0,0x00c0), two(0x07e0,0xffff), {R1,R2} },
dbc6a8f6	171	{ "shr", OP(0x14), OP_MASK, {I5U, R2} },
6d1e1ee8 C	172	{ "shr", two(0x07e0,0x0080), two(0x07e0,0xffff), {R1,R2} },
	173
	174	/* branch instructions */
6bc33c7f C	175	/* signed integer */
	176	{ "bgt", BOP(0xf), BOP_MASK, IF3 },
	177	{ "bge", BOP(0xe), BOP_MASK, IF3 },
	178	{ "blt", BOP(0x6), BOP_MASK, IF3 },
	179	{ "ble", BOP(0x7), BOP_MASK, IF3 },
	180	/* unsigned integer */
	181	{ "bh", BOP(0xb), BOP_MASK, IF3 },
	182	{ "bnh", BOP(0x3), BOP_MASK, IF3 },
6d1e1ee8	183	{ "bl", BOP(0x1), BOP_MASK, IF3 },
6d1e1ee8	184	{ "bnl", BOP(0x9), BOP_MASK, IF3 },
6bc33c7f	185	/* common */
6d1e1ee8	186	{ "be", BOP(0x2), BOP_MASK, IF3 },
6d1e1ee8	187	{ "bne", BOP(0xa), BOP_MASK, IF3 },
6bc33c7f C	188	/* others */
	189	{ "bv", BOP(0x0), BOP_MASK, IF3 },
	190	{ "bnv", BOP(0x8), BOP_MASK, IF3 },
6d1e1ee8 C	191	{ "bn", BOP(0x4), BOP_MASK, IF3 },
6d1e1ee8 C	192	{ "bp", BOP(0xc), BOP_MASK, IF3 },
6bc33c7f C	193	{ "bc", BOP(0x1), BOP_MASK, IF3 },
	194	{ "bnc", BOP(0x9), BOP_MASK, IF3 },
	195	{ "bz", BOP(0x2), BOP_MASK, IF3 },
	196	{ "bnz", BOP(0xa), BOP_MASK, IF3 },
	197	{ "br", BOP(0x5), BOP_MASK, IF3 },
6d1e1ee8	198	{ "bsa", BOP(0xd), BOP_MASK, IF3 },
6d1e1ee8	199
fed1d21f	200	{ "jmp", one(0x0060), one(0xffe0), R1 },
e89a42c1	201	{ "jarl", one(0x0780), one(0xf83f), { D22, R2 } },
6d1e1ee8 C	202	{ "jr", one(0x0780), one(0xffe0), { D22 } },
6d1e1ee8 C	203
6d1e1ee8	204	/* bit manipulation instructions */
0bdf3144 JL	205	{ "set1", two(0x07c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
	206	{ "not1", two(0x47c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
	207	{ "clr1", two(0x87c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
	208	{ "tst1", two(0xc7c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
6d1e1ee8 C	209
	210	/* special instructions */
	211	{ "di", two(0x07e0,0x0160), two(0xffff,0xffff), {0} },
	212	{ "ei", two(0x87e0,0x0160), two(0xffff,0xffff), {0} },
	213	{ "halt", two(0x07e0,0x0120), two(0xffff,0xffff), {0} },
	214	{ "reti", two(0x07e0,0x0140), two(0xffff,0xffff), {0} },
6d1e1ee8	215	{ "trap", two(0x07e0,0x0100), two(0xffe0,0xffff), {I5} },
6d1e1ee8 C	216	{ "ldsr", two(0x07e0,0x0020), two(0x07e0,0xffff), {0} },
	217	{ "stsr", two(0x07e0,0x0040), two(0x07e0,0xffff), {0} },
	218	{ "nop", one(0x00), one(0xff), {0} },
	219
	220	} ;
	221
	222	const int v850_num_opcodes =
	223	sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
	224
4f235110 C	225	\f
	226	/* The functions used to insert and extract complicated operands. */
	227
	228	static unsigned long
	229	insert_d9 (insn, value, errmsg)
	230	unsigned long insn;
	231	long value;
	232	const char **errmsg;
	233	{
	234	if (value > 511 \|\| value <= -512)
	235	*errmsg = "value out of range";
	236
	237	return (insn \| ((value & 0x1f0) << 7) \| ((value & 0x0e) << 3));
	238	}
	239
	240	static long
	241	extract_d9 (insn, invalid)
	242	unsigned long insn;
	243	int *invalid;
	244	{
	245	long ret = ((insn & 0xf800) >> 7) \| ((insn & 0x0070) >> 3);
	246
	247	if ((insn & 0x8000) != 0)
	248	ret -= 0x0200;
	249
	250	return ret;
	251	}