[deliverable/binutils-gdb.git] / opcodes / v850-opc.c

#include "ansidecl.h"
#include "opcode/v850.h"

/* Local insertion and extraction functions.  */
static unsigned long insert_d9 PARAMS ((unsigned long, long, const char **));
static long extract_d9 PARAMS ((unsigned long, int *));

/* regular opcode */
#define OP(x)		((x & 0x3f) << 5)
#define OP_MASK		OP(0x3f)

/* conditional branch opcode */
#define BOP(x)		((0x0b << 7) | (x & 0x0f))
#define BOP_MASK	((0x0b << 7) | 0x0f)

/* one-word opcodes */
#define one(x)		((unsigned int) (x))

/* two-word opcodes */
#define two(x,y)	((unsigned int) (y) | ((unsigned int) (x) << 16))


\f
const struct v850_operand v850_operands[] = {
#define UNUSED	0
  { 0, 0, 0, 0, 0 }, 

/* The R1 field in a format 1, 6, 7, or 9 insn. */
#define R1	(UNUSED+1)
  { 5, 0, 0, 0, V850_OPERAND_REG }, 

/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
#define R2	(R1+1)
  { 5, 11, 0, 0, V850_OPERAND_REG },

/* The IMM5 field in a format 2 insn. */
#define I5	(R2+1)
  { 5, 0, 0, 0, 0 }, 

/* The IMM16 field in a format 6 insn. */
#define I16	(I5+1)
  { 16, 0, 0, 0, 0 }, 

/* The DISP6 field in a format 4 insn. */
#define D6	(I16+1)
  { 6, 1, 0, 0, 0 },

/* The DISP9 field in a format 3 insn. */
#define D9	(D6+1)
  { 0, 0, insert_d9, extract_d9, 0 },

/* The DISP16 field in a format 6 insn. */
#define D16	(D9+1)
  { 16, 0, 0, 0, 0 }, 

/* The DISP22 field in a format 4 insn. */
#define D22	(D16+1)
  { 16, 0, 0, 0, 0 },

#define B3	(D22+1)
/* The 3 bit immediate field in format 8 insn.  */
  { 3, 11, 0, 0, 0 },

#define CCCC	(B3+1)
/* The 4 bit condition code in a setf instruction */
  { 4, 0, 0, 0, V850_OPERAND_CC }
} ; 

\f
/* reg-reg instruction format (Format I) */
#define IF1	{R1, R2}

/* imm-reg instruction format (Format II) */
#define IF2	{I5, R2}

/* conditional branch instruction format (Format III) */
#define IF3	{D9}

/* 16-bit load/store instruction (Format IV) */
#define IF4A	{D6, R2}
#define IF4B	{R2, D6}

/* Jump instruction (Format V) */
#define IF5	{D22}

/* 3 operand instruction (Format VI) */
#define IF6	{I16, R1, R2}

/* 32-bit load/store instruction (Format VII) */
#define IF7A	{D16, R1, R2}
#define IF7B	{R2, D16, R1}

/* Bit manipulation function.  */


\f
/* The opcode table.

   The format of the opcode table is:

   NAME		OPCODE		MASK		{ OPERANDS }

   NAME is the name of the instruction.
   OPCODE is the instruction opcode.
   MASK is the opcode mask; this is used to tell the disassembler
     which bits in the actual opcode must match OPCODE.
   OPERANDS is the list of operands.

   The disassembler reads the table in order and prints the first
   instruction which matches, so this table is sorted to put more
   specific instructions before more general instructions.  It is also
   sorted by major opcode.  */

const struct v850_opcode v850_opcodes[] = {
/* load/store instructions */
{ "sld.b",	OP(0x00),		OP_MASK,	IF4A },
{ "sld.h",	OP(0x00),		OP_MASK,	IF4A },
{ "sld.w",	OP(0x00),		OP_MASK,	IF4A },
{ "sst.b",	OP(0x00),		OP_MASK,	IF4B },
{ "sst.w",	OP(0x00),		OP_MASK,	IF4B },
{ "sst.l",	OP(0x00),		OP_MASK,	IF4B },

{ "ld.b",	OP(0x00),		OP_MASK,	IF7A },
{ "ld.h",	OP(0x00),		OP_MASK,	IF7A },
{ "ld.w",	OP(0x00),		OP_MASK,	IF7A },
{ "st.b",	OP(0x00),		OP_MASK,	IF7B },
{ "st.h",	OP(0x00),		OP_MASK,	IF7B },
{ "st.w",	OP(0x00),		OP_MASK,	IF7B },

/* arithmetic operation instructions */
{ "mov",        OP(0x00),		OP_MASK,	IF1 },
{ "mov",	OP(0x08),		OP_MASK,	IF2 },
{ "movea",	OP(0x31),		OP_MASK,	IF6 },
{ "movhi",	OP(0x31),		OP_MASK,	IF6 },
{ "add",	OP(0x0e),		OP_MASK,	IF1 },
{ "add",	OP(0x12),		OP_MASK,	IF2 },
{ "addi",	OP(0x30),		OP_MASK,	IF6 },
{ "sub",	OP(0x0d),		OP_MASK,	IF1 },
{ "subr", 	OP(0x0c),		OP_MASK,	IF1 },
{ "mulh",	OP(0x07),		OP_MASK,	IF1 },
{ "mulh",	OP(0x17),		OP_MASK,	IF2 },
{ "mulhi",	OP(0x37),		OP_MASK,	IF6 },
{ "divh",	OP(0x02),		OP_MASK,	IF1 },
{ "cmp",	OP(0x0f),		OP_MASK,	IF1 },
{ "cmp",	OP(0x13),		OP_MASK,	IF2 },
{ "setf",	two(0x0000,0x0000),	two(0x0000,0xffff), {CCCC,R2} },

/* saturated operation instructions */
{ "satadd",	OP(0x06),		OP_MASK,	IF1 },
{ "satadd",	OP(0x11),		OP_MASK,	IF2 },
{ "satsub",	OP(0x05),		OP_MASK,	IF1 },
{ "satsubi",	OP(0x33),		OP_MASK,	IF6 },
{ "satsubr",	OP(0x04),		OP_MASK,	IF1 },

/* logical operation instructions */
{ "tst",	OP(0x0b),		OP_MASK,	IF1 },
{ "or",		OP(0x08),		OP_MASK,	IF1 },
{ "ori",	OP(0x34),		OP_MASK,	IF6 },
{ "and",	OP(0x0a),		OP_MASK,	IF1 },
{ "andi",	OP(0x36),		OP_MASK,	IF6 },
{ "xor",	OP(0x09),		OP_MASK,	IF1 },
{ "xori",	OP(0x35),		OP_MASK,	IF6 },
{ "not",	OP(0x01),		OP_MASK,	IF1 },
{ "sar",	OP(0x15),		OP_MASK,	IF2 },
{ "sar",	two(0x07e0,0x00a0),	two(0x07e0,0xffff),	{R1,R2} },
{ "shl",	OP(0x16),		OP_MASK,		IF2 },
{ "shl",	two(0x07e0,0x00c0),	two(0x07e0,0xffff),	{R1,R2} },
{ "shr",	OP(0x14),		OP_MASK,		IF2 },
{ "shr",	two(0x07e0,0x0080),	two(0x07e0,0xffff),	{R1,R2} },

/* branch instructions */
	/* signed integer */
{ "bgt",	BOP(0xf),		BOP_MASK,	IF3 },
{ "bge",	BOP(0xe),		BOP_MASK,	IF3 },
{ "blt",	BOP(0x6),		BOP_MASK,	IF3 },
{ "ble",	BOP(0x7),		BOP_MASK,	IF3 },
	/* unsigned integer */
{ "bh",		BOP(0xb),		BOP_MASK,	IF3 },
{ "bnh",	BOP(0x3),		BOP_MASK,	IF3 },
{ "bl",		BOP(0x1),		BOP_MASK,	IF3 },
{ "bnl",	BOP(0x9),		BOP_MASK,	IF3 },
	/* common */
{ "be",		BOP(0x2),		BOP_MASK,	IF3 },
{ "bne",	BOP(0xa),		BOP_MASK,	IF3 },
	/* others */
{ "bv",		BOP(0x0),		BOP_MASK,	IF3 },
{ "bnv",	BOP(0x8),		BOP_MASK,	IF3 },
{ "bn",		BOP(0x4),		BOP_MASK,	IF3 },
{ "bp",		BOP(0xc),		BOP_MASK,	IF3 },
{ "bc",		BOP(0x1),		BOP_MASK,	IF3 },
{ "bnc",	BOP(0x9),		BOP_MASK,	IF3 },
{ "bz",		BOP(0x2),		BOP_MASK,	IF3 },
{ "bnz",	BOP(0xa),		BOP_MASK,	IF3 },
{ "br",		BOP(0x5),		BOP_MASK,	IF3 },
{ "bsa",	BOP(0xd),		BOP_MASK,	IF3 },

{ "jmp",	one(0x0060),		one(0xffe0),	R1 },
{ "jarl",	one(0x0780),		one(0xf83f),	{ D22, R2 } }, 
{ "jr",		one(0x0780),		one(0xffe0),	{ D22 } },

/* bit manipulation instructions */
{ "set1",	two(0x07c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1} },
{ "not1",	two(0x47c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1} },
{ "clr1",	two(0x87c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1} },
{ "tst1",	two(0xc7c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1} },

/* special instructions */
{ "di",		two(0x07e0,0x0160),	two(0xffff,0xffff),	{0} },
{ "ei",		two(0x87e0,0x0160),	two(0xffff,0xffff),	{0} },
{ "halt",	two(0x07e0,0x0120),	two(0xffff,0xffff),	{0} },
{ "reti",	two(0x07e0,0x0140),	two(0xffff,0xffff),	{0} },
{ "trap",	two(0x07e0,0x0100),	two(0xffe0,0xffff),	{I5} },
{ "ldsr",	two(0x07e0,0x0020),	two(0x07e0,0xffff),	{0} },
{ "stsr",	two(0x07e0,0x0040),	two(0x07e0,0xffff),	{0} },
{ "nop",	one(0x00),		one(0xff),		{0} },

} ;

const int v850_num_opcodes =
  sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);

\f
/* The functions used to insert and extract complicated operands.  */

static unsigned long
insert_d9 (insn, value, errmsg)
     unsigned long insn;
     long value;
     const char **errmsg;
{
  if (value > 511 || value <= -512)
    *errmsg = "value out of range";

  return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
}

static long
extract_d9 (insn, invalid)
     unsigned long insn;
     int *invalid;
{
  long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);

  if ((insn & 0x8000) != 0)
    ret -= 0x0200;

  return ret;
}
Commit	Line	Data
6d1e1ee8 C	1	#include "ansidecl.h"
	2	#include "opcode/v850.h"
	3
4f235110 C	4	/* Local insertion and extraction functions. */
	5	static unsigned long insert_d9 PARAMS ((unsigned long, long, const char **));
	6	static long extract_d9 PARAMS ((unsigned long, int *));
	7
6d1e1ee8 C	8	/* regular opcode */
	9	#define OP(x) ((x & 0x3f) << 5)
	10	#define OP_MASK OP(0x3f)
	11
	12	/* conditional branch opcode */
	13	#define BOP(x) ((0x0b << 7) \| (x & 0x0f))
	14	#define BOP_MASK ((0x0b << 7) \| 0x0f)
	15
	16	/* one-word opcodes */
	17	#define one(x) ((unsigned int) (x))
	18
	19	/* two-word opcodes */
	20	#define two(x,y) ((unsigned int) (y) \| ((unsigned int) (x) << 16))
	21
	22
	23	\f
	24	const struct v850_operand v850_operands[] = {
	25	#define UNUSED 0
69463cbb	26	{ 0, 0, 0, 0, 0 },
6d1e1ee8 C	27
	28	/* The R1 field in a format 1, 6, 7, or 9 insn. */
	29	#define R1 (UNUSED+1)
69463cbb	30	{ 5, 0, 0, 0, V850_OPERAND_REG },
6d1e1ee8 C	31
	32	/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
	33	#define R2 (R1+1)
69463cbb	34	{ 5, 11, 0, 0, V850_OPERAND_REG },
6d1e1ee8 C	35
	36	/* The IMM5 field in a format 2 insn. */
	37	#define I5 (R2+1)
69463cbb	38	{ 5, 0, 0, 0, 0 },
6d1e1ee8	39
4f235110	40	/* The IMM16 field in a format 6 insn. */
6d1e1ee8	41	#define I16 (I5+1)
69463cbb	42	{ 16, 0, 0, 0, 0 },
6d1e1ee8 C	43
	44	/* The DISP6 field in a format 4 insn. */
	45	#define D6 (I16+1)
69463cbb	46	{ 6, 1, 0, 0, 0 },
6d1e1ee8	47
4f235110 C	48	/* The DISP9 field in a format 3 insn. */
	49	#define D9 (D6+1)
	50	{ 0, 0, insert_d9, extract_d9, 0 },
6d1e1ee8 C	51
6d1e1ee8 C	52	/* The DISP16 field in a format 6 insn. */
4f235110	53	#define D16 (D9+1)
69463cbb	54	{ 16, 0, 0, 0, 0 },
6d1e1ee8 C	55
	56	/* The DISP22 field in a format 4 insn. */
	57	#define D22 (D16+1)
69463cbb	58	{ 16, 0, 0, 0, 0 },
7c8157dd JL	59
	60	#define B3 (D22+1)
	61	/* The 3 bit immediate field in format 8 insn. */
69463cbb C	62	{ 3, 11, 0, 0, 0 },
	63
	64	#define CCCC (B3+1)
	65	/* The 4 bit condition code in a setf instruction */
	66	{ 4, 0, 0, 0, V850_OPERAND_CC }
6d1e1ee8 C	67	} ;
	68
	69	\f
	70	/* reg-reg instruction format (Format I) */
	71	#define IF1 {R1, R2}
	72
	73	/* imm-reg instruction format (Format II) */
	74	#define IF2 {I5, R2}
	75
	76	/* conditional branch instruction format (Format III) */
4f235110	77	#define IF3 {D9}
6d1e1ee8 C	78
6d1e1ee8 C	79	/* 16-bit load/store instruction (Format IV) */
e89a42c1 C	80	#define IF4A {D6, R2}
e89a42c1 C	81	#define IF4B {R2, D6}
6d1e1ee8 C	82
	83	/* Jump instruction (Format V) */
	84	#define IF5 {D22}
	85
	86	/* 3 operand instruction (Format VI) */
e89a42c1	87	#define IF6 {I16, R1, R2}
6d1e1ee8 C	88
6d1e1ee8 C	89	/* 32-bit load/store instruction (Format VII) */
e89a42c1 C	90	#define IF7A {D16, R1, R2}
e89a42c1 C	91	#define IF7B {R2, D16, R1}
6d1e1ee8	92
b10e29f4	93	/* Bit manipulation function. */
6d1e1ee8 C	94
	95
	96	\f
	97	/* The opcode table.
	98
	99	The format of the opcode table is:
	100
	101	NAME OPCODE MASK { OPERANDS }
	102
	103	NAME is the name of the instruction.
	104	OPCODE is the instruction opcode.
	105	MASK is the opcode mask; this is used to tell the disassembler
	106	which bits in the actual opcode must match OPCODE.
	107	OPERANDS is the list of operands.
	108
	109	The disassembler reads the table in order and prints the first
	110	instruction which matches, so this table is sorted to put more
	111	specific instructions before more general instructions. It is also
	112	sorted by major opcode. */
	113
	114	const struct v850_opcode v850_opcodes[] = {
	115	/* load/store instructions */
e89a42c1 C	116	{ "sld.b", OP(0x00), OP_MASK, IF4A },
	117	{ "sld.h", OP(0x00), OP_MASK, IF4A },
	118	{ "sld.w", OP(0x00), OP_MASK, IF4A },
	119	{ "sst.b", OP(0x00), OP_MASK, IF4B },
	120	{ "sst.w", OP(0x00), OP_MASK, IF4B },
	121	{ "sst.l", OP(0x00), OP_MASK, IF4B },
	122
	123	{ "ld.b", OP(0x00), OP_MASK, IF7A },
	124	{ "ld.h", OP(0x00), OP_MASK, IF7A },
	125	{ "ld.w", OP(0x00), OP_MASK, IF7A },
	126	{ "st.b", OP(0x00), OP_MASK, IF7B },
	127	{ "st.h", OP(0x00), OP_MASK, IF7B },
	128	{ "st.w", OP(0x00), OP_MASK, IF7B },
6d1e1ee8 C	129
6d1e1ee8 C	130	/* arithmetic operation instructions */
6bc33c7f C	131	{ "mov", OP(0x00), OP_MASK, IF1 },
	132	{ "mov", OP(0x08), OP_MASK, IF2 },
	133	{ "movea", OP(0x31), OP_MASK, IF6 },
	134	{ "movhi", OP(0x31), OP_MASK, IF6 },
6d1e1ee8 C	135	{ "add", OP(0x0e), OP_MASK, IF1 },
	136	{ "add", OP(0x12), OP_MASK, IF2 },
	137	{ "addi", OP(0x30), OP_MASK, IF6 },
	138	{ "sub", OP(0x0d), OP_MASK, IF1 },
	139	{ "subr", OP(0x0c), OP_MASK, IF1 },
	140	{ "mulh", OP(0x07), OP_MASK, IF1 },
	141	{ "mulh", OP(0x17), OP_MASK, IF2 },
	142	{ "mulhi", OP(0x37), OP_MASK, IF6 },
	143	{ "divh", OP(0x02), OP_MASK, IF1 },
	144	{ "cmp", OP(0x0f), OP_MASK, IF1 },
	145	{ "cmp", OP(0x13), OP_MASK, IF2 },
69463cbb	146	{ "setf", two(0x0000,0x0000), two(0x0000,0xffff), {CCCC,R2} },
6d1e1ee8 C	147
	148	/* saturated operation instructions */
	149	{ "satadd", OP(0x06), OP_MASK, IF1 },
	150	{ "satadd", OP(0x11), OP_MASK, IF2 },
	151	{ "satsub", OP(0x05), OP_MASK, IF1 },
	152	{ "satsubi", OP(0x33), OP_MASK, IF6 },
	153	{ "satsubr", OP(0x04), OP_MASK, IF1 },
	154
	155	/* logical operation instructions */
	156	{ "tst", OP(0x0b), OP_MASK, IF1 },
	157	{ "or", OP(0x08), OP_MASK, IF1 },
	158	{ "ori", OP(0x34), OP_MASK, IF6 },
	159	{ "and", OP(0x0a), OP_MASK, IF1 },
	160	{ "andi", OP(0x36), OP_MASK, IF6 },
	161	{ "xor", OP(0x09), OP_MASK, IF1 },
	162	{ "xori", OP(0x35), OP_MASK, IF6 },
	163	{ "not", OP(0x01), OP_MASK, IF1 },
	164	{ "sar", OP(0x15), OP_MASK, IF2 },
	165	{ "sar", two(0x07e0,0x00a0), two(0x07e0,0xffff), {R1,R2} },
	166	{ "shl", OP(0x16), OP_MASK, IF2 },
	167	{ "shl", two(0x07e0,0x00c0), two(0x07e0,0xffff), {R1,R2} },
	168	{ "shr", OP(0x14), OP_MASK, IF2 },
	169	{ "shr", two(0x07e0,0x0080), two(0x07e0,0xffff), {R1,R2} },
	170
	171	/* branch instructions */
6bc33c7f C	172	/* signed integer */
	173	{ "bgt", BOP(0xf), BOP_MASK, IF3 },
	174	{ "bge", BOP(0xe), BOP_MASK, IF3 },
	175	{ "blt", BOP(0x6), BOP_MASK, IF3 },
	176	{ "ble", BOP(0x7), BOP_MASK, IF3 },
	177	/* unsigned integer */
	178	{ "bh", BOP(0xb), BOP_MASK, IF3 },
	179	{ "bnh", BOP(0x3), BOP_MASK, IF3 },
6d1e1ee8	180	{ "bl", BOP(0x1), BOP_MASK, IF3 },
6d1e1ee8	181	{ "bnl", BOP(0x9), BOP_MASK, IF3 },
6bc33c7f	182	/* common */
6d1e1ee8	183	{ "be", BOP(0x2), BOP_MASK, IF3 },
6d1e1ee8	184	{ "bne", BOP(0xa), BOP_MASK, IF3 },
6bc33c7f C	185	/* others */
	186	{ "bv", BOP(0x0), BOP_MASK, IF3 },
	187	{ "bnv", BOP(0x8), BOP_MASK, IF3 },
6d1e1ee8 C	188	{ "bn", BOP(0x4), BOP_MASK, IF3 },
6d1e1ee8 C	189	{ "bp", BOP(0xc), BOP_MASK, IF3 },
6bc33c7f C	190	{ "bc", BOP(0x1), BOP_MASK, IF3 },
	191	{ "bnc", BOP(0x9), BOP_MASK, IF3 },
	192	{ "bz", BOP(0x2), BOP_MASK, IF3 },
	193	{ "bnz", BOP(0xa), BOP_MASK, IF3 },
	194	{ "br", BOP(0x5), BOP_MASK, IF3 },
6d1e1ee8	195	{ "bsa", BOP(0xd), BOP_MASK, IF3 },
6d1e1ee8	196
fed1d21f	197	{ "jmp", one(0x0060), one(0xffe0), R1 },
e89a42c1	198	{ "jarl", one(0x0780), one(0xf83f), { D22, R2 } },
6d1e1ee8 C	199	{ "jr", one(0x0780), one(0xffe0), { D22 } },
6d1e1ee8 C	200
6d1e1ee8	201	/* bit manipulation instructions */
0bdf3144 JL	202	{ "set1", two(0x07c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
	203	{ "not1", two(0x47c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
	204	{ "clr1", two(0x87c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
	205	{ "tst1", two(0xc7c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
6d1e1ee8 C	206
	207	/* special instructions */
	208	{ "di", two(0x07e0,0x0160), two(0xffff,0xffff), {0} },
	209	{ "ei", two(0x87e0,0x0160), two(0xffff,0xffff), {0} },
	210	{ "halt", two(0x07e0,0x0120), two(0xffff,0xffff), {0} },
	211	{ "reti", two(0x07e0,0x0140), two(0xffff,0xffff), {0} },
6d1e1ee8	212	{ "trap", two(0x07e0,0x0100), two(0xffe0,0xffff), {I5} },
6d1e1ee8 C	213	{ "ldsr", two(0x07e0,0x0020), two(0x07e0,0xffff), {0} },
	214	{ "stsr", two(0x07e0,0x0040), two(0x07e0,0xffff), {0} },
	215	{ "nop", one(0x00), one(0xff), {0} },
	216
	217	} ;
	218
	219	const int v850_num_opcodes =
	220	sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
	221
4f235110 C	222	\f
	223	/* The functions used to insert and extract complicated operands. */
	224
	225	static unsigned long
	226	insert_d9 (insn, value, errmsg)
	227	unsigned long insn;
	228	long value;
	229	const char **errmsg;
	230	{
	231	if (value > 511 \|\| value <= -512)
	232	*errmsg = "value out of range";
	233
	234	return (insn \| ((value & 0x1f0) << 7) \| ((value & 0x0e) << 3));
	235	}
	236
	237	static long
	238	extract_d9 (insn, invalid)
	239	unsigned long insn;
	240	int *invalid;
	241	{
	242	long ret = ((insn & 0xf800) >> 7) \| ((insn & 0x0070) >> 3);
	243
	244	if ((insn & 0x8000) != 0)
	245	ret -= 0x0200;
	246
	247	return ret;
	248	}