[deliverable/binutils-gdb.git] / opcodes / v850-opc.c

#include "ansidecl.h"
#include "opcode/v850.h"

/* regular opcode */
#define OP(x)		((x & 0x3f) << 5)
#define OP_MASK		OP(0x3f)

/* conditional branch opcode */
#define BOP(x)		((0x0b << 7) | (x & 0x0f))
#define BOP_MASK	((0x0b << 7) | 0x0f)

/* one-word opcodes */
#define one(x)		((unsigned int) (x))

/* two-word opcodes */
#define two(x,y)	((unsigned int) (y) | ((unsigned int) (x) << 16))


\f
const struct v850_operand v850_operands[] = {
#define UNUSED	0
  { 0, 0, 0, 0, 0 }, 

/* The R1 field in a format 1, 6, 7, or 9 insn. */
#define R1	(UNUSED+1)
  { 5, 0, 0, 0, V850_OPERAND_REG }, 

/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
#define R2	(R1+1)
  { 5, 11, 0, 0, V850_OPERAND_REG },

/* The IMM5 field in a format 2 insn. */
#define I5	(R2+1)
  { 5, 0, 0, 0, 0 }, 

#define IMM16 field in a format 6 insn. */
#define I16	(I5+1)
  { 16, 0, 0, 0, 0 }, 

/* The DISP6 field in a format 4 insn. */
#define D6	(I16+1)
  { 6, 1, 0, 0, 0 },

/* The DISP8 field in a format 3 insn. */
#define D8	(D6+1)
  { 9, 0, 0, 0, 0 },

/* The DISP16 field in a format 6 insn. */
#define D16	(D8+1)
  { 16, 0, 0, 0, 0 }, 

/* The DISP22 field in a format 4 insn. */
#define D22	(D16+1)
  { 16, 0, 0, 0, 0 },

#define B3	(D22+1)
/* The 3 bit immediate field in format 8 insn.  */
  { 3, 11, 0, 0, 0 },

#define CCCC	(B3+1)
/* The 4 bit condition code in a setf instruction */
  { 4, 0, 0, 0, V850_OPERAND_CC }
} ; 

\f
/* reg-reg instruction format (Format I) */
#define IF1	{R1, R2}

/* imm-reg instruction format (Format II) */
#define IF2	{I5, R2}

/* conditional branch instruction format (Format III) */
#define IF3	{D8}

/* 16-bit load/store instruction (Format IV) */
#define IF4A	{D6, R2}
#define IF4B	{R2, D6}

/* Jump instruction (Format V) */
#define IF5	{D22}

/* 3 operand instruction (Format VI) */
#define IF6	{I16, R1, R2}

/* 32-bit load/store instruction (Format VII) */
#define IF7A	{D16, R1, R2}
#define IF7B	{R2, D16, R1}

/* Bit manipulation function.  */


\f
/* The opcode table.

   The format of the opcode table is:

   NAME		OPCODE		MASK		{ OPERANDS }

   NAME is the name of the instruction.
   OPCODE is the instruction opcode.
   MASK is the opcode mask; this is used to tell the disassembler
     which bits in the actual opcode must match OPCODE.
   OPERANDS is the list of operands.

   The disassembler reads the table in order and prints the first
   instruction which matches, so this table is sorted to put more
   specific instructions before more general instructions.  It is also
   sorted by major opcode.  */

const struct v850_opcode v850_opcodes[] = {
/* load/store instructions */
{ "sld.b",	OP(0x00),		OP_MASK,	IF4A },
{ "sld.h",	OP(0x00),		OP_MASK,	IF4A },
{ "sld.w",	OP(0x00),		OP_MASK,	IF4A },
{ "sst.b",	OP(0x00),		OP_MASK,	IF4B },
{ "sst.w",	OP(0x00),		OP_MASK,	IF4B },
{ "sst.l",	OP(0x00),		OP_MASK,	IF4B },

{ "ld.b",	OP(0x00),		OP_MASK,	IF7A },
{ "ld.h",	OP(0x00),		OP_MASK,	IF7A },
{ "ld.w",	OP(0x00),		OP_MASK,	IF7A },
{ "st.b",	OP(0x00),		OP_MASK,	IF7B },
{ "st.h",	OP(0x00),		OP_MASK,	IF7B },
{ "st.w",	OP(0x00),		OP_MASK,	IF7B },

/* arithmetic operation instructions */
{ "mov",        OP(0x00),		OP_MASK,	IF1 },
{ "mov",	OP(0x08),		OP_MASK,	IF2 },
{ "movea",	OP(0x31),		OP_MASK,	IF6 },
{ "movhi",	OP(0x31),		OP_MASK,	IF6 },
{ "add",	OP(0x0e),		OP_MASK,	IF1 },
{ "add",	OP(0x12),		OP_MASK,	IF2 },
{ "addi",	OP(0x30),		OP_MASK,	IF6 },
{ "sub",	OP(0x0d),		OP_MASK,	IF1 },
{ "subr", 	OP(0x0c),		OP_MASK,	IF1 },
{ "mulh",	OP(0x07),		OP_MASK,	IF1 },
{ "mulh",	OP(0x17),		OP_MASK,	IF2 },
{ "mulhi",	OP(0x37),		OP_MASK,	IF6 },
{ "divh",	OP(0x02),		OP_MASK,	IF1 },
{ "cmp",	OP(0x0f),		OP_MASK,	IF1 },
{ "cmp",	OP(0x13),		OP_MASK,	IF2 },
{ "setf",	two(0x0000,0x0000),	two(0x0000,0xffff), {CCCC,R2} },

/* saturated operation instructions */
{ "satadd",	OP(0x06),		OP_MASK,	IF1 },
{ "satadd",	OP(0x11),		OP_MASK,	IF2 },
{ "satsub",	OP(0x05),		OP_MASK,	IF1 },
{ "satsubi",	OP(0x33),		OP_MASK,	IF6 },
{ "satsubr",	OP(0x04),		OP_MASK,	IF1 },

/* logical operation instructions */
{ "tst",	OP(0x0b),		OP_MASK,	IF1 },
{ "or",		OP(0x08),		OP_MASK,	IF1 },
{ "ori",	OP(0x34),		OP_MASK,	IF6 },
{ "and",	OP(0x0a),		OP_MASK,	IF1 },
{ "andi",	OP(0x36),		OP_MASK,	IF6 },
{ "xor",	OP(0x09),		OP_MASK,	IF1 },
{ "xori",	OP(0x35),		OP_MASK,	IF6 },
{ "not",	OP(0x01),		OP_MASK,	IF1 },
{ "sar",	OP(0x15),		OP_MASK,	IF2 },
{ "sar",	two(0x07e0,0x00a0),	two(0x07e0,0xffff),	{R1,R2} },
{ "shl",	OP(0x16),		OP_MASK,		IF2 },
{ "shl",	two(0x07e0,0x00c0),	two(0x07e0,0xffff),	{R1,R2} },
{ "shr",	OP(0x14),		OP_MASK,		IF2 },
{ "shr",	two(0x07e0,0x0080),	two(0x07e0,0xffff),	{R1,R2} },

/* branch instructions */
	/* signed integer */
{ "bgt",	BOP(0xf),		BOP_MASK,	IF3 },
{ "bge",	BOP(0xe),		BOP_MASK,	IF3 },
{ "blt",	BOP(0x6),		BOP_MASK,	IF3 },
{ "ble",	BOP(0x7),		BOP_MASK,	IF3 },
	/* unsigned integer */
{ "bh",		BOP(0xb),		BOP_MASK,	IF3 },
{ "bnh",	BOP(0x3),		BOP_MASK,	IF3 },
{ "bl",		BOP(0x1),		BOP_MASK,	IF3 },
{ "bnl",	BOP(0x9),		BOP_MASK,	IF3 },
	/* common */
{ "be",		BOP(0x2),		BOP_MASK,	IF3 },
{ "bne",	BOP(0xa),		BOP_MASK,	IF3 },
	/* others */
{ "bv",		BOP(0x0),		BOP_MASK,	IF3 },
{ "bnv",	BOP(0x8),		BOP_MASK,	IF3 },
{ "bn",		BOP(0x4),		BOP_MASK,	IF3 },
{ "bp",		BOP(0xc),		BOP_MASK,	IF3 },
{ "bc",		BOP(0x1),		BOP_MASK,	IF3 },
{ "bnc",	BOP(0x9),		BOP_MASK,	IF3 },
{ "bz",		BOP(0x2),		BOP_MASK,	IF3 },
{ "bnz",	BOP(0xa),		BOP_MASK,	IF3 },
{ "br",		BOP(0x5),		BOP_MASK,	IF3 },
{ "bsa",	BOP(0xd),		BOP_MASK,	IF3 },

{ "jmp",	one(0x0060),		one(0xffe0),	R1 },
{ "jarl",	one(0x0780),		one(0xf83f),	{ D22, R2 } }, 
{ "jr",		one(0x0780),		one(0xffe0),	{ D22 } },

/* bit manipulation instructions */
{ "set1",	two(0x07c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1} },
{ "not1",	two(0x47c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1} },
{ "clr1",	two(0x87c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1} },
{ "tst1",	two(0xc7c0,0x0000),	two(0xc7e0,0x0000),	{B3, D16, R1} },

/* special instructions */
{ "di",		two(0x07e0,0x0160),	two(0xffff,0xffff),	{0} },
{ "ei",		two(0x87e0,0x0160),	two(0xffff,0xffff),	{0} },
{ "halt",	two(0x07e0,0x0120),	two(0xffff,0xffff),	{0} },
{ "reti",	two(0x07e0,0x0140),	two(0xffff,0xffff),	{0} },
{ "trap",	two(0x07e0,0x0100),	two(0xffe0,0xffff),	{I5} },
{ "ldsr",	two(0x07e0,0x0020),	two(0x07e0,0xffff),	{0} },
{ "stsr",	two(0x07e0,0x0040),	two(0x07e0,0xffff),	{0} },
{ "nop",	one(0x00),		one(0xff),		{0} },

} ;

const int v850_num_opcodes =
  sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
Commit	Line	Data
6d1e1ee8 C	1	#include "ansidecl.h"
	2	#include "opcode/v850.h"
	3
	4	/* regular opcode */
	5	#define OP(x) ((x & 0x3f) << 5)
	6	#define OP_MASK OP(0x3f)
	7
	8	/* conditional branch opcode */
	9	#define BOP(x) ((0x0b << 7) \| (x & 0x0f))
	10	#define BOP_MASK ((0x0b << 7) \| 0x0f)
	11
	12	/* one-word opcodes */
	13	#define one(x) ((unsigned int) (x))
	14
	15	/* two-word opcodes */
	16	#define two(x,y) ((unsigned int) (y) \| ((unsigned int) (x) << 16))
	17
	18
	19	\f
	20	const struct v850_operand v850_operands[] = {
	21	#define UNUSED 0
69463cbb	22	{ 0, 0, 0, 0, 0 },
6d1e1ee8 C	23
	24	/* The R1 field in a format 1, 6, 7, or 9 insn. */
	25	#define R1 (UNUSED+1)
69463cbb	26	{ 5, 0, 0, 0, V850_OPERAND_REG },
6d1e1ee8 C	27
	28	/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
	29	#define R2 (R1+1)
69463cbb	30	{ 5, 11, 0, 0, V850_OPERAND_REG },
6d1e1ee8 C	31
	32	/* The IMM5 field in a format 2 insn. */
	33	#define I5 (R2+1)
69463cbb	34	{ 5, 0, 0, 0, 0 },
6d1e1ee8 C	35
	36	#define IMM16 field in a format 6 insn. */
	37	#define I16 (I5+1)
69463cbb	38	{ 16, 0, 0, 0, 0 },
6d1e1ee8 C	39
	40	/* The DISP6 field in a format 4 insn. */
	41	#define D6 (I16+1)
69463cbb	42	{ 6, 1, 0, 0, 0 },
6d1e1ee8 C	43
	44	/* The DISP8 field in a format 3 insn. */
	45	#define D8 (D6+1)
69463cbb	46	{ 9, 0, 0, 0, 0 },
6d1e1ee8 C	47
	48	/* The DISP16 field in a format 6 insn. */
	49	#define D16 (D8+1)
69463cbb	50	{ 16, 0, 0, 0, 0 },
6d1e1ee8 C	51
	52	/* The DISP22 field in a format 4 insn. */
	53	#define D22 (D16+1)
69463cbb	54	{ 16, 0, 0, 0, 0 },
7c8157dd JL	55
	56	#define B3 (D22+1)
	57	/* The 3 bit immediate field in format 8 insn. */
69463cbb C	58	{ 3, 11, 0, 0, 0 },
	59
	60	#define CCCC (B3+1)
	61	/* The 4 bit condition code in a setf instruction */
	62	{ 4, 0, 0, 0, V850_OPERAND_CC }
6d1e1ee8 C	63	} ;
	64
	65	\f
	66	/* reg-reg instruction format (Format I) */
	67	#define IF1 {R1, R2}
	68
	69	/* imm-reg instruction format (Format II) */
	70	#define IF2 {I5, R2}
	71
	72	/* conditional branch instruction format (Format III) */
	73	#define IF3 {D8}
	74
	75	/* 16-bit load/store instruction (Format IV) */
e89a42c1 C	76	#define IF4A {D6, R2}
e89a42c1 C	77	#define IF4B {R2, D6}
6d1e1ee8 C	78
	79	/* Jump instruction (Format V) */
	80	#define IF5 {D22}
	81
	82	/* 3 operand instruction (Format VI) */
e89a42c1	83	#define IF6 {I16, R1, R2}
6d1e1ee8 C	84
6d1e1ee8 C	85	/* 32-bit load/store instruction (Format VII) */
e89a42c1 C	86	#define IF7A {D16, R1, R2}
e89a42c1 C	87	#define IF7B {R2, D16, R1}
6d1e1ee8	88
b10e29f4	89	/* Bit manipulation function. */
6d1e1ee8 C	90
	91
	92	\f
	93	/* The opcode table.
	94
	95	The format of the opcode table is:
	96
	97	NAME OPCODE MASK { OPERANDS }
	98
	99	NAME is the name of the instruction.
	100	OPCODE is the instruction opcode.
	101	MASK is the opcode mask; this is used to tell the disassembler
	102	which bits in the actual opcode must match OPCODE.
	103	OPERANDS is the list of operands.
	104
	105	The disassembler reads the table in order and prints the first
	106	instruction which matches, so this table is sorted to put more
	107	specific instructions before more general instructions. It is also
	108	sorted by major opcode. */
	109
	110	const struct v850_opcode v850_opcodes[] = {
	111	/* load/store instructions */
e89a42c1 C	112	{ "sld.b", OP(0x00), OP_MASK, IF4A },
	113	{ "sld.h", OP(0x00), OP_MASK, IF4A },
	114	{ "sld.w", OP(0x00), OP_MASK, IF4A },
	115	{ "sst.b", OP(0x00), OP_MASK, IF4B },
	116	{ "sst.w", OP(0x00), OP_MASK, IF4B },
	117	{ "sst.l", OP(0x00), OP_MASK, IF4B },
	118
	119	{ "ld.b", OP(0x00), OP_MASK, IF7A },
	120	{ "ld.h", OP(0x00), OP_MASK, IF7A },
	121	{ "ld.w", OP(0x00), OP_MASK, IF7A },
	122	{ "st.b", OP(0x00), OP_MASK, IF7B },
	123	{ "st.h", OP(0x00), OP_MASK, IF7B },
	124	{ "st.w", OP(0x00), OP_MASK, IF7B },
6d1e1ee8 C	125
6d1e1ee8 C	126	/* arithmetic operation instructions */
6bc33c7f C	127	{ "mov", OP(0x00), OP_MASK, IF1 },
	128	{ "mov", OP(0x08), OP_MASK, IF2 },
	129	{ "movea", OP(0x31), OP_MASK, IF6 },
	130	{ "movhi", OP(0x31), OP_MASK, IF6 },
6d1e1ee8 C	131	{ "add", OP(0x0e), OP_MASK, IF1 },
	132	{ "add", OP(0x12), OP_MASK, IF2 },
	133	{ "addi", OP(0x30), OP_MASK, IF6 },
	134	{ "sub", OP(0x0d), OP_MASK, IF1 },
	135	{ "subr", OP(0x0c), OP_MASK, IF1 },
	136	{ "mulh", OP(0x07), OP_MASK, IF1 },
	137	{ "mulh", OP(0x17), OP_MASK, IF2 },
	138	{ "mulhi", OP(0x37), OP_MASK, IF6 },
	139	{ "divh", OP(0x02), OP_MASK, IF1 },
	140	{ "cmp", OP(0x0f), OP_MASK, IF1 },
	141	{ "cmp", OP(0x13), OP_MASK, IF2 },
69463cbb	142	{ "setf", two(0x0000,0x0000), two(0x0000,0xffff), {CCCC,R2} },
6d1e1ee8 C	143
	144	/* saturated operation instructions */
	145	{ "satadd", OP(0x06), OP_MASK, IF1 },
	146	{ "satadd", OP(0x11), OP_MASK, IF2 },
	147	{ "satsub", OP(0x05), OP_MASK, IF1 },
	148	{ "satsubi", OP(0x33), OP_MASK, IF6 },
	149	{ "satsubr", OP(0x04), OP_MASK, IF1 },
	150
	151	/* logical operation instructions */
	152	{ "tst", OP(0x0b), OP_MASK, IF1 },
	153	{ "or", OP(0x08), OP_MASK, IF1 },
	154	{ "ori", OP(0x34), OP_MASK, IF6 },
	155	{ "and", OP(0x0a), OP_MASK, IF1 },
	156	{ "andi", OP(0x36), OP_MASK, IF6 },
	157	{ "xor", OP(0x09), OP_MASK, IF1 },
	158	{ "xori", OP(0x35), OP_MASK, IF6 },
	159	{ "not", OP(0x01), OP_MASK, IF1 },
	160	{ "sar", OP(0x15), OP_MASK, IF2 },
	161	{ "sar", two(0x07e0,0x00a0), two(0x07e0,0xffff), {R1,R2} },
	162	{ "shl", OP(0x16), OP_MASK, IF2 },
	163	{ "shl", two(0x07e0,0x00c0), two(0x07e0,0xffff), {R1,R2} },
	164	{ "shr", OP(0x14), OP_MASK, IF2 },
	165	{ "shr", two(0x07e0,0x0080), two(0x07e0,0xffff), {R1,R2} },
	166
	167	/* branch instructions */
6bc33c7f C	168	/* signed integer */
	169	{ "bgt", BOP(0xf), BOP_MASK, IF3 },
	170	{ "bge", BOP(0xe), BOP_MASK, IF3 },
	171	{ "blt", BOP(0x6), BOP_MASK, IF3 },
	172	{ "ble", BOP(0x7), BOP_MASK, IF3 },
	173	/* unsigned integer */
	174	{ "bh", BOP(0xb), BOP_MASK, IF3 },
	175	{ "bnh", BOP(0x3), BOP_MASK, IF3 },
6d1e1ee8	176	{ "bl", BOP(0x1), BOP_MASK, IF3 },
6d1e1ee8	177	{ "bnl", BOP(0x9), BOP_MASK, IF3 },
6bc33c7f	178	/* common */
6d1e1ee8	179	{ "be", BOP(0x2), BOP_MASK, IF3 },
6d1e1ee8	180	{ "bne", BOP(0xa), BOP_MASK, IF3 },
6bc33c7f C	181	/* others */
	182	{ "bv", BOP(0x0), BOP_MASK, IF3 },
	183	{ "bnv", BOP(0x8), BOP_MASK, IF3 },
6d1e1ee8 C	184	{ "bn", BOP(0x4), BOP_MASK, IF3 },
6d1e1ee8 C	185	{ "bp", BOP(0xc), BOP_MASK, IF3 },
6bc33c7f C	186	{ "bc", BOP(0x1), BOP_MASK, IF3 },
	187	{ "bnc", BOP(0x9), BOP_MASK, IF3 },
	188	{ "bz", BOP(0x2), BOP_MASK, IF3 },
	189	{ "bnz", BOP(0xa), BOP_MASK, IF3 },
	190	{ "br", BOP(0x5), BOP_MASK, IF3 },
6d1e1ee8	191	{ "bsa", BOP(0xd), BOP_MASK, IF3 },
6d1e1ee8	192
fed1d21f	193	{ "jmp", one(0x0060), one(0xffe0), R1 },
e89a42c1	194	{ "jarl", one(0x0780), one(0xf83f), { D22, R2 } },
6d1e1ee8 C	195	{ "jr", one(0x0780), one(0xffe0), { D22 } },
6d1e1ee8 C	196
6d1e1ee8	197	/* bit manipulation instructions */
0bdf3144 JL	198	{ "set1", two(0x07c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
	199	{ "not1", two(0x47c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
	200	{ "clr1", two(0x87c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
	201	{ "tst1", two(0xc7c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
6d1e1ee8 C	202
	203	/* special instructions */
	204	{ "di", two(0x07e0,0x0160), two(0xffff,0xffff), {0} },
	205	{ "ei", two(0x87e0,0x0160), two(0xffff,0xffff), {0} },
	206	{ "halt", two(0x07e0,0x0120), two(0xffff,0xffff), {0} },
	207	{ "reti", two(0x07e0,0x0140), two(0xffff,0xffff), {0} },
6d1e1ee8	208	{ "trap", two(0x07e0,0x0100), two(0xffe0,0xffff), {I5} },
6d1e1ee8 C	209	{ "ldsr", two(0x07e0,0x0020), two(0x07e0,0xffff), {0} },
	210	{ "stsr", two(0x07e0,0x0040), two(0x07e0,0xffff), {0} },
	211	{ "nop", one(0x00), one(0xff), {0} },
	212
	213	} ;
	214
	215	const int v850_num_opcodes =
	216	sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
	217