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93fbbb04 GK |
1 | /* CPU data for xstormy16. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
1951c6f7 | 5 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
93fbbb04 GK |
6 | |
7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License along | |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | ||
23 | */ | |
24 | ||
25 | #include "sysdep.h" | |
26 | #include <stdio.h> | |
27 | #include <stdarg.h> | |
28 | #include "ansidecl.h" | |
29 | #include "bfd.h" | |
30 | #include "symcat.h" | |
31 | #include "xstormy16-desc.h" | |
32 | #include "xstormy16-opc.h" | |
33 | #include "opintl.h" | |
34 | #include "libiberty.h" | |
98f70fc4 | 35 | #include "xregex.h" |
93fbbb04 GK |
36 | |
37 | /* Attributes. */ | |
38 | ||
39 | static const CGEN_ATTR_ENTRY bool_attr[] = | |
40 | { | |
41 | { "#f", 0 }, | |
42 | { "#t", 1 }, | |
43 | { 0, 0 } | |
44 | }; | |
45 | ||
46 | static const CGEN_ATTR_ENTRY MACH_attr[] = | |
47 | { | |
48 | { "base", MACH_BASE }, | |
49 | { "xstormy16", MACH_XSTORMY16 }, | |
50 | { "max", MACH_MAX }, | |
51 | { 0, 0 } | |
52 | }; | |
53 | ||
54 | static const CGEN_ATTR_ENTRY ISA_attr[] = | |
55 | { | |
56 | { "xstormy16", ISA_XSTORMY16 }, | |
57 | { "max", ISA_MAX }, | |
58 | { 0, 0 } | |
59 | }; | |
60 | ||
61 | const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[] = | |
62 | { | |
63 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, | |
64 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, | |
65 | { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, | |
66 | { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, | |
67 | { "RESERVED", &bool_attr[0], &bool_attr[0] }, | |
68 | { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, | |
69 | { "SIGNED", &bool_attr[0], &bool_attr[0] }, | |
70 | { 0, 0, 0 } | |
71 | }; | |
72 | ||
73 | const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[] = | |
74 | { | |
75 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, | |
76 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, | |
77 | { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, | |
78 | { "PC", &bool_attr[0], &bool_attr[0] }, | |
79 | { "PROFILE", &bool_attr[0], &bool_attr[0] }, | |
80 | { 0, 0, 0 } | |
81 | }; | |
82 | ||
83 | const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[] = | |
84 | { | |
85 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, | |
86 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, | |
87 | { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, | |
88 | { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, | |
89 | { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, | |
90 | { "SIGNED", &bool_attr[0], &bool_attr[0] }, | |
91 | { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, | |
92 | { "RELAX", &bool_attr[0], &bool_attr[0] }, | |
93 | { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, | |
94 | { 0, 0, 0 } | |
95 | }; | |
96 | ||
97 | const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[] = | |
98 | { | |
99 | { "MACH", & MACH_attr[0], & MACH_attr[0] }, | |
100 | { "ALIAS", &bool_attr[0], &bool_attr[0] }, | |
101 | { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, | |
102 | { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, | |
103 | { "COND-CTI", &bool_attr[0], &bool_attr[0] }, | |
104 | { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, | |
105 | { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, | |
106 | { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, | |
107 | { "RELAX", &bool_attr[0], &bool_attr[0] }, | |
108 | { "NO-DIS", &bool_attr[0], &bool_attr[0] }, | |
109 | { "PBB", &bool_attr[0], &bool_attr[0] }, | |
110 | { 0, 0, 0 } | |
111 | }; | |
112 | ||
113 | /* Instruction set variants. */ | |
114 | ||
115 | static const CGEN_ISA xstormy16_cgen_isa_table[] = { | |
116 | { "xstormy16", 32, 32, 16, 32 }, | |
117 | { 0, 0, 0, 0, 0 } | |
118 | }; | |
119 | ||
120 | /* Machine variants. */ | |
121 | ||
122 | static const CGEN_MACH xstormy16_cgen_mach_table[] = { | |
123 | { "xstormy16", "xstormy16", MACH_XSTORMY16, 16 }, | |
124 | { 0, 0, 0, 0 } | |
125 | }; | |
126 | ||
127 | static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_names_entries[] = | |
128 | { | |
129 | { "r0", 0, {0, {0}}, 0, 0 }, | |
130 | { "r1", 1, {0, {0}}, 0, 0 }, | |
131 | { "r2", 2, {0, {0}}, 0, 0 }, | |
132 | { "r3", 3, {0, {0}}, 0, 0 }, | |
133 | { "r4", 4, {0, {0}}, 0, 0 }, | |
134 | { "r5", 5, {0, {0}}, 0, 0 }, | |
135 | { "r6", 6, {0, {0}}, 0, 0 }, | |
136 | { "r7", 7, {0, {0}}, 0, 0 }, | |
137 | { "r8", 8, {0, {0}}, 0, 0 }, | |
138 | { "r9", 9, {0, {0}}, 0, 0 }, | |
139 | { "r10", 10, {0, {0}}, 0, 0 }, | |
140 | { "r11", 11, {0, {0}}, 0, 0 }, | |
141 | { "r12", 12, {0, {0}}, 0, 0 }, | |
142 | { "r13", 13, {0, {0}}, 0, 0 }, | |
143 | { "r14", 14, {0, {0}}, 0, 0 }, | |
144 | { "r15", 15, {0, {0}}, 0, 0 }, | |
145 | { "psw", 14, {0, {0}}, 0, 0 }, | |
146 | { "sp", 15, {0, {0}}, 0, 0 } | |
147 | }; | |
148 | ||
149 | CGEN_KEYWORD xstormy16_cgen_opval_gr_names = | |
150 | { | |
151 | & xstormy16_cgen_opval_gr_names_entries[0], | |
152 | 18, | |
153 | 0, 0, 0, 0, "" | |
154 | }; | |
155 | ||
1951c6f7 | 156 | static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_Rb_names_entries[] = |
93fbbb04 GK |
157 | { |
158 | { "r8", 0, {0, {0}}, 0, 0 }, | |
1951c6f7 MG |
159 | { "r9", 1, {0, {0}}, 0, 0 }, |
160 | { "r10", 2, {0, {0}}, 0, 0 }, | |
161 | { "r11", 3, {0, {0}}, 0, 0 }, | |
162 | { "r12", 4, {0, {0}}, 0, 0 }, | |
163 | { "r13", 5, {0, {0}}, 0, 0 }, | |
164 | { "r14", 6, {0, {0}}, 0, 0 }, | |
165 | { "r15", 7, {0, {0}}, 0, 0 }, | |
166 | { "psw", 6, {0, {0}}, 0, 0 }, | |
167 | { "sp", 7, {0, {0}}, 0, 0 } | |
93fbbb04 GK |
168 | }; |
169 | ||
1951c6f7 | 170 | CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names = |
93fbbb04 | 171 | { |
1951c6f7 MG |
172 | & xstormy16_cgen_opval_gr_Rb_names_entries[0], |
173 | 10, | |
93fbbb04 GK |
174 | 0, 0, 0, 0, "" |
175 | }; | |
176 | ||
177 | static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_branchcond_entries[] = | |
178 | { | |
179 | { "ge", 0, {0, {0}}, 0, 0 }, | |
180 | { "nc", 1, {0, {0}}, 0, 0 }, | |
181 | { "lt", 2, {0, {0}}, 0, 0 }, | |
182 | { "c", 3, {0, {0}}, 0, 0 }, | |
183 | { "gt", 4, {0, {0}}, 0, 0 }, | |
184 | { "hi", 5, {0, {0}}, 0, 0 }, | |
185 | { "le", 6, {0, {0}}, 0, 0 }, | |
186 | { "ls", 7, {0, {0}}, 0, 0 }, | |
187 | { "pl", 8, {0, {0}}, 0, 0 }, | |
188 | { "nv", 9, {0, {0}}, 0, 0 }, | |
189 | { "mi", 10, {0, {0}}, 0, 0 }, | |
190 | { "v", 11, {0, {0}}, 0, 0 }, | |
191 | { "nz.b", 12, {0, {0}}, 0, 0 }, | |
192 | { "nz", 13, {0, {0}}, 0, 0 }, | |
193 | { "z.b", 14, {0, {0}}, 0, 0 }, | |
194 | { "z", 15, {0, {0}}, 0, 0 } | |
195 | }; | |
196 | ||
197 | CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond = | |
198 | { | |
199 | & xstormy16_cgen_opval_h_branchcond_entries[0], | |
200 | 16, | |
201 | 0, 0, 0, 0, "" | |
202 | }; | |
203 | ||
204 | static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_wordsize_entries[] = | |
205 | { | |
206 | { ".b", 0, {0, {0}}, 0, 0 }, | |
207 | { ".w", 1, {0, {0}}, 0, 0 }, | |
208 | { "", 1, {0, {0}}, 0, 0 } | |
209 | }; | |
210 | ||
211 | CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize = | |
212 | { | |
213 | & xstormy16_cgen_opval_h_wordsize_entries[0], | |
214 | 3, | |
215 | 0, 0, 0, 0, "" | |
216 | }; | |
217 | ||
218 | ||
219 | /* The hardware table. */ | |
220 | ||
221 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) | |
222 | #define A(a) (1 << CGEN_HW_##a) | |
223 | #else | |
224 | #define A(a) (1 << CGEN_HW_/**/a) | |
225 | #endif | |
226 | ||
227 | const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] = | |
228 | { | |
229 | { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
230 | { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
231 | { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
232 | { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
233 | { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, | |
234 | { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE) } } }, | |
235 | { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_names, { 0, { (1<<MACH_BASE) } } }, | |
1951c6f7 MG |
236 | { "h-Rb", HW_H_RB, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
237 | { "h-Rbj", HW_H_RBJ, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, | |
93fbbb04 GK |
238 | { "h-Rpsw", HW_H_RPSW, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
239 | { "h-z8", HW_H_Z8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, | |
240 | { "h-z16", HW_H_Z16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, | |
241 | { "h-cy", HW_H_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, | |
242 | { "h-hc", HW_H_HC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, | |
243 | { "h-ov", HW_H_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, | |
244 | { "h-pt", HW_H_PT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, | |
245 | { "h-s", HW_H_S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, | |
246 | { "h-branchcond", HW_H_BRANCHCOND, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_branchcond, { 0, { (1<<MACH_BASE) } } }, | |
247 | { "h-wordsize", HW_H_WORDSIZE, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_wordsize, { 0, { (1<<MACH_BASE) } } }, | |
248 | { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } | |
249 | }; | |
250 | ||
251 | #undef A | |
252 | ||
253 | ||
254 | /* The instruction field table. */ | |
255 | ||
256 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) | |
257 | #define A(a) (1 << CGEN_IFLD_##a) | |
258 | #else | |
259 | #define A(a) (1 << CGEN_IFLD_/**/a) | |
260 | #endif | |
261 | ||
262 | const CGEN_IFLD xstormy16_cgen_ifld_table[] = | |
263 | { | |
264 | { XSTORMY16_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, | |
265 | { XSTORMY16_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, | |
266 | { XSTORMY16_F_RD, "f-Rd", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } }, | |
267 | { XSTORMY16_F_RDM, "f-Rdm", 0, 32, 13, 3, { 0, { (1<<MACH_BASE) } } }, | |
268 | { XSTORMY16_F_RM, "f-Rm", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } }, | |
269 | { XSTORMY16_F_RS, "f-Rs", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } }, | |
270 | { XSTORMY16_F_RB, "f-Rb", 0, 32, 17, 3, { 0, { (1<<MACH_BASE) } } }, | |
271 | { XSTORMY16_F_RBJ, "f-Rbj", 0, 32, 11, 1, { 0, { (1<<MACH_BASE) } } }, | |
272 | { XSTORMY16_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } } }, | |
273 | { XSTORMY16_F_OP2, "f-op2", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } }, | |
274 | { XSTORMY16_F_OP2A, "f-op2a", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } }, | |
275 | { XSTORMY16_F_OP2M, "f-op2m", 0, 32, 7, 1, { 0, { (1<<MACH_BASE) } } }, | |
276 | { XSTORMY16_F_OP3, "f-op3", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } }, | |
277 | { XSTORMY16_F_OP3A, "f-op3a", 0, 32, 8, 2, { 0, { (1<<MACH_BASE) } } }, | |
278 | { XSTORMY16_F_OP3B, "f-op3b", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } } }, | |
279 | { XSTORMY16_F_OP4, "f-op4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } }, | |
280 | { XSTORMY16_F_OP4M, "f-op4m", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } } }, | |
281 | { XSTORMY16_F_OP4B, "f-op4b", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } }, | |
282 | { XSTORMY16_F_OP5, "f-op5", 0, 32, 16, 4, { 0, { (1<<MACH_BASE) } } }, | |
283 | { XSTORMY16_F_OP5A, "f-op5a", 0, 32, 16, 1, { 0, { (1<<MACH_BASE) } } }, | |
284 | { XSTORMY16_F_OP, "f-op", 0, 32, 0, 16, { 0, { (1<<MACH_BASE) } } }, | |
285 | { XSTORMY16_F_IMM2, "f-imm2", 0, 32, 10, 2, { 0, { (1<<MACH_BASE) } } }, | |
286 | { XSTORMY16_F_IMM3, "f-imm3", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } }, | |
287 | { XSTORMY16_F_IMM3B, "f-imm3b", 0, 32, 17, 3, { 0, { (1<<MACH_BASE) } } }, | |
288 | { XSTORMY16_F_IMM4, "f-imm4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } }, | |
289 | { XSTORMY16_F_IMM8, "f-imm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } }, | |
290 | { XSTORMY16_F_IMM12, "f-imm12", 0, 32, 20, 12, { 0, { (1<<MACH_BASE) } } }, | |
291 | { XSTORMY16_F_IMM16, "f-imm16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } }, | |
292 | { XSTORMY16_F_LMEM8, "f-lmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, | |
293 | { XSTORMY16_F_HMEM8, "f-hmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, | |
294 | { XSTORMY16_F_REL8_2, "f-rel8-2", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, | |
295 | { XSTORMY16_F_REL8_4, "f-rel8-4", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, | |
296 | { XSTORMY16_F_REL12, "f-rel12", 0, 32, 20, 12, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, | |
297 | { XSTORMY16_F_REL12A, "f-rel12a", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, | |
298 | { XSTORMY16_F_ABS24_1, "f-abs24-1", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } }, | |
299 | { XSTORMY16_F_ABS24_2, "f-abs24-2", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } }, | |
300 | { 0, 0, 0, 0, 0, 0, {0, {0}} } | |
301 | }; | |
302 | ||
303 | #undef A | |
304 | ||
305 | ||
9a2e995d GH |
306 | |
307 | /* multi ifield declarations */ | |
308 | ||
309 | const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD []; | |
310 | ||
311 | ||
312 | /* multi ifield definitions */ | |
313 | ||
314 | const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [] = | |
315 | { | |
98f70fc4 AM |
316 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[34] } }, |
317 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[35] } }, | |
318 | { 0, { (const PTR) 0 } } | |
9a2e995d GH |
319 | }; |
320 | ||
93fbbb04 GK |
321 | /* The operand table. */ |
322 | ||
323 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) | |
324 | #define A(a) (1 << CGEN_OPERAND_##a) | |
325 | #else | |
326 | #define A(a) (1 << CGEN_OPERAND_/**/a) | |
327 | #endif | |
328 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) | |
329 | #define OPERAND(op) XSTORMY16_OPERAND_##op | |
330 | #else | |
331 | #define OPERAND(op) XSTORMY16_OPERAND_/**/op | |
332 | #endif | |
333 | ||
334 | const CGEN_OPERAND xstormy16_cgen_operand_table[] = | |
335 | { | |
336 | /* pc: program counter */ | |
337 | { "pc", XSTORMY16_OPERAND_PC, HW_H_PC, 0, 0, | |
98f70fc4 | 338 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[0] } }, |
93fbbb04 GK |
339 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
340 | /* psw-z8: */ | |
341 | { "psw-z8", XSTORMY16_OPERAND_PSW_Z8, HW_H_Z8, 0, 0, | |
98f70fc4 | 342 | { 0, { (const PTR) 0 } }, |
93fbbb04 GK |
343 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
344 | /* psw-z16: */ | |
345 | { "psw-z16", XSTORMY16_OPERAND_PSW_Z16, HW_H_Z16, 0, 0, | |
98f70fc4 | 346 | { 0, { (const PTR) 0 } }, |
93fbbb04 GK |
347 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
348 | /* psw-cy: */ | |
349 | { "psw-cy", XSTORMY16_OPERAND_PSW_CY, HW_H_CY, 0, 0, | |
98f70fc4 | 350 | { 0, { (const PTR) 0 } }, |
93fbbb04 GK |
351 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
352 | /* psw-hc: */ | |
353 | { "psw-hc", XSTORMY16_OPERAND_PSW_HC, HW_H_HC, 0, 0, | |
98f70fc4 | 354 | { 0, { (const PTR) 0 } }, |
93fbbb04 GK |
355 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
356 | /* psw-ov: */ | |
357 | { "psw-ov", XSTORMY16_OPERAND_PSW_OV, HW_H_OV, 0, 0, | |
98f70fc4 | 358 | { 0, { (const PTR) 0 } }, |
93fbbb04 GK |
359 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
360 | /* psw-pt: */ | |
361 | { "psw-pt", XSTORMY16_OPERAND_PSW_PT, HW_H_PT, 0, 0, | |
98f70fc4 | 362 | { 0, { (const PTR) 0 } }, |
93fbbb04 GK |
363 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
364 | /* psw-s: */ | |
365 | { "psw-s", XSTORMY16_OPERAND_PSW_S, HW_H_S, 0, 0, | |
98f70fc4 | 366 | { 0, { (const PTR) 0 } }, |
93fbbb04 GK |
367 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
368 | /* Rd: general register destination */ | |
369 | { "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4, | |
98f70fc4 | 370 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[2] } }, |
93fbbb04 GK |
371 | { 0, { (1<<MACH_BASE) } } }, |
372 | /* Rdm: general register destination */ | |
373 | { "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3, | |
98f70fc4 | 374 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[3] } }, |
93fbbb04 GK |
375 | { 0, { (1<<MACH_BASE) } } }, |
376 | /* Rm: general register for memory */ | |
377 | { "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3, | |
98f70fc4 | 378 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[4] } }, |
93fbbb04 GK |
379 | { 0, { (1<<MACH_BASE) } } }, |
380 | /* Rs: general register source */ | |
381 | { "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4, | |
98f70fc4 | 382 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[5] } }, |
93fbbb04 GK |
383 | { 0, { (1<<MACH_BASE) } } }, |
384 | /* Rb: base register */ | |
1951c6f7 | 385 | { "Rb", XSTORMY16_OPERAND_RB, HW_H_RB, 17, 3, |
98f70fc4 | 386 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[6] } }, |
93fbbb04 GK |
387 | { 0, { (1<<MACH_BASE) } } }, |
388 | /* Rbj: base register for jump */ | |
389 | { "Rbj", XSTORMY16_OPERAND_RBJ, HW_H_RBJ, 11, 1, | |
98f70fc4 | 390 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[7] } }, |
93fbbb04 GK |
391 | { 0, { (1<<MACH_BASE) } } }, |
392 | /* bcond2: branch condition opcode */ | |
393 | { "bcond2", XSTORMY16_OPERAND_BCOND2, HW_H_BRANCHCOND, 4, 4, | |
98f70fc4 | 394 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[9] } }, |
93fbbb04 GK |
395 | { 0, { (1<<MACH_BASE) } } }, |
396 | /* ws2: word size opcode */ | |
397 | { "ws2", XSTORMY16_OPERAND_WS2, HW_H_WORDSIZE, 7, 1, | |
98f70fc4 | 398 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[11] } }, |
93fbbb04 GK |
399 | { 0, { (1<<MACH_BASE) } } }, |
400 | /* bcond5: branch condition opcode */ | |
401 | { "bcond5", XSTORMY16_OPERAND_BCOND5, HW_H_BRANCHCOND, 16, 4, | |
98f70fc4 | 402 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[18] } }, |
93fbbb04 GK |
403 | { 0, { (1<<MACH_BASE) } } }, |
404 | /* imm2: 2 bit unsigned immediate */ | |
405 | { "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2, | |
98f70fc4 | 406 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[21] } }, |
93fbbb04 GK |
407 | { 0, { (1<<MACH_BASE) } } }, |
408 | /* imm3: 3 bit unsigned immediate */ | |
409 | { "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3, | |
98f70fc4 | 410 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[22] } }, |
93fbbb04 GK |
411 | { 0, { (1<<MACH_BASE) } } }, |
412 | /* imm3b: 3 bit unsigned immediate for bit tests */ | |
413 | { "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3, | |
98f70fc4 | 414 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[23] } }, |
93fbbb04 GK |
415 | { 0, { (1<<MACH_BASE) } } }, |
416 | /* imm4: 4 bit unsigned immediate */ | |
417 | { "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4, | |
98f70fc4 | 418 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[24] } }, |
93fbbb04 GK |
419 | { 0, { (1<<MACH_BASE) } } }, |
420 | /* imm8: 8 bit unsigned immediate */ | |
421 | { "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8, | |
98f70fc4 | 422 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[25] } }, |
93fbbb04 GK |
423 | { 0, { (1<<MACH_BASE) } } }, |
424 | /* imm8small: 8 bit unsigned immediate */ | |
425 | { "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8, | |
98f70fc4 | 426 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[25] } }, |
93fbbb04 GK |
427 | { 0, { (1<<MACH_BASE) } } }, |
428 | /* imm12: 12 bit signed immediate */ | |
429 | { "imm12", XSTORMY16_OPERAND_IMM12, HW_H_SINT, 20, 12, | |
98f70fc4 | 430 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[26] } }, |
93fbbb04 GK |
431 | { 0, { (1<<MACH_BASE) } } }, |
432 | /* imm16: 16 bit immediate */ | |
433 | { "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16, | |
98f70fc4 | 434 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[27] } }, |
93fbbb04 GK |
435 | { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } }, |
436 | /* lmem8: 8 bit unsigned immediate low memory */ | |
437 | { "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8, | |
98f70fc4 | 438 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[28] } }, |
93fbbb04 GK |
439 | { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, |
440 | /* hmem8: 8 bit unsigned immediate high memory */ | |
441 | { "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8, | |
98f70fc4 | 442 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[29] } }, |
93fbbb04 GK |
443 | { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, |
444 | /* rel8-2: 8 bit relative address */ | |
445 | { "rel8-2", XSTORMY16_OPERAND_REL8_2, HW_H_UINT, 8, 8, | |
98f70fc4 | 446 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[30] } }, |
93fbbb04 GK |
447 | { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, |
448 | /* rel8-4: 8 bit relative address */ | |
449 | { "rel8-4", XSTORMY16_OPERAND_REL8_4, HW_H_UINT, 8, 8, | |
98f70fc4 | 450 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[31] } }, |
93fbbb04 GK |
451 | { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, |
452 | /* rel12: 12 bit relative address */ | |
453 | { "rel12", XSTORMY16_OPERAND_REL12, HW_H_UINT, 20, 12, | |
98f70fc4 | 454 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[32] } }, |
93fbbb04 GK |
455 | { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, |
456 | /* rel12a: 12 bit relative address */ | |
457 | { "rel12a", XSTORMY16_OPERAND_REL12A, HW_H_UINT, 4, 11, | |
98f70fc4 | 458 | { 0, { (const PTR) &xstormy16_cgen_ifld_table[33] } }, |
93fbbb04 GK |
459 | { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, |
460 | /* abs24: 24 bit absolute address */ | |
461 | { "abs24", XSTORMY16_OPERAND_ABS24, HW_H_UINT, 8, 24, | |
98f70fc4 | 462 | { 2, { (const PTR) &XSTORMY16_F_ABS24_MULTI_IFIELD[0] } }, |
93fbbb04 GK |
463 | { 0|A(ABS_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
464 | /* psw: program status word */ | |
465 | { "psw", XSTORMY16_OPERAND_PSW, HW_H_GR, 0, 0, | |
98f70fc4 | 466 | { 0, { (const PTR) 0 } }, |
93fbbb04 GK |
467 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
468 | /* Rpsw: N0-N3 of the program status word */ | |
469 | { "Rpsw", XSTORMY16_OPERAND_RPSW, HW_H_RPSW, 0, 0, | |
98f70fc4 | 470 | { 0, { (const PTR) 0 } }, |
93fbbb04 GK |
471 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
472 | /* sp: stack pointer */ | |
473 | { "sp", XSTORMY16_OPERAND_SP, HW_H_GR, 0, 0, | |
98f70fc4 | 474 | { 0, { (const PTR) 0 } }, |
93fbbb04 GK |
475 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
476 | /* R0: R0 */ | |
477 | { "R0", XSTORMY16_OPERAND_R0, HW_H_GR, 0, 0, | |
98f70fc4 | 478 | { 0, { (const PTR) 0 } }, |
93fbbb04 GK |
479 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
480 | /* R1: R1 */ | |
481 | { "R1", XSTORMY16_OPERAND_R1, HW_H_GR, 0, 0, | |
98f70fc4 | 482 | { 0, { (const PTR) 0 } }, |
93fbbb04 GK |
483 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
484 | /* R2: R2 */ | |
485 | { "R2", XSTORMY16_OPERAND_R2, HW_H_GR, 0, 0, | |
98f70fc4 | 486 | { 0, { (const PTR) 0 } }, |
93fbbb04 GK |
487 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
488 | /* R8: R8 */ | |
489 | { "R8", XSTORMY16_OPERAND_R8, HW_H_GR, 0, 0, | |
98f70fc4 | 490 | { 0, { (const PTR) 0 } }, |
93fbbb04 | 491 | { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
98f70fc4 AM |
492 | /* sentinel */ |
493 | { 0, 0, 0, 0, 0, | |
494 | { 0, { (const PTR) 0 } }, | |
495 | { 0, { 0 } } } | |
93fbbb04 GK |
496 | }; |
497 | ||
498 | #undef A | |
499 | ||
500 | ||
501 | /* The instruction table. */ | |
502 | ||
503 | #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) | |
504 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) | |
505 | #define A(a) (1 << CGEN_INSN_##a) | |
506 | #else | |
507 | #define A(a) (1 << CGEN_INSN_/**/a) | |
508 | #endif | |
509 | ||
510 | static const CGEN_IBASE xstormy16_cgen_insn_table[MAX_INSNS] = | |
511 | { | |
512 | /* Special null first entry. | |
513 | A `num' value of zero is thus invalid. | |
514 | Also, the special `invalid' insn resides here. */ | |
515 | { 0, 0, 0, 0, {0, {0}} }, | |
516 | /* mov$ws2 $lmem8,#$imm16 */ | |
517 | { | |
518 | XSTORMY16_INSN_MOVLMEMIMM, "movlmemimm", "mov", 32, | |
519 | { 0, { (1<<MACH_BASE) } } | |
520 | }, | |
521 | /* mov$ws2 $hmem8,#$imm16 */ | |
522 | { | |
523 | XSTORMY16_INSN_MOVHMEMIMM, "movhmemimm", "mov", 32, | |
524 | { 0, { (1<<MACH_BASE) } } | |
525 | }, | |
526 | /* mov$ws2 $Rm,$lmem8 */ | |
527 | { | |
528 | XSTORMY16_INSN_MOVLGRMEM, "movlgrmem", "mov", 16, | |
529 | { 0, { (1<<MACH_BASE) } } | |
530 | }, | |
531 | /* mov$ws2 $Rm,$hmem8 */ | |
532 | { | |
533 | XSTORMY16_INSN_MOVHGRMEM, "movhgrmem", "mov", 16, | |
534 | { 0, { (1<<MACH_BASE) } } | |
535 | }, | |
536 | /* mov$ws2 $lmem8,$Rm */ | |
537 | { | |
538 | XSTORMY16_INSN_MOVLMEMGR, "movlmemgr", "mov", 16, | |
539 | { 0, { (1<<MACH_BASE) } } | |
540 | }, | |
541 | /* mov$ws2 $hmem8,$Rm */ | |
542 | { | |
543 | XSTORMY16_INSN_MOVHMEMGR, "movhmemgr", "mov", 16, | |
544 | { 0, { (1<<MACH_BASE) } } | |
545 | }, | |
546 | /* mov$ws2 $Rdm,($Rs) */ | |
547 | { | |
548 | XSTORMY16_INSN_MOVGRGRI, "movgrgri", "mov", 16, | |
549 | { 0, { (1<<MACH_BASE) } } | |
550 | }, | |
551 | /* mov$ws2 $Rdm,($Rs++) */ | |
552 | { | |
553 | XSTORMY16_INSN_MOVGRGRIPOSTINC, "movgrgripostinc", "mov", 16, | |
554 | { 0, { (1<<MACH_BASE) } } | |
555 | }, | |
556 | /* mov$ws2 $Rdm,(--$Rs) */ | |
557 | { | |
558 | XSTORMY16_INSN_MOVGRGRIPREDEC, "movgrgripredec", "mov", 16, | |
559 | { 0, { (1<<MACH_BASE) } } | |
560 | }, | |
561 | /* mov$ws2 ($Rs),$Rdm */ | |
562 | { | |
563 | XSTORMY16_INSN_MOVGRIGR, "movgrigr", "mov", 16, | |
564 | { 0, { (1<<MACH_BASE) } } | |
565 | }, | |
566 | /* mov$ws2 ($Rs++),$Rdm */ | |
567 | { | |
568 | XSTORMY16_INSN_MOVGRIPOSTINCGR, "movgripostincgr", "mov", 16, | |
569 | { 0, { (1<<MACH_BASE) } } | |
570 | }, | |
571 | /* mov$ws2 (--$Rs),$Rdm */ | |
572 | { | |
573 | XSTORMY16_INSN_MOVGRIPREDECGR, "movgripredecgr", "mov", 16, | |
574 | { 0, { (1<<MACH_BASE) } } | |
575 | }, | |
576 | /* mov$ws2 $Rdm,($Rs,$imm12) */ | |
577 | { | |
578 | XSTORMY16_INSN_MOVGRGRII, "movgrgrii", "mov", 32, | |
579 | { 0, { (1<<MACH_BASE) } } | |
580 | }, | |
581 | /* mov$ws2 $Rdm,($Rs++,$imm12) */ | |
582 | { | |
583 | XSTORMY16_INSN_MOVGRGRIIPOSTINC, "movgrgriipostinc", "mov", 32, | |
584 | { 0, { (1<<MACH_BASE) } } | |
585 | }, | |
586 | /* mov$ws2 $Rdm,(--$Rs,$imm12) */ | |
587 | { | |
588 | XSTORMY16_INSN_MOVGRGRIIPREDEC, "movgrgriipredec", "mov", 32, | |
589 | { 0, { (1<<MACH_BASE) } } | |
590 | }, | |
591 | /* mov$ws2 ($Rs,$imm12),$Rdm */ | |
592 | { | |
593 | XSTORMY16_INSN_MOVGRIIGR, "movgriigr", "mov", 32, | |
594 | { 0, { (1<<MACH_BASE) } } | |
595 | }, | |
596 | /* mov$ws2 ($Rs++,$imm12),$Rdm */ | |
597 | { | |
598 | XSTORMY16_INSN_MOVGRIIPOSTINCGR, "movgriipostincgr", "mov", 32, | |
599 | { 0, { (1<<MACH_BASE) } } | |
600 | }, | |
601 | /* mov$ws2 (--$Rs,$imm12),$Rdm */ | |
602 | { | |
603 | XSTORMY16_INSN_MOVGRIIPREDECGR, "movgriipredecgr", "mov", 32, | |
604 | { 0, { (1<<MACH_BASE) } } | |
605 | }, | |
606 | /* mov $Rd,$Rs */ | |
607 | { | |
608 | XSTORMY16_INSN_MOVGRGR, "movgrgr", "mov", 16, | |
609 | { 0, { (1<<MACH_BASE) } } | |
610 | }, | |
611 | /* mov.w Rx,#$imm8 */ | |
612 | { | |
613 | XSTORMY16_INSN_MOVWIMM8, "movwimm8", "mov.w", 16, | |
614 | { 0, { (1<<MACH_BASE) } } | |
615 | }, | |
616 | /* mov.w $Rm,#$imm8small */ | |
617 | { | |
618 | XSTORMY16_INSN_MOVWGRIMM8, "movwgrimm8", "mov.w", 16, | |
619 | { 0, { (1<<MACH_BASE) } } | |
620 | }, | |
621 | /* mov.w $Rd,#$imm16 */ | |
622 | { | |
623 | XSTORMY16_INSN_MOVWGRIMM16, "movwgrimm16", "mov.w", 32, | |
624 | { 0, { (1<<MACH_BASE) } } | |
625 | }, | |
626 | /* mov.b $Rd,RxL */ | |
627 | { | |
628 | XSTORMY16_INSN_MOVLOWGR, "movlowgr", "mov.b", 16, | |
629 | { 0, { (1<<MACH_BASE) } } | |
630 | }, | |
631 | /* mov.b $Rd,RxH */ | |
632 | { | |
633 | XSTORMY16_INSN_MOVHIGHGR, "movhighgr", "mov.b", 16, | |
634 | { 0, { (1<<MACH_BASE) } } | |
635 | }, | |
636 | /* movf$ws2 $Rdm,($Rs) */ | |
637 | { | |
638 | XSTORMY16_INSN_MOVFGRGRI, "movfgrgri", "movf", 16, | |
639 | { 0, { (1<<MACH_BASE) } } | |
640 | }, | |
641 | /* movf$ws2 $Rdm,($Rs++) */ | |
642 | { | |
643 | XSTORMY16_INSN_MOVFGRGRIPOSTINC, "movfgrgripostinc", "movf", 16, | |
644 | { 0, { (1<<MACH_BASE) } } | |
645 | }, | |
646 | /* movf$ws2 $Rdm,(--$Rs) */ | |
647 | { | |
648 | XSTORMY16_INSN_MOVFGRGRIPREDEC, "movfgrgripredec", "movf", 16, | |
649 | { 0, { (1<<MACH_BASE) } } | |
650 | }, | |
651 | /* movf$ws2 ($Rs),$Rdm */ | |
652 | { | |
653 | XSTORMY16_INSN_MOVFGRIGR, "movfgrigr", "movf", 16, | |
654 | { 0, { (1<<MACH_BASE) } } | |
655 | }, | |
656 | /* movf$ws2 ($Rs++),$Rdm */ | |
657 | { | |
658 | XSTORMY16_INSN_MOVFGRIPOSTINCGR, "movfgripostincgr", "movf", 16, | |
659 | { 0, { (1<<MACH_BASE) } } | |
660 | }, | |
661 | /* movf$ws2 (--$Rs),$Rdm */ | |
662 | { | |
663 | XSTORMY16_INSN_MOVFGRIPREDECGR, "movfgripredecgr", "movf", 16, | |
664 | { 0, { (1<<MACH_BASE) } } | |
665 | }, | |
666 | /* movf$ws2 $Rdm,($Rb,$Rs,$imm12) */ | |
667 | { | |
668 | XSTORMY16_INSN_MOVFGRGRII, "movfgrgrii", "movf", 32, | |
669 | { 0, { (1<<MACH_BASE) } } | |
670 | }, | |
671 | /* movf$ws2 $Rdm,($Rb,$Rs++,$imm12) */ | |
672 | { | |
673 | XSTORMY16_INSN_MOVFGRGRIIPOSTINC, "movfgrgriipostinc", "movf", 32, | |
674 | { 0, { (1<<MACH_BASE) } } | |
675 | }, | |
676 | /* movf$ws2 $Rdm,($Rb,--$Rs,$imm12) */ | |
677 | { | |
678 | XSTORMY16_INSN_MOVFGRGRIIPREDEC, "movfgrgriipredec", "movf", 32, | |
679 | { 0, { (1<<MACH_BASE) } } | |
680 | }, | |
681 | /* movf$ws2 ($Rb,$Rs,$imm12),$Rdm */ | |
682 | { | |
683 | XSTORMY16_INSN_MOVFGRIIGR, "movfgriigr", "movf", 32, | |
684 | { 0, { (1<<MACH_BASE) } } | |
685 | }, | |
686 | /* movf$ws2 ($Rb,$Rs++,$imm12),$Rdm */ | |
687 | { | |
688 | XSTORMY16_INSN_MOVFGRIIPOSTINCGR, "movfgriipostincgr", "movf", 32, | |
689 | { 0, { (1<<MACH_BASE) } } | |
690 | }, | |
691 | /* movf$ws2 ($Rb,--$Rs,$imm12),$Rdm */ | |
692 | { | |
693 | XSTORMY16_INSN_MOVFGRIIPREDECGR, "movfgriipredecgr", "movf", 32, | |
694 | { 0, { (1<<MACH_BASE) } } | |
695 | }, | |
696 | /* mask $Rd,$Rs */ | |
697 | { | |
698 | XSTORMY16_INSN_MASKGRGR, "maskgrgr", "mask", 16, | |
699 | { 0, { (1<<MACH_BASE) } } | |
700 | }, | |
701 | /* mask $Rd,#$imm16 */ | |
702 | { | |
703 | XSTORMY16_INSN_MASKGRIMM16, "maskgrimm16", "mask", 32, | |
704 | { 0, { (1<<MACH_BASE) } } | |
705 | }, | |
706 | /* push $Rd */ | |
707 | { | |
708 | XSTORMY16_INSN_PUSHGR, "pushgr", "push", 16, | |
709 | { 0, { (1<<MACH_BASE) } } | |
710 | }, | |
711 | /* pop $Rd */ | |
712 | { | |
713 | XSTORMY16_INSN_POPGR, "popgr", "pop", 16, | |
714 | { 0, { (1<<MACH_BASE) } } | |
715 | }, | |
716 | /* swpn $Rd */ | |
717 | { | |
718 | XSTORMY16_INSN_SWPN, "swpn", "swpn", 16, | |
719 | { 0, { (1<<MACH_BASE) } } | |
720 | }, | |
721 | /* swpb $Rd */ | |
722 | { | |
723 | XSTORMY16_INSN_SWPB, "swpb", "swpb", 16, | |
724 | { 0, { (1<<MACH_BASE) } } | |
725 | }, | |
726 | /* swpw $Rd,$Rs */ | |
727 | { | |
728 | XSTORMY16_INSN_SWPW, "swpw", "swpw", 16, | |
729 | { 0, { (1<<MACH_BASE) } } | |
730 | }, | |
731 | /* and $Rd,$Rs */ | |
732 | { | |
733 | XSTORMY16_INSN_ANDGRGR, "andgrgr", "and", 16, | |
734 | { 0, { (1<<MACH_BASE) } } | |
735 | }, | |
736 | /* and Rx,#$imm8 */ | |
737 | { | |
738 | XSTORMY16_INSN_ANDIMM8, "andimm8", "and", 16, | |
739 | { 0, { (1<<MACH_BASE) } } | |
740 | }, | |
741 | /* and $Rd,#$imm16 */ | |
742 | { | |
743 | XSTORMY16_INSN_ANDGRIMM16, "andgrimm16", "and", 32, | |
744 | { 0, { (1<<MACH_BASE) } } | |
745 | }, | |
746 | /* or $Rd,$Rs */ | |
747 | { | |
748 | XSTORMY16_INSN_ORGRGR, "orgrgr", "or", 16, | |
749 | { 0, { (1<<MACH_BASE) } } | |
750 | }, | |
751 | /* or Rx,#$imm8 */ | |
752 | { | |
753 | XSTORMY16_INSN_ORIMM8, "orimm8", "or", 16, | |
754 | { 0, { (1<<MACH_BASE) } } | |
755 | }, | |
756 | /* or $Rd,#$imm16 */ | |
757 | { | |
758 | XSTORMY16_INSN_ORGRIMM16, "orgrimm16", "or", 32, | |
759 | { 0, { (1<<MACH_BASE) } } | |
760 | }, | |
761 | /* xor $Rd,$Rs */ | |
762 | { | |
763 | XSTORMY16_INSN_XORGRGR, "xorgrgr", "xor", 16, | |
764 | { 0, { (1<<MACH_BASE) } } | |
765 | }, | |
766 | /* xor Rx,#$imm8 */ | |
767 | { | |
768 | XSTORMY16_INSN_XORIMM8, "xorimm8", "xor", 16, | |
769 | { 0, { (1<<MACH_BASE) } } | |
770 | }, | |
771 | /* xor $Rd,#$imm16 */ | |
772 | { | |
773 | XSTORMY16_INSN_XORGRIMM16, "xorgrimm16", "xor", 32, | |
774 | { 0, { (1<<MACH_BASE) } } | |
775 | }, | |
776 | /* not $Rd */ | |
777 | { | |
778 | XSTORMY16_INSN_NOTGR, "notgr", "not", 16, | |
779 | { 0, { (1<<MACH_BASE) } } | |
780 | }, | |
781 | /* add $Rd,$Rs */ | |
782 | { | |
783 | XSTORMY16_INSN_ADDGRGR, "addgrgr", "add", 16, | |
784 | { 0, { (1<<MACH_BASE) } } | |
785 | }, | |
786 | /* add $Rd,#$imm4 */ | |
787 | { | |
788 | XSTORMY16_INSN_ADDGRIMM4, "addgrimm4", "add", 16, | |
789 | { 0, { (1<<MACH_BASE) } } | |
790 | }, | |
791 | /* add Rx,#$imm8 */ | |
792 | { | |
793 | XSTORMY16_INSN_ADDIMM8, "addimm8", "add", 16, | |
794 | { 0, { (1<<MACH_BASE) } } | |
795 | }, | |
796 | /* add $Rd,#$imm16 */ | |
797 | { | |
798 | XSTORMY16_INSN_ADDGRIMM16, "addgrimm16", "add", 32, | |
799 | { 0, { (1<<MACH_BASE) } } | |
800 | }, | |
801 | /* adc $Rd,$Rs */ | |
802 | { | |
803 | XSTORMY16_INSN_ADCGRGR, "adcgrgr", "adc", 16, | |
804 | { 0, { (1<<MACH_BASE) } } | |
805 | }, | |
806 | /* adc $Rd,#$imm4 */ | |
807 | { | |
808 | XSTORMY16_INSN_ADCGRIMM4, "adcgrimm4", "adc", 16, | |
809 | { 0, { (1<<MACH_BASE) } } | |
810 | }, | |
811 | /* adc Rx,#$imm8 */ | |
812 | { | |
813 | XSTORMY16_INSN_ADCIMM8, "adcimm8", "adc", 16, | |
814 | { 0, { (1<<MACH_BASE) } } | |
815 | }, | |
816 | /* adc $Rd,#$imm16 */ | |
817 | { | |
818 | XSTORMY16_INSN_ADCGRIMM16, "adcgrimm16", "adc", 32, | |
819 | { 0, { (1<<MACH_BASE) } } | |
820 | }, | |
821 | /* sub $Rd,$Rs */ | |
822 | { | |
823 | XSTORMY16_INSN_SUBGRGR, "subgrgr", "sub", 16, | |
824 | { 0, { (1<<MACH_BASE) } } | |
825 | }, | |
826 | /* sub $Rd,#$imm4 */ | |
827 | { | |
828 | XSTORMY16_INSN_SUBGRIMM4, "subgrimm4", "sub", 16, | |
829 | { 0, { (1<<MACH_BASE) } } | |
830 | }, | |
831 | /* sub Rx,#$imm8 */ | |
832 | { | |
833 | XSTORMY16_INSN_SUBIMM8, "subimm8", "sub", 16, | |
834 | { 0, { (1<<MACH_BASE) } } | |
835 | }, | |
836 | /* sub $Rd,#$imm16 */ | |
837 | { | |
838 | XSTORMY16_INSN_SUBGRIMM16, "subgrimm16", "sub", 32, | |
839 | { 0, { (1<<MACH_BASE) } } | |
840 | }, | |
841 | /* sbc $Rd,$Rs */ | |
842 | { | |
843 | XSTORMY16_INSN_SBCGRGR, "sbcgrgr", "sbc", 16, | |
844 | { 0, { (1<<MACH_BASE) } } | |
845 | }, | |
846 | /* sbc $Rd,#$imm4 */ | |
847 | { | |
848 | XSTORMY16_INSN_SBCGRIMM4, "sbcgrimm4", "sbc", 16, | |
849 | { 0, { (1<<MACH_BASE) } } | |
850 | }, | |
851 | /* sbc Rx,#$imm8 */ | |
852 | { | |
853 | XSTORMY16_INSN_SBCGRIMM8, "sbcgrimm8", "sbc", 16, | |
854 | { 0, { (1<<MACH_BASE) } } | |
855 | }, | |
856 | /* sbc $Rd,#$imm16 */ | |
857 | { | |
858 | XSTORMY16_INSN_SBCGRIMM16, "sbcgrimm16", "sbc", 32, | |
859 | { 0, { (1<<MACH_BASE) } } | |
860 | }, | |
861 | /* inc $Rd,#$imm2 */ | |
862 | { | |
863 | XSTORMY16_INSN_INCGRIMM2, "incgrimm2", "inc", 16, | |
864 | { 0, { (1<<MACH_BASE) } } | |
865 | }, | |
866 | /* dec $Rd,#$imm2 */ | |
867 | { | |
868 | XSTORMY16_INSN_DECGRIMM2, "decgrimm2", "dec", 16, | |
869 | { 0, { (1<<MACH_BASE) } } | |
870 | }, | |
871 | /* rrc $Rd,$Rs */ | |
872 | { | |
873 | XSTORMY16_INSN_RRCGRGR, "rrcgrgr", "rrc", 16, | |
874 | { 0, { (1<<MACH_BASE) } } | |
875 | }, | |
876 | /* rrc $Rd,#$imm4 */ | |
877 | { | |
878 | XSTORMY16_INSN_RRCGRIMM4, "rrcgrimm4", "rrc", 16, | |
879 | { 0, { (1<<MACH_BASE) } } | |
880 | }, | |
881 | /* rlc $Rd,$Rs */ | |
882 | { | |
883 | XSTORMY16_INSN_RLCGRGR, "rlcgrgr", "rlc", 16, | |
884 | { 0, { (1<<MACH_BASE) } } | |
885 | }, | |
886 | /* rlc $Rd,#$imm4 */ | |
887 | { | |
888 | XSTORMY16_INSN_RLCGRIMM4, "rlcgrimm4", "rlc", 16, | |
889 | { 0, { (1<<MACH_BASE) } } | |
890 | }, | |
891 | /* shr $Rd,$Rs */ | |
892 | { | |
893 | XSTORMY16_INSN_SHRGRGR, "shrgrgr", "shr", 16, | |
894 | { 0, { (1<<MACH_BASE) } } | |
895 | }, | |
896 | /* shr $Rd,#$imm4 */ | |
897 | { | |
898 | XSTORMY16_INSN_SHRGRIMM, "shrgrimm", "shr", 16, | |
899 | { 0, { (1<<MACH_BASE) } } | |
900 | }, | |
901 | /* shl $Rd,$Rs */ | |
902 | { | |
903 | XSTORMY16_INSN_SHLGRGR, "shlgrgr", "shl", 16, | |
904 | { 0, { (1<<MACH_BASE) } } | |
905 | }, | |
906 | /* shl $Rd,#$imm4 */ | |
907 | { | |
908 | XSTORMY16_INSN_SHLGRIMM, "shlgrimm", "shl", 16, | |
909 | { 0, { (1<<MACH_BASE) } } | |
910 | }, | |
911 | /* asr $Rd,$Rs */ | |
912 | { | |
913 | XSTORMY16_INSN_ASRGRGR, "asrgrgr", "asr", 16, | |
914 | { 0, { (1<<MACH_BASE) } } | |
915 | }, | |
916 | /* asr $Rd,#$imm4 */ | |
917 | { | |
918 | XSTORMY16_INSN_ASRGRIMM, "asrgrimm", "asr", 16, | |
919 | { 0, { (1<<MACH_BASE) } } | |
920 | }, | |
921 | /* set1 $Rd,#$imm4 */ | |
922 | { | |
923 | XSTORMY16_INSN_SET1GRIMM, "set1grimm", "set1", 16, | |
924 | { 0, { (1<<MACH_BASE) } } | |
925 | }, | |
926 | /* set1 $Rd,$Rs */ | |
927 | { | |
928 | XSTORMY16_INSN_SET1GRGR, "set1grgr", "set1", 16, | |
929 | { 0, { (1<<MACH_BASE) } } | |
930 | }, | |
931 | /* set1 $lmem8,#$imm3 */ | |
932 | { | |
933 | XSTORMY16_INSN_SET1LMEMIMM, "set1lmemimm", "set1", 16, | |
934 | { 0, { (1<<MACH_BASE) } } | |
935 | }, | |
936 | /* set1 $hmem8,#$imm3 */ | |
937 | { | |
938 | XSTORMY16_INSN_SET1HMEMIMM, "set1hmemimm", "set1", 16, | |
939 | { 0, { (1<<MACH_BASE) } } | |
940 | }, | |
941 | /* clr1 $Rd,#$imm4 */ | |
942 | { | |
943 | XSTORMY16_INSN_CLR1GRIMM, "clr1grimm", "clr1", 16, | |
944 | { 0, { (1<<MACH_BASE) } } | |
945 | }, | |
946 | /* clr1 $Rd,$Rs */ | |
947 | { | |
948 | XSTORMY16_INSN_CLR1GRGR, "clr1grgr", "clr1", 16, | |
949 | { 0, { (1<<MACH_BASE) } } | |
950 | }, | |
951 | /* clr1 $lmem8,#$imm3 */ | |
952 | { | |
953 | XSTORMY16_INSN_CLR1LMEMIMM, "clr1lmemimm", "clr1", 16, | |
954 | { 0, { (1<<MACH_BASE) } } | |
955 | }, | |
956 | /* clr1 $hmem8,#$imm3 */ | |
957 | { | |
958 | XSTORMY16_INSN_CLR1HMEMIMM, "clr1hmemimm", "clr1", 16, | |
959 | { 0, { (1<<MACH_BASE) } } | |
960 | }, | |
961 | /* cbw $Rd */ | |
962 | { | |
963 | XSTORMY16_INSN_CBWGR, "cbwgr", "cbw", 16, | |
964 | { 0, { (1<<MACH_BASE) } } | |
965 | }, | |
966 | /* rev $Rd */ | |
967 | { | |
968 | XSTORMY16_INSN_REVGR, "revgr", "rev", 16, | |
969 | { 0, { (1<<MACH_BASE) } } | |
970 | }, | |
971 | /* b$bcond5 $Rd,$Rs,$rel12 */ | |
972 | { | |
973 | XSTORMY16_INSN_BCCGRGR, "bccgrgr", "b", 32, | |
974 | { 0|A(COND_CTI), { (1<<MACH_BASE) } } | |
975 | }, | |
976 | /* b$bcond5 $Rm,#$imm8,$rel12 */ | |
977 | { | |
978 | XSTORMY16_INSN_BCCGRIMM8, "bccgrimm8", "b", 32, | |
979 | { 0|A(COND_CTI), { (1<<MACH_BASE) } } | |
980 | }, | |
981 | /* b$bcond2 Rx,#$imm16,${rel8-4} */ | |
982 | { | |
983 | XSTORMY16_INSN_BCCIMM16, "bccimm16", "b", 32, | |
984 | { 0|A(COND_CTI), { (1<<MACH_BASE) } } | |
985 | }, | |
986 | /* bn $Rd,#$imm4,$rel12 */ | |
987 | { | |
988 | XSTORMY16_INSN_BNGRIMM4, "bngrimm4", "bn", 32, | |
989 | { 0|A(COND_CTI), { (1<<MACH_BASE) } } | |
990 | }, | |
991 | /* bn $Rd,$Rs,$rel12 */ | |
992 | { | |
993 | XSTORMY16_INSN_BNGRGR, "bngrgr", "bn", 32, | |
994 | { 0|A(COND_CTI), { (1<<MACH_BASE) } } | |
995 | }, | |
996 | /* bn $lmem8,#$imm3b,$rel12 */ | |
997 | { | |
998 | XSTORMY16_INSN_BNLMEMIMM, "bnlmemimm", "bn", 32, | |
999 | { 0|A(COND_CTI), { (1<<MACH_BASE) } } | |
1000 | }, | |
1001 | /* bn $hmem8,#$imm3b,$rel12 */ | |
1002 | { | |
1003 | XSTORMY16_INSN_BNHMEMIMM, "bnhmemimm", "bn", 32, | |
1004 | { 0|A(COND_CTI), { (1<<MACH_BASE) } } | |
1005 | }, | |
1006 | /* bp $Rd,#$imm4,$rel12 */ | |
1007 | { | |
1008 | XSTORMY16_INSN_BPGRIMM4, "bpgrimm4", "bp", 32, | |
1009 | { 0|A(COND_CTI), { (1<<MACH_BASE) } } | |
1010 | }, | |
1011 | /* bp $Rd,$Rs,$rel12 */ | |
1012 | { | |
1013 | XSTORMY16_INSN_BPGRGR, "bpgrgr", "bp", 32, | |
1014 | { 0|A(COND_CTI), { (1<<MACH_BASE) } } | |
1015 | }, | |
1016 | /* bp $lmem8,#$imm3b,$rel12 */ | |
1017 | { | |
1018 | XSTORMY16_INSN_BPLMEMIMM, "bplmemimm", "bp", 32, | |
1019 | { 0|A(COND_CTI), { (1<<MACH_BASE) } } | |
1020 | }, | |
1021 | /* bp $hmem8,#$imm3b,$rel12 */ | |
1022 | { | |
1023 | XSTORMY16_INSN_BPHMEMIMM, "bphmemimm", "bp", 32, | |
1024 | { 0|A(COND_CTI), { (1<<MACH_BASE) } } | |
1025 | }, | |
1026 | /* b$bcond2 ${rel8-2} */ | |
1027 | { | |
1028 | XSTORMY16_INSN_BCC, "bcc", "b", 16, | |
1029 | { 0|A(COND_CTI), { (1<<MACH_BASE) } } | |
1030 | }, | |
1031 | /* br $Rd */ | |
1032 | { | |
1033 | XSTORMY16_INSN_BGR, "bgr", "br", 16, | |
1034 | { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } | |
1035 | }, | |
1036 | /* br $rel12a */ | |
1037 | { | |
1038 | XSTORMY16_INSN_BR, "br", "br", 16, | |
1039 | { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } | |
1040 | }, | |
1041 | /* jmp $Rbj,$Rd */ | |
1042 | { | |
1043 | XSTORMY16_INSN_JMP, "jmp", "jmp", 16, | |
1044 | { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } | |
1045 | }, | |
1046 | /* jmpf $abs24 */ | |
1047 | { | |
1048 | XSTORMY16_INSN_JMPF, "jmpf", "jmpf", 32, | |
1049 | { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } | |
1050 | }, | |
1051 | /* callr $Rd */ | |
1052 | { | |
1053 | XSTORMY16_INSN_CALLRGR, "callrgr", "callr", 16, | |
1054 | { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } | |
1055 | }, | |
1056 | /* callr $rel12a */ | |
1057 | { | |
1058 | XSTORMY16_INSN_CALLRIMM, "callrimm", "callr", 16, | |
1059 | { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } | |
1060 | }, | |
1061 | /* call $Rbj,$Rd */ | |
1062 | { | |
1063 | XSTORMY16_INSN_CALLGR, "callgr", "call", 16, | |
1064 | { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } | |
1065 | }, | |
1066 | /* callf $abs24 */ | |
1067 | { | |
1068 | XSTORMY16_INSN_CALLFIMM, "callfimm", "callf", 32, | |
1069 | { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } | |
1070 | }, | |
1071 | /* icallr $Rd */ | |
1072 | { | |
1073 | XSTORMY16_INSN_ICALLRGR, "icallrgr", "icallr", 16, | |
1074 | { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } | |
1075 | }, | |
1076 | /* icall $Rbj,$Rd */ | |
1077 | { | |
1078 | XSTORMY16_INSN_ICALLGR, "icallgr", "icall", 16, | |
1079 | { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } | |
1080 | }, | |
1081 | /* icallf $abs24 */ | |
1082 | { | |
1083 | XSTORMY16_INSN_ICALLFIMM, "icallfimm", "icallf", 32, | |
1084 | { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } | |
1085 | }, | |
1086 | /* iret */ | |
1087 | { | |
1088 | XSTORMY16_INSN_IRET, "iret", "iret", 16, | |
1089 | { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } | |
1090 | }, | |
1091 | /* ret */ | |
1092 | { | |
1093 | XSTORMY16_INSN_RET, "ret", "ret", 16, | |
1094 | { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } | |
1095 | }, | |
1096 | /* mul */ | |
1097 | { | |
1098 | XSTORMY16_INSN_MUL, "mul", "mul", 16, | |
1099 | { 0, { (1<<MACH_BASE) } } | |
1100 | }, | |
1101 | /* div */ | |
1102 | { | |
1103 | XSTORMY16_INSN_DIV, "div", "div", 16, | |
1104 | { 0, { (1<<MACH_BASE) } } | |
1105 | }, | |
193eb15d DD |
1106 | /* sdiv */ |
1107 | { | |
1108 | XSTORMY16_INSN_SDIV, "sdiv", "sdiv", 16, | |
1109 | { 0, { (1<<MACH_BASE) } } | |
1110 | }, | |
1111 | /* sdivlh */ | |
1112 | { | |
1113 | XSTORMY16_INSN_SDIVLH, "sdivlh", "sdivlh", 16, | |
1114 | { 0, { (1<<MACH_BASE) } } | |
1115 | }, | |
1116 | /* divlh */ | |
1117 | { | |
1118 | XSTORMY16_INSN_DIVLH, "divlh", "divlh", 16, | |
1119 | { 0, { (1<<MACH_BASE) } } | |
1120 | }, | |
93fbbb04 GK |
1121 | /* nop */ |
1122 | { | |
1123 | XSTORMY16_INSN_NOP, "nop", "nop", 16, | |
1124 | { 0, { (1<<MACH_BASE) } } | |
1125 | }, | |
1126 | /* halt */ | |
1127 | { | |
1128 | XSTORMY16_INSN_HALT, "halt", "halt", 16, | |
1129 | { 0, { (1<<MACH_BASE) } } | |
1130 | }, | |
1131 | /* hold */ | |
1132 | { | |
1133 | XSTORMY16_INSN_HOLD, "hold", "hold", 16, | |
1134 | { 0, { (1<<MACH_BASE) } } | |
1135 | }, | |
1951c6f7 MG |
1136 | /* holdx */ |
1137 | { | |
1138 | XSTORMY16_INSN_HOLDX, "holdx", "holdx", 16, | |
1139 | { 0, { (1<<MACH_BASE) } } | |
1140 | }, | |
93fbbb04 GK |
1141 | /* brk */ |
1142 | { | |
1143 | XSTORMY16_INSN_BRK, "brk", "brk", 16, | |
1144 | { 0, { (1<<MACH_BASE) } } | |
1145 | }, | |
1146 | /* --unused-- */ | |
1147 | { | |
1148 | XSTORMY16_INSN_SYSCALL, "syscall", "--unused--", 16, | |
1149 | { 0, { (1<<MACH_BASE) } } | |
1150 | }, | |
1151 | }; | |
1152 | ||
1153 | #undef OP | |
1154 | #undef A | |
1155 | ||
1156 | /* Initialize anything needed to be done once, before any cpu_open call. */ | |
1157 | static void init_tables PARAMS ((void)); | |
1158 | ||
1159 | static void | |
1160 | init_tables () | |
1161 | { | |
1162 | } | |
1163 | ||
1164 | static const CGEN_MACH * lookup_mach_via_bfd_name | |
1165 | PARAMS ((const CGEN_MACH *, const char *)); | |
1166 | static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); | |
1167 | static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); | |
1168 | static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); | |
1169 | static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); | |
1170 | static void xstormy16_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); | |
1171 | ||
1172 | /* Subroutine of xstormy16_cgen_cpu_open to look up a mach via its bfd name. */ | |
1173 | ||
1174 | static const CGEN_MACH * | |
1175 | lookup_mach_via_bfd_name (table, name) | |
1176 | const CGEN_MACH *table; | |
1177 | const char *name; | |
1178 | { | |
1179 | while (table->name) | |
1180 | { | |
1181 | if (strcmp (name, table->bfd_name) == 0) | |
1182 | return table; | |
1183 | ++table; | |
1184 | } | |
1185 | abort (); | |
1186 | } | |
1187 | ||
1188 | /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */ | |
1189 | ||
1190 | static void | |
1191 | build_hw_table (cd) | |
1192 | CGEN_CPU_TABLE *cd; | |
1193 | { | |
1194 | int i; | |
1195 | int machs = cd->machs; | |
1196 | const CGEN_HW_ENTRY *init = & xstormy16_cgen_hw_table[0]; | |
1197 | /* MAX_HW is only an upper bound on the number of selected entries. | |
1198 | However each entry is indexed by it's enum so there can be holes in | |
1199 | the table. */ | |
1200 | const CGEN_HW_ENTRY **selected = | |
1201 | (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); | |
1202 | ||
1203 | cd->hw_table.init_entries = init; | |
1204 | cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); | |
1205 | memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); | |
1206 | /* ??? For now we just use machs to determine which ones we want. */ | |
1207 | for (i = 0; init[i].name != NULL; ++i) | |
1208 | if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) | |
1209 | & machs) | |
1210 | selected[init[i].type] = &init[i]; | |
1211 | cd->hw_table.entries = selected; | |
1212 | cd->hw_table.num_entries = MAX_HW; | |
1213 | } | |
1214 | ||
1215 | /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */ | |
1216 | ||
1217 | static void | |
1218 | build_ifield_table (cd) | |
1219 | CGEN_CPU_TABLE *cd; | |
1220 | { | |
1221 | cd->ifld_table = & xstormy16_cgen_ifld_table[0]; | |
1222 | } | |
1223 | ||
1224 | /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */ | |
1225 | ||
1226 | static void | |
1227 | build_operand_table (cd) | |
1228 | CGEN_CPU_TABLE *cd; | |
1229 | { | |
1230 | int i; | |
1231 | int machs = cd->machs; | |
1232 | const CGEN_OPERAND *init = & xstormy16_cgen_operand_table[0]; | |
1233 | /* MAX_OPERANDS is only an upper bound on the number of selected entries. | |
1234 | However each entry is indexed by it's enum so there can be holes in | |
1235 | the table. */ | |
1236 | const CGEN_OPERAND **selected = | |
1237 | (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); | |
1238 | ||
1239 | cd->operand_table.init_entries = init; | |
1240 | cd->operand_table.entry_size = sizeof (CGEN_OPERAND); | |
1241 | memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); | |
1242 | /* ??? For now we just use mach to determine which ones we want. */ | |
1243 | for (i = 0; init[i].name != NULL; ++i) | |
1244 | if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) | |
1245 | & machs) | |
1246 | selected[init[i].type] = &init[i]; | |
1247 | cd->operand_table.entries = selected; | |
1248 | cd->operand_table.num_entries = MAX_OPERANDS; | |
1249 | } | |
1250 | ||
1251 | /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. | |
1252 | ??? This could leave out insns not supported by the specified mach/isa, | |
1253 | but that would cause errors like "foo only supported by bar" to become | |
1254 | "unknown insn", so for now we include all insns and require the app to | |
1255 | do the checking later. | |
1256 | ??? On the other hand, parsing of such insns may require their hardware or | |
1257 | operand elements to be in the table [which they mightn't be]. */ | |
1258 | ||
1259 | static void | |
1260 | build_insn_table (cd) | |
1261 | CGEN_CPU_TABLE *cd; | |
1262 | { | |
1263 | int i; | |
1264 | const CGEN_IBASE *ib = & xstormy16_cgen_insn_table[0]; | |
1265 | CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); | |
1266 | ||
1267 | memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); | |
1268 | for (i = 0; i < MAX_INSNS; ++i) | |
1269 | insns[i].base = &ib[i]; | |
1270 | cd->insn_table.init_entries = insns; | |
1271 | cd->insn_table.entry_size = sizeof (CGEN_IBASE); | |
1272 | cd->insn_table.num_init_entries = MAX_INSNS; | |
1273 | } | |
1274 | ||
1275 | /* Subroutine of xstormy16_cgen_cpu_open to rebuild the tables. */ | |
1276 | ||
1277 | static void | |
1278 | xstormy16_cgen_rebuild_tables (cd) | |
1279 | CGEN_CPU_TABLE *cd; | |
1280 | { | |
1281 | int i; | |
1282 | unsigned int isas = cd->isas; | |
1283 | unsigned int machs = cd->machs; | |
1284 | ||
1285 | cd->int_insn_p = CGEN_INT_INSN_P; | |
1286 | ||
1287 | /* Data derived from the isa spec. */ | |
1288 | #define UNSET (CGEN_SIZE_UNKNOWN + 1) | |
1289 | cd->default_insn_bitsize = UNSET; | |
1290 | cd->base_insn_bitsize = UNSET; | |
1291 | cd->min_insn_bitsize = 65535; /* some ridiculously big number */ | |
1292 | cd->max_insn_bitsize = 0; | |
1293 | for (i = 0; i < MAX_ISAS; ++i) | |
1294 | if (((1 << i) & isas) != 0) | |
1295 | { | |
1296 | const CGEN_ISA *isa = & xstormy16_cgen_isa_table[i]; | |
1297 | ||
9a2e995d GH |
1298 | /* Default insn sizes of all selected isas must be |
1299 | equal or we set the result to 0, meaning "unknown". */ | |
93fbbb04 GK |
1300 | if (cd->default_insn_bitsize == UNSET) |
1301 | cd->default_insn_bitsize = isa->default_insn_bitsize; | |
1302 | else if (isa->default_insn_bitsize == cd->default_insn_bitsize) | |
1303 | ; /* this is ok */ | |
1304 | else | |
1305 | cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; | |
1306 | ||
9a2e995d GH |
1307 | /* Base insn sizes of all selected isas must be equal |
1308 | or we set the result to 0, meaning "unknown". */ | |
93fbbb04 GK |
1309 | if (cd->base_insn_bitsize == UNSET) |
1310 | cd->base_insn_bitsize = isa->base_insn_bitsize; | |
1311 | else if (isa->base_insn_bitsize == cd->base_insn_bitsize) | |
1312 | ; /* this is ok */ | |
1313 | else | |
1314 | cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; | |
1315 | ||
1316 | /* Set min,max insn sizes. */ | |
1317 | if (isa->min_insn_bitsize < cd->min_insn_bitsize) | |
1318 | cd->min_insn_bitsize = isa->min_insn_bitsize; | |
1319 | if (isa->max_insn_bitsize > cd->max_insn_bitsize) | |
1320 | cd->max_insn_bitsize = isa->max_insn_bitsize; | |
1321 | } | |
1322 | ||
1323 | /* Data derived from the mach spec. */ | |
1324 | for (i = 0; i < MAX_MACHS; ++i) | |
1325 | if (((1 << i) & machs) != 0) | |
1326 | { | |
1327 | const CGEN_MACH *mach = & xstormy16_cgen_mach_table[i]; | |
1328 | ||
1329 | if (mach->insn_chunk_bitsize != 0) | |
1330 | { | |
1331 | if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) | |
1332 | { | |
1333 | fprintf (stderr, "xstormy16_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", | |
1334 | cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); | |
1335 | abort (); | |
1336 | } | |
1337 | ||
1338 | cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; | |
1339 | } | |
1340 | } | |
1341 | ||
1342 | /* Determine which hw elements are used by MACH. */ | |
1343 | build_hw_table (cd); | |
1344 | ||
1345 | /* Build the ifield table. */ | |
1346 | build_ifield_table (cd); | |
1347 | ||
1348 | /* Determine which operands are used by MACH/ISA. */ | |
1349 | build_operand_table (cd); | |
1350 | ||
1351 | /* Build the instruction table. */ | |
1352 | build_insn_table (cd); | |
1353 | } | |
1354 | ||
1355 | /* Initialize a cpu table and return a descriptor. | |
1356 | It's much like opening a file, and must be the first function called. | |
1357 | The arguments are a set of (type/value) pairs, terminated with | |
1358 | CGEN_CPU_OPEN_END. | |
1359 | ||
1360 | Currently supported values: | |
1361 | CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr | |
1362 | CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr | |
1363 | CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name | |
1364 | CGEN_CPU_OPEN_ENDIAN: specify endian choice | |
1365 | CGEN_CPU_OPEN_END: terminates arguments | |
1366 | ||
1367 | ??? Simultaneous multiple isas might not make sense, but it's not (yet) | |
1368 | precluded. | |
1369 | ||
1370 | ??? We only support ISO C stdargs here, not K&R. | |
1371 | Laziness, plus experiment to see if anything requires K&R - eventually | |
1372 | K&R will no longer be supported - e.g. GDB is currently trying this. */ | |
1373 | ||
1374 | CGEN_CPU_DESC | |
1375 | xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) | |
1376 | { | |
1377 | CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); | |
1378 | static int init_p; | |
1379 | unsigned int isas = 0; /* 0 = "unspecified" */ | |
1380 | unsigned int machs = 0; /* 0 = "unspecified" */ | |
1381 | enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; | |
1382 | va_list ap; | |
1383 | ||
1384 | if (! init_p) | |
1385 | { | |
1386 | init_tables (); | |
1387 | init_p = 1; | |
1388 | } | |
1389 | ||
1390 | memset (cd, 0, sizeof (*cd)); | |
1391 | ||
1392 | va_start (ap, arg_type); | |
1393 | while (arg_type != CGEN_CPU_OPEN_END) | |
1394 | { | |
1395 | switch (arg_type) | |
1396 | { | |
1397 | case CGEN_CPU_OPEN_ISAS : | |
1398 | isas = va_arg (ap, unsigned int); | |
1399 | break; | |
1400 | case CGEN_CPU_OPEN_MACHS : | |
1401 | machs = va_arg (ap, unsigned int); | |
1402 | break; | |
1403 | case CGEN_CPU_OPEN_BFDMACH : | |
1404 | { | |
1405 | const char *name = va_arg (ap, const char *); | |
1406 | const CGEN_MACH *mach = | |
1407 | lookup_mach_via_bfd_name (xstormy16_cgen_mach_table, name); | |
1408 | ||
1409 | machs |= 1 << mach->num; | |
1410 | break; | |
1411 | } | |
1412 | case CGEN_CPU_OPEN_ENDIAN : | |
1413 | endian = va_arg (ap, enum cgen_endian); | |
1414 | break; | |
1415 | default : | |
1416 | fprintf (stderr, "xstormy16_cgen_cpu_open: unsupported argument `%d'\n", | |
1417 | arg_type); | |
1418 | abort (); /* ??? return NULL? */ | |
1419 | } | |
1420 | arg_type = va_arg (ap, enum cgen_cpu_open_arg); | |
1421 | } | |
1422 | va_end (ap); | |
1423 | ||
1424 | /* mach unspecified means "all" */ | |
1425 | if (machs == 0) | |
1426 | machs = (1 << MAX_MACHS) - 1; | |
1427 | /* base mach is always selected */ | |
1428 | machs |= 1; | |
1429 | /* isa unspecified means "all" */ | |
1430 | if (isas == 0) | |
1431 | isas = (1 << MAX_ISAS) - 1; | |
1432 | if (endian == CGEN_ENDIAN_UNKNOWN) | |
1433 | { | |
1434 | /* ??? If target has only one, could have a default. */ | |
1435 | fprintf (stderr, "xstormy16_cgen_cpu_open: no endianness specified\n"); | |
1436 | abort (); | |
1437 | } | |
1438 | ||
1439 | cd->isas = isas; | |
1440 | cd->machs = machs; | |
1441 | cd->endian = endian; | |
1442 | /* FIXME: for the sparc case we can determine insn-endianness statically. | |
1443 | The worry here is where both data and insn endian can be independently | |
1444 | chosen, in which case this function will need another argument. | |
1445 | Actually, will want to allow for more arguments in the future anyway. */ | |
1446 | cd->insn_endian = endian; | |
1447 | ||
1448 | /* Table (re)builder. */ | |
1449 | cd->rebuild_tables = xstormy16_cgen_rebuild_tables; | |
1450 | xstormy16_cgen_rebuild_tables (cd); | |
1451 | ||
1452 | /* Default to not allowing signed overflow. */ | |
1453 | cd->signed_overflow_ok_p = 0; | |
1454 | ||
1455 | return (CGEN_CPU_DESC) cd; | |
1456 | } | |
1457 | ||
1458 | /* Cover fn to xstormy16_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. | |
1459 | MACH_NAME is the bfd name of the mach. */ | |
1460 | ||
1461 | CGEN_CPU_DESC | |
1462 | xstormy16_cgen_cpu_open_1 (mach_name, endian) | |
1463 | const char *mach_name; | |
1464 | enum cgen_endian endian; | |
1465 | { | |
1466 | return xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, | |
1467 | CGEN_CPU_OPEN_ENDIAN, endian, | |
1468 | CGEN_CPU_OPEN_END); | |
1469 | } | |
1470 | ||
1471 | /* Close a cpu table. | |
1472 | ??? This can live in a machine independent file, but there's currently | |
1473 | no place to put this file (there's no libcgen). libopcodes is the wrong | |
1474 | place as some simulator ports use this but they don't use libopcodes. */ | |
1475 | ||
1476 | void | |
1477 | xstormy16_cgen_cpu_close (cd) | |
1478 | CGEN_CPU_DESC cd; | |
1479 | { | |
a978a3e5 | 1480 | unsigned int i; |
98f70fc4 | 1481 | const CGEN_INSN *insns; |
a978a3e5 NC |
1482 | |
1483 | if (cd->macro_insn_table.init_entries) | |
1484 | { | |
1485 | insns = cd->macro_insn_table.init_entries; | |
1486 | for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) | |
1487 | { | |
1488 | if (CGEN_INSN_RX ((insns))) | |
98f70fc4 | 1489 | regfree (CGEN_INSN_RX (insns)); |
a978a3e5 NC |
1490 | } |
1491 | } | |
1492 | ||
1493 | if (cd->insn_table.init_entries) | |
1494 | { | |
1495 | insns = cd->insn_table.init_entries; | |
1496 | for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) | |
1497 | { | |
1498 | if (CGEN_INSN_RX (insns)) | |
98f70fc4 | 1499 | regfree (CGEN_INSN_RX (insns)); |
a978a3e5 NC |
1500 | } |
1501 | } | |
1502 | ||
1503 | ||
1504 | ||
1505 | if (cd->macro_insn_table.init_entries) | |
1506 | free ((CGEN_INSN *) cd->macro_insn_table.init_entries); | |
1507 | ||
93fbbb04 GK |
1508 | if (cd->insn_table.init_entries) |
1509 | free ((CGEN_INSN *) cd->insn_table.init_entries); | |
a978a3e5 | 1510 | |
93fbbb04 GK |
1511 | if (cd->hw_table.entries) |
1512 | free ((CGEN_HW_ENTRY *) cd->hw_table.entries); | |
a978a3e5 NC |
1513 | |
1514 | if (cd->operand_table.entries) | |
1515 | free ((CGEN_HW_ENTRY *) cd->operand_table.entries); | |
1516 | ||
93fbbb04 GK |
1517 | free (cd); |
1518 | } | |
1519 |