Commit | Line | Data |
---|---|---|
963201cf JW |
1 | 2016-12-13 Jim Wilson <jim.wilson@linaro.org> |
2 | ||
3 | * simulator.c (NEG, POS): Move before set_flags_for_add64. | |
4 | (set_flags_for_add64): Replace with a modified copy of | |
5 | set_flags_for_sub64. | |
6 | ||
668650d5 JW |
7 | 2016-12-03 Jim Wilson <jim.wilson@linaro.org> |
8 | ||
9 | * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting. | |
10 | (dexTestBranchImmediate): Shift high bit of pos by 5 not 4. | |
11 | ||
88ddd4a1 JW |
12 | 2016-12-01 Jim Wilson <jim.wilson@linaro.org> |
13 | ||
88256e71 | 14 | * simulator.c (fsturs): Switch use of rn and st variables. |
88ddd4a1 JW |
15 | (fsturd, fsturq): Likewise |
16 | ||
5357150c MF |
17 | 2016-08-15 Mike Frysinger <vapier@gentoo.org> |
18 | ||
19 | * interp.c: Include bfd.h. | |
20 | (symcount, symtab, aarch64_get_sym_value): Delete. | |
21 | (remove_useless_symbols): Change count type to long. | |
22 | (aarch64_get_func): Add SIM_DESC to arg list. Add symcount | |
23 | and symtab local variables. | |
24 | (sim_create_inferior): Delete storage. Replace symbol code | |
25 | with a call to trace_load_symbols. | |
26 | * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h | |
27 | includes. | |
28 | (aarch64_get_heap_start): Change aarch64_get_sym_value to | |
29 | trace_sym_value. | |
30 | * memory.h: Delete bfd.h include. | |
31 | (mem_add_blk): Delete unused prototype. | |
32 | * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func. | |
33 | * simulator.c (aarch64_get_func): Add SIM_DESC to arg list. | |
34 | (aarch64_get_sym_value): Delete. | |
35 | ||
b14bdb3b NC |
36 | 2016-08-12 Nick Clifton <nickc@redhat.com> |
37 | ||
38 | * simulator.c (aarch64_step): Revert pervious delta. | |
39 | (aarch64_run): Call sim_events_tick after each | |
40 | instruction is simulated, and if necessary call | |
41 | sim_events_process. | |
42 | * simulator.h: Revert previous delta. | |
43 | ||
6a277579 NC |
44 | 2016-08-11 Nick Clifton <nickc@redhat.com> |
45 | ||
46 | * interp.c (sim_create_inferior): Allow for being called with a | |
47 | NULL abfd parameter. If a bfd is provided, initialise the sim | |
48 | with that start address. | |
49 | * simulator.c (HALT_NYI): Just print out the numeric value of the | |
50 | instruction when not tracing. | |
b14bdb3b NC |
51 | (aarch64_step): Change from static to global. |
52 | * simulator.h: Add a prototype for aarch64_step(). | |
6a277579 | 53 | |
293acfae AM |
54 | 2016-07-27 Alan Modra <amodra@gmail.com> |
55 | ||
56 | * memory.c: Don't include libbfd.h. | |
57 | ||
0f118bc7 NC |
58 | 2016-07-21 Nick Clifton <nickc@redhat.com> |
59 | ||
0c66ea4c | 60 | * simulator.c (fsqrts): Use sqrtf rather than sqrt. |
0f118bc7 | 61 | |
c7be4414 JW |
62 | 2016-06-30 Jim Wilson <jim.wilson@linaro.org> |
63 | ||
64 | * cpustate.h: Include config.h. | |
65 | (union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code | |
66 | use anonymous structs to align members. | |
67 | * simulator.c (aarch64_step): Use sim_core_read_buffer and | |
68 | endian_le2h_4 to read instruction from pc. | |
69 | ||
fd7ed446 NC |
70 | 2016-05-06 Nick Clifton <nickc@redhat.com> |
71 | ||
72 | * simulator.c (do_FMLA_by_element): New function. | |
73 | (do_vec_op2): Call it. | |
74 | ||
2cdad34c NC |
75 | 2016-04-27 Nick Clifton <nickc@redhat.com> |
76 | ||
77 | * simulator.c: Add TRACE_DECODE statements to all emulation | |
78 | functions. | |
79 | ||
7517e550 NC |
80 | 2016-03-30 Nick Clifton <nickc@redhat.com> |
81 | ||
82 | * cpustate.c (aarch64_set_reg_s32): New function. | |
83 | (aarch64_set_reg_u32): New function. | |
84 | (aarch64_get_FP_half): Place half precision value into the correct | |
85 | slot of the union. | |
86 | (aarch64_set_FP_half): Likewise. | |
87 | * cpustate.h: Add prototypes for aarch64_set_reg_s32 and | |
88 | aarch64_set_reg_u32. | |
89 | * memory.c (FETCH_FUNC): Cast the read value to the access type | |
90 | before converting it to the return type. Rename to FETCH_FUNC64. | |
91 | (FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit | |
92 | accesses. Use for 32-bit memory access functions. | |
93 | * simulator.c (ldrsb_wb): Use sign extension not zero extension. | |
94 | (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise. | |
95 | (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise. | |
96 | (ldrsh_scale_ext, ldrsw_abs): Likewise. | |
97 | (ldrh32_abs): Store 32 bit value not 64-bits. | |
98 | (ldrh32_wb, ldrh32_scale_ext): Likewise. | |
99 | (do_vec_MOV_immediate): Fix computation of val. | |
100 | (do_vec_MVNI): Likewise. | |
101 | (DO_VEC_WIDENING_MUL): New macro. | |
102 | (do_vec_mull): Use new macro. | |
103 | (do_vec_mul): Use new macro. | |
104 | (do_vec_MLA): Read values before writing. | |
105 | (do_vec_xtl): Likewise. | |
106 | (do_vec_SSHL): Select correct shift value. | |
107 | (do_vec_USHL): Likewise. | |
108 | (do_scalar_UCVTF): New function. | |
109 | (do_scalar_vec): Call new function. | |
110 | (store_pair_u64): Treat reads of SP as reads of XZR. | |
111 | ||
ef0d8ffc NC |
112 | 2016-03-29 Nick Clifton <nickc@redhat.com> |
113 | ||
114 | * cpustate.c: Remove space after asterisk in function parameters. | |
115 | * decode.h (greg): Delete unused function. | |
116 | (vreg, shift, extension, scaling, writeback, condcode): Likewise. | |
117 | * simulator.c: Use INSTR macro in more places. | |
118 | (HALT_NYI): Use sim_io_eprintf in place of fprintf. | |
119 | Remove extraneous whitespace. | |
120 | ||
5ab6d79e NC |
121 | 2016-03-23 Nick Clifton <nickc@redhat.com> |
122 | ||
123 | * cpustate.c (aarch64_get_FP_half): New function. Read a vector | |
124 | register as a half precision floating point number. | |
125 | (aarch64_set_FP_half): New function. Similar, but for setting | |
126 | a half precision register. | |
127 | (aarch64_get_thread_id): New function. Returns the value of the | |
128 | CPU's TPIDR register. | |
129 | (aarch64_get_FPCR): New function. Returns the value of the CPU's | |
130 | floating point control register. | |
131 | (aarch64_set_FPCR): New function. Set the value of the CPU's FPCR | |
132 | register. | |
133 | * cpustate.h: Add prototypes for new functions. | |
134 | * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields. | |
135 | * memory.c: Use unaligned core access functions for all memory | |
136 | reads and writes. | |
137 | * simulator.c (HALT_NYI): Generate an error message if tracing | |
138 | will not tell the user why the simulator is halting. | |
139 | (HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro. | |
140 | (INSTR): New time-saver macro. | |
141 | (fldrb_abs): New function. Loads an 8-bit value using a scaled | |
142 | offset. | |
143 | (fldrh_abs): New function. Likewise for 16-bit values. | |
144 | (do_vec_SSHL): Allow for negative shift values. | |
145 | (do_vec_USHL): Likewise. | |
146 | (do_vec_SHL): Correct computation of shift amount. | |
147 | (do_vec_SSHR_USHR): Correct decision of signed vs unsigned | |
148 | shifts and computation of shift value. | |
149 | (clz): New function. Counts leading zero bits. | |
150 | (do_vec_CLZ): New function. Implements CLZ (vector). | |
151 | (do_vec_MOV_element): Call do_vec_CLZ. | |
152 | (dexSimpleFPCondCompare): Implement. | |
153 | (do_FCVT_half_to_single): New function. Implements one of the | |
154 | FCVT operations. | |
155 | (do_FCVT_half_to_double): New function. Likewise. | |
156 | (do_FCVT_single_to_half): New function. Likewise. | |
157 | (do_FCVT_double_to_half): New function. Likewise. | |
158 | (dexSimpleFPDataProc1Source): Call new FCVT functions. | |
159 | (do_scalar_SHL): Handle negative shifts. | |
160 | (do_scalar_shift): Handle SSHR. | |
161 | (do_scalar_USHL): New function. | |
162 | (do_double_add): Simplify to just performing a double precision | |
163 | add operation. Move remaining code into... | |
164 | (do_scalar_vec): ... New function. | |
165 | (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs | |
166 | functions. | |
167 | (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR | |
168 | registers. | |
169 | (system_set): New function. | |
170 | (do_MSR_immediate): New function. Stub for now. | |
171 | (do_MSR_reg): New function. Likewise. Partially implements MSR | |
172 | instruction. | |
173 | (do_SYS): New function. Stub for now, | |
174 | (dexSystem): Call new functions. | |
175 | ||
e101a78b NC |
176 | 2016-03-18 Nick Clifton <nickc@redhat.com> |
177 | ||
178 | * cpustate.c: Remove spurious spaces from TRACE strings. | |
179 | Print hex equivalents of floats and doubles. | |
180 | Check element number against array size when accessing vector | |
181 | registers. | |
4c0ca98e NC |
182 | (GET_VEC_ELEMENT): Fix off by one error checking for an invalid |
183 | element index. | |
184 | (SET_VEC_ELEMENT): Likewise. | |
87bba7a5 | 185 | (GET_VEC_ELEMENT): And fix thinko using macro arguments. |
4c0ca98e | 186 | |
e101a78b NC |
187 | * memory.c: Trace memory reads when --trace-memory is enabled. |
188 | Remove float and double load and store functions. | |
189 | * memory.h (aarch64_get_mem_float): Delete prototype. | |
190 | (aarch64_get_mem_double): Likewise. | |
191 | (aarch64_set_mem_float): Likewise. | |
192 | (aarch64_set_mem_double): Likewise. | |
193 | * simulator (IS_SET): Always return either 0 or 1. | |
194 | (IS_CLEAR): Likewise. | |
195 | (fldrs_pcrel): Load and store floats using 32-bit memory accesses | |
196 | and doubles using 64-bit memory accesses. | |
197 | (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise. | |
198 | (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise. | |
199 | (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise. | |
200 | (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise. | |
201 | (store_pair_double, load_pair_float, load_pair_double): Likewise. | |
202 | (do_vec_MUL_by_element): New function. | |
203 | (do_vec_op2): Call do_vec_MUL_by_element. | |
204 | (do_scalar_NEG): New function. | |
205 | (do_double_add): Call do_scalar_NEG. | |
206 | ||
57aa1742 NC |
207 | 2016-03-03 Nick Clifton <nickc@redhat.com> |
208 | ||
209 | * simulator.c (set_flags_for_sub32): Correct type of signbit. | |
210 | (CondCompare): Swap interpretation of bit 30. | |
211 | (DO_ADDP): Delete macro. | |
212 | (do_vec_ADDP): Copy source registers before starting to update | |
213 | destination register. | |
214 | (do_vec_FADDP): Likewise. | |
215 | (do_vec_load_store): Fix computation of sizeof_operation. | |
216 | (rbit64): Fix type of constant. | |
217 | (aarch64_step): When displaying insn value, display all 32 bits. | |
218 | ||
ce39bd38 MF |
219 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
220 | ||
221 | * config.in, configure: Regenerate. | |
222 | ||
e19418e0 MF |
223 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
224 | ||
225 | * configure: Regenerate. | |
226 | ||
16f7876d MF |
227 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
228 | ||
229 | * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call. | |
230 | * configure: Regenerate. | |
231 | ||
99d8e879 MF |
232 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
233 | ||
234 | * configure: Regenerate. | |
35656e95 MF |
235 | |
236 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> | |
237 | ||
238 | * configure: Regenerate. | |
99d8e879 | 239 | |
347fe5bb MF |
240 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
241 | ||
242 | * configure.ac (SIM_AC_OPTION_INLINE): Delete call. | |
243 | * configure: Regenerate. | |
244 | ||
22be3fbe MF |
245 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
246 | ||
247 | * configure: Regenerate. | |
248 | ||
0dc73ef7 MF |
249 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
250 | ||
251 | * configure: Regenerate. | |
252 | ||
936df756 MF |
253 | 2016-01-09 Mike Frysinger <vapier@gentoo.org> |
254 | ||
255 | * config.in, configure: Regenerate. | |
256 | ||
2e3d4f4d MF |
257 | 2016-01-06 Mike Frysinger <vapier@gentoo.org> |
258 | ||
259 | * interp.c (sim_create_inferior): Mark argv and env const. | |
260 | (sim_open): Mark argv const. | |
261 | ||
1a846c62 MF |
262 | 2016-01-05 Mike Frysinger <vapier@gentoo.org> |
263 | ||
264 | * interp.c: Delete dis-asm.h include. | |
265 | (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete. | |
266 | (sim_create_inferior): Delete disassemble init logic. | |
267 | (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete. | |
268 | (sim_open): Delete sim_add_option_table call. | |
269 | * memory.c (mem_error): Delete disas check. | |
270 | * simulator.c: Delete dis-asm.h include. | |
271 | (disas): Delete. | |
272 | (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM. | |
273 | (HALT_NYI): Likewise. | |
274 | (handle_halt): Delete disas call. | |
275 | (aarch64_step): Replace disas logic with TRACE_DISASM. | |
276 | * simulator.h: Delete dis-asm.h include. | |
277 | (aarch64_print_insn): Delete. | |
278 | ||
bc273e17 MF |
279 | 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
280 | ||
281 | * simulator.c (MAX, MIN): Delete. | |
282 | (do_vec_maxv): Change MAX to max and MIN to min. | |
283 | (do_vec_fminmaxV): Likewise. | |
284 | ||
ac8eefeb TG |
285 | 2016-01-04 Tristan Gingold <gingold@adacore.com> |
286 | ||
287 | * simulator.c: Remove syscall.h include. | |
288 | ||
9bbf6f91 MF |
289 | 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
290 | ||
291 | * configure: Regenerate. | |
292 | ||
0cb8d851 MF |
293 | 2016-01-03 Mike Frysinger <vapier@gentoo.org> |
294 | ||
295 | * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete. | |
296 | * configure: Regenerate. | |
297 | ||
1ac72f06 MF |
298 | 2016-01-02 Mike Frysinger <vapier@gentoo.org> |
299 | ||
300 | * configure: Regenerate. | |
301 | ||
5d015275 MF |
302 | 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
303 | ||
304 | * interp.c (sim_dis_read): Change private_data to application_data. | |
305 | (sim_create_inferior): Likewise. | |
306 | ||
5e744ef8 MF |
307 | 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
308 | ||
309 | * Makefile.in (SIM_OBJS): Delete sim-hload.o. | |
310 | ||
1b393626 MF |
311 | 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
312 | ||
313 | * config.in, configure: Regenerate. | |
314 | ||
0e967299 MF |
315 | 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
316 | ||
317 | * interp.c (sim_create_inferior): Update comment and argv check. | |
318 | ||
f66affe9 MF |
319 | 2015-12-14 Nick Clifton <nickc@redhat.com> |
320 | ||
321 | * simulator.c (system_get): New function. Provides read | |
322 | access to the dczid system register. | |
323 | (do_mrs): New function - implements the MRS instruction. | |
324 | (dexSystem): Call do_mrs for the MRS instruction. Halt on | |
325 | unimplemented system instructions. | |
326 | ||
327 | 2015-11-24 Nick Clifton <nickc@redhat.com> | |
328 | ||
329 | * configure.ac: New configure template. | |
330 | * aclocal.m4: Generate. | |
331 | * config.in: Generate. | |
332 | * configure: Generate. | |
333 | * cpustate.c: New file - functions for accessing AArch64 registers. | |
334 | * cpustate.h: New header. | |
335 | * decode.h: New header. | |
336 | * interp.c: New file - interface between GDB and simulator. | |
337 | * Makefile.in: New makefile template. | |
338 | * memory.c: New file - functions for simulating aarch64 memory | |
339 | accesses. | |
340 | * memory.h: New header. | |
341 | * sim-main.h: New header. | |
342 | * simulator.c: New file - aarch64 simulator functions. | |
343 | * simulator.h: New header. |