[deliverable/binutils-gdb.git] / sim / aarch64 / ChangeLog

2017-01-23  Jim Wilson  <jim.wilson@linaro.org>

	* simulator.c (do_vec_compare): Add case 0x23 for CMTST.

2017-01-17  Jim Wilson  <jim.wilson@linaro.org>

	* simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
	aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
	case 3, call HALT_UNALLOC unconditionally.
	(do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
	i + 2.  Delete if on bias, change index to i + bias * X.

2017-01-09  Jim Wilson  <jim.wilson@linaro.org>

	* simulator.c (do_vec_UZP): Rewrite.

2017-01-04  Jim Wilson  <jim.wilson@linaro.org>

	* cpustate.c: Include math.h.
	(aarch64_set_FP_float): Use signbit to check for signed zero.
	(aarch64_set_FP_double): Likewise.
	* simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
	(do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
	args same size as third arg.
	(fmaxnm): Use isnan instead of fpclassify.
	(fminnm, dmaxnm, dminnm): Likewise.
	(do_vec_MLS): Reverse order of subtraction operands.
	(dexSimpleFPCondSelect): Call aarch64_get_FP_double or
	aarch64_get_FP_float to get source register contents.
	(UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
	DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
	DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
	(do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
	raise_exception calls.

2016-12-21  Jim Wilson  <jim.wilson@linaro.org>

	* simulator.c (set_flags_for_float_compare): Add code to handle Inf.
	Add comment to document NaN issue.
	(set_flags_for_double_compare): Likewise.

2016-12-13  Jim Wilson  <jim.wilson@linaro.org>

	* simulator.c (NEG, POS): Move before set_flags_for_add64.
	(set_flags_for_add64): Replace with a modified copy of
	set_flags_for_sub64.

2016-12-03  Jim Wilson  <jim.wilson@linaro.org>

	* simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
	(dexTestBranchImmediate): Shift high bit of pos by 5 not 4.

2016-12-01  Jim Wilson  <jim.wilson@linaro.org>

	* simulator.c (fsturs): Switch use of rn and st variables.
	(fsturd, fsturq): Likewise

2016-08-15  Mike Frysinger  <vapier@gentoo.org>

	* interp.c: Include bfd.h.
	(symcount, symtab, aarch64_get_sym_value): Delete.
	(remove_useless_symbols): Change count type to long.
	(aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
	and symtab local variables.
	(sim_create_inferior): Delete storage.  Replace symbol code
	with a call to trace_load_symbols.
	* memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
	includes.
	(aarch64_get_heap_start): Change aarch64_get_sym_value to
	trace_sym_value.
	* memory.h: Delete bfd.h include.
	(mem_add_blk): Delete unused prototype.
	* simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
	* simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
	(aarch64_get_sym_value): Delete.

2016-08-12  Nick Clifton  <nickc@redhat.com>

	* simulator.c (aarch64_step): Revert pervious delta.
	(aarch64_run): Call sim_events_tick after each
	instruction is simulated, and if necessary call
	sim_events_process.
	* simulator.h: Revert previous delta.

2016-08-11  Nick Clifton  <nickc@redhat.com>

	* interp.c (sim_create_inferior): Allow for being called with a
	NULL abfd parameter.  If a bfd is provided, initialise the sim
	with that start address.
	* simulator.c (HALT_NYI): Just print out the numeric value of the
	instruction when not tracing.
	(aarch64_step): Change from static to global.
	* simulator.h: Add a prototype for aarch64_step().

2016-07-27  Alan Modra  <amodra@gmail.com>

	* memory.c: Don't include libbfd.h.

2016-07-21  Nick Clifton  <nickc@redhat.com>

	* simulator.c (fsqrts): Use sqrtf rather than sqrt.

2016-06-30  Jim Wilson  <jim.wilson@linaro.org>

	* cpustate.h: Include config.h.
	(union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
	use anonymous structs to align members.
	* simulator.c (aarch64_step): Use sim_core_read_buffer and
	endian_le2h_4 to read instruction from pc.

2016-05-06  Nick Clifton  <nickc@redhat.com>

	* simulator.c (do_FMLA_by_element): New function.
	(do_vec_op2): Call it.

2016-04-27  Nick Clifton  <nickc@redhat.com>

	* simulator.c: Add TRACE_DECODE statements to all emulation
	functions.

2016-03-30  Nick Clifton  <nickc@redhat.com>

	* cpustate.c (aarch64_set_reg_s32): New function.
	(aarch64_set_reg_u32): New function.
	(aarch64_get_FP_half): Place half precision value into the correct
	slot of the union.
	(aarch64_set_FP_half): Likewise.
	* cpustate.h: Add prototypes for aarch64_set_reg_s32 and
	aarch64_set_reg_u32.
	* memory.c (FETCH_FUNC): Cast the read value to the access type
	before converting it to the return type.  Rename to FETCH_FUNC64.
	(FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
	accesses.  Use for 32-bit memory access functions.
	* simulator.c (ldrsb_wb): Use sign extension not zero extension.
	(ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
	(ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
	(ldrsh_scale_ext, ldrsw_abs): Likewise.
	(ldrh32_abs): Store 32 bit value not 64-bits.
	(ldrh32_wb, ldrh32_scale_ext): Likewise.
	(do_vec_MOV_immediate): Fix computation of val.
	(do_vec_MVNI): Likewise.
	(DO_VEC_WIDENING_MUL): New macro.
	(do_vec_mull): Use new macro.
	(do_vec_mul): Use new macro.
	(do_vec_MLA): Read values before writing.
	(do_vec_xtl): Likewise.
	(do_vec_SSHL): Select correct shift value.
	(do_vec_USHL): Likewise.
	(do_scalar_UCVTF): New function.
	(do_scalar_vec): Call new function.
	(store_pair_u64): Treat reads of SP as reads of XZR.

2016-03-29  Nick Clifton  <nickc@redhat.com>

	* cpustate.c: Remove space after asterisk in function parameters.
	* decode.h (greg): Delete unused function.
	(vreg, shift, extension, scaling, writeback, condcode): Likewise.
	* simulator.c: Use INSTR macro in more places.
	(HALT_NYI): Use sim_io_eprintf in place of fprintf.
	Remove extraneous whitespace.

2016-03-23  Nick Clifton  <nickc@redhat.com>

	* cpustate.c (aarch64_get_FP_half): New function.  Read a vector
	register as a half precision floating point number.
	(aarch64_set_FP_half): New function.  Similar, but for setting
	a half precision register.
	(aarch64_get_thread_id): New function.  Returns the value of the
	CPU's TPIDR register.
	(aarch64_get_FPCR): New function.  Returns the value of the CPU's
	floating point control register.
	(aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
	register.
	* cpustate.h: Add prototypes for new functions.
	* sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
	* memory.c: Use unaligned core access functions for all memory
	reads and writes.
	* simulator.c (HALT_NYI): Generate an error message if tracing
	will not tell the user why the simulator is halting.
	(HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
	(INSTR): New time-saver macro.
	(fldrb_abs): New function.  Loads an 8-bit value using a scaled
	offset.
	(fldrh_abs): New function.  Likewise for 16-bit values.
	(do_vec_SSHL): Allow for negative shift values.
	(do_vec_USHL): Likewise.
	(do_vec_SHL): Correct computation of shift amount.
	(do_vec_SSHR_USHR): Correct decision of signed vs unsigned
	shifts and computation of shift value.
	(clz): New function.  Counts leading zero bits.
	(do_vec_CLZ): New function.  Implements CLZ (vector).
	(do_vec_MOV_element): Call do_vec_CLZ.
	(dexSimpleFPCondCompare): Implement.
	(do_FCVT_half_to_single): New function.  Implements one of the
	FCVT operations.
	(do_FCVT_half_to_double): New function.  Likewise.
	(do_FCVT_single_to_half): New function.  Likewise.
	(do_FCVT_double_to_half): New function.  Likewise.
	(dexSimpleFPDataProc1Source): Call new FCVT functions.
	(do_scalar_SHL): Handle negative shifts.
	(do_scalar_shift): Handle SSHR.
	(do_scalar_USHL): New function.
	(do_double_add): Simplify to just performing a double precision
	add operation.  Move remaining code into...
	(do_scalar_vec): ... New function.
	(dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
	functions.
	(system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
	registers.
	(system_set): New function.
	(do_MSR_immediate): New function.  Stub for now.
	(do_MSR_reg): New function.  Likewise. Partially implements MSR
	instruction.
	(do_SYS): New function.  Stub for now,
	(dexSystem): Call new functions.

2016-03-18  Nick Clifton  <nickc@redhat.com>

	* cpustate.c: Remove spurious spaces from TRACE strings.
	Print hex equivalents of floats and doubles.
	Check element number against array size when accessing vector
	registers.
	(GET_VEC_ELEMENT): Fix off by one error checking for an invalid
	element index.
	(SET_VEC_ELEMENT): Likewise.
	(GET_VEC_ELEMENT): And fix thinko using macro arguments.

	* memory.c: Trace memory reads when --trace-memory is enabled.
	Remove float and double load and store functions.
	* memory.h (aarch64_get_mem_float): Delete prototype.
	(aarch64_get_mem_double): Likewise.
	(aarch64_set_mem_float): Likewise.
	(aarch64_set_mem_double): Likewise.
	* simulator (IS_SET): Always return either 0 or 1.
	(IS_CLEAR): Likewise.
	(fldrs_pcrel): Load and store floats using 32-bit memory accesses
	and doubles using 64-bit memory accesses.
	(fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
	(fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
	(fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
	(fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
	(store_pair_double, load_pair_float, load_pair_double): Likewise.
	(do_vec_MUL_by_element): New function.
	(do_vec_op2): Call do_vec_MUL_by_element.
	(do_scalar_NEG): New function.
	(do_double_add): Call do_scalar_NEG.

2016-03-03  Nick Clifton  <nickc@redhat.com>

	* simulator.c (set_flags_for_sub32): Correct type of signbit.
	(CondCompare): Swap interpretation of bit 30.
	(DO_ADDP): Delete macro.
	(do_vec_ADDP): Copy source registers before starting to update
	destination register.
	(do_vec_FADDP): Likewise.
	(do_vec_load_store): Fix computation of sizeof_operation.
	(rbit64): Fix type of constant.
	(aarch64_step): When displaying insn value, display all 32 bits.

2016-01-10  Mike Frysinger  <vapier@gentoo.org>

	* config.in, configure: Regenerate.

2016-01-10  Mike Frysinger  <vapier@gentoo.org>

	* configure: Regenerate.

2016-01-10  Mike Frysinger  <vapier@gentoo.org>

	* configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
	* configure: Regenerate.

2016-01-10  Mike Frysinger  <vapier@gentoo.org>

	* configure: Regenerate.

2016-01-10  Mike Frysinger  <vapier@gentoo.org>

	* configure: Regenerate.

2016-01-10  Mike Frysinger  <vapier@gentoo.org>

	* configure.ac (SIM_AC_OPTION_INLINE): Delete call.
	* configure: Regenerate.

2016-01-10  Mike Frysinger  <vapier@gentoo.org>

	* configure: Regenerate.

2016-01-10  Mike Frysinger  <vapier@gentoo.org>

	* configure: Regenerate.

2016-01-09  Mike Frysinger  <vapier@gentoo.org>

	* config.in, configure: Regenerate.

2016-01-06  Mike Frysinger  <vapier@gentoo.org>

	* interp.c (sim_create_inferior): Mark argv and env const.
	(sim_open): Mark argv const.

2016-01-05  Mike Frysinger  <vapier@gentoo.org>

	* interp.c: Delete dis-asm.h include.
	(info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
	(sim_create_inferior): Delete disassemble init logic.
	(OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
	(sim_open): Delete sim_add_option_table call.
	* memory.c (mem_error): Delete disas check.
	* simulator.c: Delete dis-asm.h include.
	(disas): Delete.
	(HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
	(HALT_NYI): Likewise.
	(handle_halt): Delete disas call.
	(aarch64_step): Replace disas logic with TRACE_DISASM.
	* simulator.h: Delete dis-asm.h include.
	(aarch64_print_insn): Delete.

2016-01-04  Mike Frysinger  <vapier@gentoo.org>

	* simulator.c (MAX, MIN): Delete.
	(do_vec_maxv): Change MAX to max and MIN to min.
	(do_vec_fminmaxV): Likewise.

2016-01-04  Tristan Gingold  <gingold@adacore.com>

	* simulator.c: Remove syscall.h include.

2016-01-04  Mike Frysinger  <vapier@gentoo.org>

	* configure: Regenerate.

2016-01-03  Mike Frysinger  <vapier@gentoo.org>

	* configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
	* configure: Regenerate.

2016-01-02  Mike Frysinger  <vapier@gentoo.org>

	* configure: Regenerate.

2015-12-27  Mike Frysinger  <vapier@gentoo.org>

	* interp.c (sim_dis_read): Change private_data to application_data.
	(sim_create_inferior): Likewise.

2015-12-27  Mike Frysinger  <vapier@gentoo.org>

	* Makefile.in (SIM_OBJS): Delete sim-hload.o.

2015-12-26  Mike Frysinger  <vapier@gentoo.org>

	* config.in, configure: Regenerate.

2015-12-26  Mike Frysinger  <vapier@gentoo.org>

	* interp.c (sim_create_inferior): Update comment and argv check.

2015-12-14  Nick Clifton  <nickc@redhat.com>

	* simulator.c (system_get): New function.  Provides read
	access to the dczid system register.
	(do_mrs): New function - implements the MRS instruction.
	(dexSystem): Call do_mrs for the MRS instruction.  Halt on
	unimplemented system instructions.

2015-11-24  Nick Clifton  <nickc@redhat.com>

	* configure.ac: New configure template.
	* aclocal.m4: Generate.
	* config.in: Generate.
	* configure: Generate.
	* cpustate.c: New file - functions for accessing AArch64 registers.
	* cpustate.h: New header.
	* decode.h: New header.
	* interp.c: New file - interface between GDB and simulator.
	* Makefile.in: New makefile template.
	* memory.c: New file - functions for simulating aarch64 memory
	accesses.
	* memory.h: New header.
	* sim-main.h: New header.
	* simulator.c: New file - aarch64 simulator functions.
	* simulator.h: New header.
Commit	Line	Data
fbf32f63 JW	1	2017-01-23 Jim Wilson <jim.wilson@linaro.org>
	2
	3	* simulator.c (do_vec_compare): Add case 0x23 for CMTST.
	4
05b3d79d JW	5	2017-01-17 Jim Wilson <jim.wilson@linaro.org>
	6
	7	* simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
	8	aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In
	9	case 3, call HALT_UNALLOC unconditionally.
	10	(do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to
	11	i + 2. Delete if on bias, change index to i + bias * X.
	12
a4fb5981 JW	13	2017-01-09 Jim Wilson <jim.wilson@linaro.org>
	14
	15	* simulator.c (do_vec_UZP): Rewrite.
	16
c0386d4d JW	17	2017-01-04 Jim Wilson <jim.wilson@linaro.org>
	18
	19	* cpustate.c: Include math.h.
	20	(aarch64_set_FP_float): Use signbit to check for signed zero.
	21	(aarch64_set_FP_double): Likewise.
	22	* simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
	23	(do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
	24	args same size as third arg.
	25	(fmaxnm): Use isnan instead of fpclassify.
	26	(fminnm, dmaxnm, dminnm): Likewise.
	27	(do_vec_MLS): Reverse order of subtraction operands.
	28	(dexSimpleFPCondSelect): Call aarch64_get_FP_double or
	29	aarch64_get_FP_float to get source register contents.
	30	(UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
	31	DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
	32	DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
	33	(do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
	34	raise_exception calls.
	35
87903eaf JW	36	2016-12-21 Jim Wilson <jim.wilson@linaro.org>
	37
	38	* simulator.c (set_flags_for_float_compare): Add code to handle Inf.
	39	Add comment to document NaN issue.
	40	(set_flags_for_double_compare): Likewise.
	41
963201cf JW	42	2016-12-13 Jim Wilson <jim.wilson@linaro.org>
	43
	44	* simulator.c (NEG, POS): Move before set_flags_for_add64.
	45	(set_flags_for_add64): Replace with a modified copy of
	46	set_flags_for_sub64.
	47
668650d5 JW	48	2016-12-03 Jim Wilson <jim.wilson@linaro.org>
	49
	50	* simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
	51	(dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
	52
88ddd4a1 JW	53	2016-12-01 Jim Wilson <jim.wilson@linaro.org>
88ddd4a1 JW	54
88256e71	55	* simulator.c (fsturs): Switch use of rn and st variables.
88ddd4a1 JW	56	(fsturd, fsturq): Likewise
88ddd4a1 JW	57
5357150c MF	58	2016-08-15 Mike Frysinger <vapier@gentoo.org>
	59
	60	* interp.c: Include bfd.h.
	61	(symcount, symtab, aarch64_get_sym_value): Delete.
	62	(remove_useless_symbols): Change count type to long.
	63	(aarch64_get_func): Add SIM_DESC to arg list. Add symcount
	64	and symtab local variables.
	65	(sim_create_inferior): Delete storage. Replace symbol code
	66	with a call to trace_load_symbols.
	67	* memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
	68	includes.
	69	(aarch64_get_heap_start): Change aarch64_get_sym_value to
	70	trace_sym_value.
	71	* memory.h: Delete bfd.h include.
	72	(mem_add_blk): Delete unused prototype.
	73	* simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
	74	* simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
	75	(aarch64_get_sym_value): Delete.
	76
b14bdb3b NC	77	2016-08-12 Nick Clifton <nickc@redhat.com>
	78
	79	* simulator.c (aarch64_step): Revert pervious delta.
	80	(aarch64_run): Call sim_events_tick after each
	81	instruction is simulated, and if necessary call
	82	sim_events_process.
	83	* simulator.h: Revert previous delta.
	84
6a277579 NC	85	2016-08-11 Nick Clifton <nickc@redhat.com>
	86
	87	* interp.c (sim_create_inferior): Allow for being called with a
	88	NULL abfd parameter. If a bfd is provided, initialise the sim
	89	with that start address.
	90	* simulator.c (HALT_NYI): Just print out the numeric value of the
	91	instruction when not tracing.
b14bdb3b NC	92	(aarch64_step): Change from static to global.
b14bdb3b NC	93	* simulator.h: Add a prototype for aarch64_step().
6a277579	94
293acfae AM	95	2016-07-27 Alan Modra <amodra@gmail.com>
	96
	97	* memory.c: Don't include libbfd.h.
	98
0f118bc7 NC	99	2016-07-21 Nick Clifton <nickc@redhat.com>
0f118bc7 NC	100
0c66ea4c	101	* simulator.c (fsqrts): Use sqrtf rather than sqrt.
0f118bc7	102
c7be4414 JW	103	2016-06-30 Jim Wilson <jim.wilson@linaro.org>
	104
	105	* cpustate.h: Include config.h.
	106	(union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code
	107	use anonymous structs to align members.
	108	* simulator.c (aarch64_step): Use sim_core_read_buffer and
	109	endian_le2h_4 to read instruction from pc.
	110
fd7ed446 NC	111	2016-05-06 Nick Clifton <nickc@redhat.com>
	112
	113	* simulator.c (do_FMLA_by_element): New function.
	114	(do_vec_op2): Call it.
	115
2cdad34c NC	116	2016-04-27 Nick Clifton <nickc@redhat.com>
	117
	118	* simulator.c: Add TRACE_DECODE statements to all emulation
	119	functions.
	120
7517e550 NC	121	2016-03-30 Nick Clifton <nickc@redhat.com>
	122
	123	* cpustate.c (aarch64_set_reg_s32): New function.
	124	(aarch64_set_reg_u32): New function.
	125	(aarch64_get_FP_half): Place half precision value into the correct
	126	slot of the union.
	127	(aarch64_set_FP_half): Likewise.
	128	* cpustate.h: Add prototypes for aarch64_set_reg_s32 and
	129	aarch64_set_reg_u32.
	130	* memory.c (FETCH_FUNC): Cast the read value to the access type
	131	before converting it to the return type. Rename to FETCH_FUNC64.
	132	(FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit
	133	accesses. Use for 32-bit memory access functions.
	134	* simulator.c (ldrsb_wb): Use sign extension not zero extension.
	135	(ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
	136	(ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
	137	(ldrsh_scale_ext, ldrsw_abs): Likewise.
	138	(ldrh32_abs): Store 32 bit value not 64-bits.
	139	(ldrh32_wb, ldrh32_scale_ext): Likewise.
	140	(do_vec_MOV_immediate): Fix computation of val.
	141	(do_vec_MVNI): Likewise.
	142	(DO_VEC_WIDENING_MUL): New macro.
	143	(do_vec_mull): Use new macro.
	144	(do_vec_mul): Use new macro.
	145	(do_vec_MLA): Read values before writing.
	146	(do_vec_xtl): Likewise.
	147	(do_vec_SSHL): Select correct shift value.
	148	(do_vec_USHL): Likewise.
	149	(do_scalar_UCVTF): New function.
	150	(do_scalar_vec): Call new function.
	151	(store_pair_u64): Treat reads of SP as reads of XZR.
	152
ef0d8ffc NC	153	2016-03-29 Nick Clifton <nickc@redhat.com>
	154
	155	* cpustate.c: Remove space after asterisk in function parameters.
	156	* decode.h (greg): Delete unused function.
	157	(vreg, shift, extension, scaling, writeback, condcode): Likewise.
	158	* simulator.c: Use INSTR macro in more places.
	159	(HALT_NYI): Use sim_io_eprintf in place of fprintf.
	160	Remove extraneous whitespace.
	161
5ab6d79e NC	162	2016-03-23 Nick Clifton <nickc@redhat.com>
	163
	164	* cpustate.c (aarch64_get_FP_half): New function. Read a vector
	165	register as a half precision floating point number.
	166	(aarch64_set_FP_half): New function. Similar, but for setting
	167	a half precision register.
	168	(aarch64_get_thread_id): New function. Returns the value of the
	169	CPU's TPIDR register.
	170	(aarch64_get_FPCR): New function. Returns the value of the CPU's
	171	floating point control register.
	172	(aarch64_set_FPCR): New function. Set the value of the CPU's FPCR
	173	register.
	174	* cpustate.h: Add prototypes for new functions.
	175	* sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
	176	* memory.c: Use unaligned core access functions for all memory
	177	reads and writes.
	178	* simulator.c (HALT_NYI): Generate an error message if tracing
	179	will not tell the user why the simulator is halting.
	180	(HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro.
	181	(INSTR): New time-saver macro.
	182	(fldrb_abs): New function. Loads an 8-bit value using a scaled
	183	offset.
	184	(fldrh_abs): New function. Likewise for 16-bit values.
	185	(do_vec_SSHL): Allow for negative shift values.
	186	(do_vec_USHL): Likewise.
	187	(do_vec_SHL): Correct computation of shift amount.
	188	(do_vec_SSHR_USHR): Correct decision of signed vs unsigned
	189	shifts and computation of shift value.
	190	(clz): New function. Counts leading zero bits.
	191	(do_vec_CLZ): New function. Implements CLZ (vector).
	192	(do_vec_MOV_element): Call do_vec_CLZ.
	193	(dexSimpleFPCondCompare): Implement.
	194	(do_FCVT_half_to_single): New function. Implements one of the
	195	FCVT operations.
	196	(do_FCVT_half_to_double): New function. Likewise.
	197	(do_FCVT_single_to_half): New function. Likewise.
	198	(do_FCVT_double_to_half): New function. Likewise.
	199	(dexSimpleFPDataProc1Source): Call new FCVT functions.
	200	(do_scalar_SHL): Handle negative shifts.
	201	(do_scalar_shift): Handle SSHR.
	202	(do_scalar_USHL): New function.
	203	(do_double_add): Simplify to just performing a double precision
	204	add operation. Move remaining code into...
	205	(do_scalar_vec): ... New function.
	206	(dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
	207	functions.
	208	(system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
	209	registers.
	210	(system_set): New function.
	211	(do_MSR_immediate): New function. Stub for now.
	212	(do_MSR_reg): New function. Likewise. Partially implements MSR
	213	instruction.
	214	(do_SYS): New function. Stub for now,
	215	(dexSystem): Call new functions.
	216
e101a78b NC	217	2016-03-18 Nick Clifton <nickc@redhat.com>
	218
	219	* cpustate.c: Remove spurious spaces from TRACE strings.
	220	Print hex equivalents of floats and doubles.
	221	Check element number against array size when accessing vector
	222	registers.
4c0ca98e NC	223	(GET_VEC_ELEMENT): Fix off by one error checking for an invalid
	224	element index.
	225	(SET_VEC_ELEMENT): Likewise.
87bba7a5	226	(GET_VEC_ELEMENT): And fix thinko using macro arguments.
4c0ca98e	227
e101a78b NC	228	* memory.c: Trace memory reads when --trace-memory is enabled.
	229	Remove float and double load and store functions.
	230	* memory.h (aarch64_get_mem_float): Delete prototype.
	231	(aarch64_get_mem_double): Likewise.
	232	(aarch64_set_mem_float): Likewise.
	233	(aarch64_set_mem_double): Likewise.
	234	* simulator (IS_SET): Always return either 0 or 1.
	235	(IS_CLEAR): Likewise.
	236	(fldrs_pcrel): Load and store floats using 32-bit memory accesses
	237	and doubles using 64-bit memory accesses.
	238	(fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
	239	(fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
	240	(fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
	241	(fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
	242	(store_pair_double, load_pair_float, load_pair_double): Likewise.
	243	(do_vec_MUL_by_element): New function.
	244	(do_vec_op2): Call do_vec_MUL_by_element.
	245	(do_scalar_NEG): New function.
	246	(do_double_add): Call do_scalar_NEG.
	247
57aa1742 NC	248	2016-03-03 Nick Clifton <nickc@redhat.com>
	249
	250	* simulator.c (set_flags_for_sub32): Correct type of signbit.
	251	(CondCompare): Swap interpretation of bit 30.
	252	(DO_ADDP): Delete macro.
	253	(do_vec_ADDP): Copy source registers before starting to update
	254	destination register.
	255	(do_vec_FADDP): Likewise.
	256	(do_vec_load_store): Fix computation of sizeof_operation.
	257	(rbit64): Fix type of constant.
	258	(aarch64_step): When displaying insn value, display all 32 bits.
	259
ce39bd38 MF	260	2016-01-10 Mike Frysinger <vapier@gentoo.org>
	261
	262	* config.in, configure: Regenerate.
	263
e19418e0 MF	264	2016-01-10 Mike Frysinger <vapier@gentoo.org>
	265
	266	* configure: Regenerate.
	267
16f7876d MF	268	2016-01-10 Mike Frysinger <vapier@gentoo.org>
	269
	270	* configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
	271	* configure: Regenerate.
	272
99d8e879 MF	273	2016-01-10 Mike Frysinger <vapier@gentoo.org>
	274
	275	* configure: Regenerate.
35656e95 MF	276
	277	2016-01-10 Mike Frysinger <vapier@gentoo.org>
	278
	279	* configure: Regenerate.
99d8e879	280
347fe5bb MF	281	2016-01-10 Mike Frysinger <vapier@gentoo.org>
	282
	283	* configure.ac (SIM_AC_OPTION_INLINE): Delete call.
	284	* configure: Regenerate.
	285
22be3fbe MF	286	2016-01-10 Mike Frysinger <vapier@gentoo.org>
	287
	288	* configure: Regenerate.
	289
0dc73ef7 MF	290	2016-01-10 Mike Frysinger <vapier@gentoo.org>
	291
	292	* configure: Regenerate.
	293
936df756 MF	294	2016-01-09 Mike Frysinger <vapier@gentoo.org>
	295
	296	* config.in, configure: Regenerate.
	297
2e3d4f4d MF	298	2016-01-06 Mike Frysinger <vapier@gentoo.org>
	299
	300	* interp.c (sim_create_inferior): Mark argv and env const.
	301	(sim_open): Mark argv const.
	302
1a846c62 MF	303	2016-01-05 Mike Frysinger <vapier@gentoo.org>
	304
	305	* interp.c: Delete dis-asm.h include.
	306	(info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
	307	(sim_create_inferior): Delete disassemble init logic.
	308	(OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
	309	(sim_open): Delete sim_add_option_table call.
	310	* memory.c (mem_error): Delete disas check.
	311	* simulator.c: Delete dis-asm.h include.
	312	(disas): Delete.
	313	(HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
	314	(HALT_NYI): Likewise.
	315	(handle_halt): Delete disas call.
	316	(aarch64_step): Replace disas logic with TRACE_DISASM.
	317	* simulator.h: Delete dis-asm.h include.
	318	(aarch64_print_insn): Delete.
	319
bc273e17 MF	320	2016-01-04 Mike Frysinger <vapier@gentoo.org>
	321
	322	* simulator.c (MAX, MIN): Delete.
	323	(do_vec_maxv): Change MAX to max and MIN to min.
	324	(do_vec_fminmaxV): Likewise.
	325
ac8eefeb TG	326	2016-01-04 Tristan Gingold <gingold@adacore.com>
	327
	328	* simulator.c: Remove syscall.h include.
	329
9bbf6f91 MF	330	2016-01-04 Mike Frysinger <vapier@gentoo.org>
	331
	332	* configure: Regenerate.
	333
0cb8d851 MF	334	2016-01-03 Mike Frysinger <vapier@gentoo.org>
	335
	336	* configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
	337	* configure: Regenerate.
	338
1ac72f06 MF	339	2016-01-02 Mike Frysinger <vapier@gentoo.org>
	340
	341	* configure: Regenerate.
	342
5d015275 MF	343	2015-12-27 Mike Frysinger <vapier@gentoo.org>
	344
	345	* interp.c (sim_dis_read): Change private_data to application_data.
	346	(sim_create_inferior): Likewise.
	347
5e744ef8 MF	348	2015-12-27 Mike Frysinger <vapier@gentoo.org>
	349
	350	* Makefile.in (SIM_OBJS): Delete sim-hload.o.
	351
1b393626 MF	352	2015-12-26 Mike Frysinger <vapier@gentoo.org>
	353
	354	* config.in, configure: Regenerate.
	355
0e967299 MF	356	2015-12-26 Mike Frysinger <vapier@gentoo.org>
	357
	358	* interp.c (sim_create_inferior): Update comment and argv check.
	359
f66affe9 MF	360	2015-12-14 Nick Clifton <nickc@redhat.com>
	361
	362	* simulator.c (system_get): New function. Provides read
	363	access to the dczid system register.
	364	(do_mrs): New function - implements the MRS instruction.
	365	(dexSystem): Call do_mrs for the MRS instruction. Halt on
	366	unimplemented system instructions.
	367
	368	2015-11-24 Nick Clifton <nickc@redhat.com>
	369
	370	* configure.ac: New configure template.
	371	* aclocal.m4: Generate.
	372	* config.in: Generate.
	373	* configure: Generate.
	374	* cpustate.c: New file - functions for accessing AArch64 registers.
	375	* cpustate.h: New header.
	376	* decode.h: New header.
	377	* interp.c: New file - interface between GDB and simulator.
	378	* Makefile.in: New makefile template.
	379	* memory.c: New file - functions for simulating aarch64 memory
	380	accesses.
	381	* memory.h: New header.
	382	* sim-main.h: New header.
	383	* simulator.c: New file - aarch64 simulator functions.
	384	* simulator.h: New header.