Commit | Line | Data |
---|---|---|
8ecbe595 JW |
1 | 2017-03-03 Jim Wilson <jim.wilson@linaro.org> |
2 | ||
3 | * simulator.c (mul64hi): Shift carry left by 32. | |
4 | (smulh): Change signum to negate. If negate, invert result, and add | |
5 | carry bit if low part of multiply result is zero. | |
6 | ||
ac189e7b JW |
7 | 2017-02-25 Jim Wilson <jim.wilson@linaro.org> |
8 | ||
152e1e1b JW |
9 | * simulator.c (do_vec_SMOV_into_scalar): New. |
10 | (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar. | |
11 | Rewritten. | |
12 | (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted. | |
13 | (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call. Add | |
14 | do_vec_SMOV_into_scalar call. Delete do_vec_MOV_into_scalar and | |
15 | do_vec_UMOV calls. Add do_vec_UMOV_into_scalar call. | |
16 | ||
ac189e7b JW |
17 | * simulator.c (popcount): New. |
18 | (do_vec_CNT): New. | |
19 | (do_vec_op1): Add do_vec_CNT call. | |
20 | ||
2e7e5e28 JW |
21 | 2017-02-19 Jim Wilson <jim.wilson@linaro.org> |
22 | ||
23 | * simulator.c (do_vec_ADDV): Mov val declaration inside each case, | |
24 | with type set to input type size. | |
25 | (do_vec_xtl): Change bias from 3 to 4 for byte case. | |
26 | ||
e8f42b5e JW |
27 | 2017-02-14 Jim Wilson <jim.wilson@linaro.org> |
28 | ||
742e3a77 JW |
29 | * simulator.c (do_vec_MLA): Rewrite switch body. |
30 | ||
bf25e9a0 JW |
31 | * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and |
32 | 2. Move test_false if inside loop. Fix logic for computing result | |
33 | stored to vd. | |
34 | ||
e8f42b5e JW |
35 | * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New. |
36 | (do_vec_LDn_single, do_vec_STn_single): New. | |
37 | (do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with | |
38 | loop over nregs using new var n. Add n times size to address in loop. | |
39 | Add n to vd in loop. | |
40 | (do_vec_load_store): Add comment for instruction bit 24. New var | |
41 | single to hold instruction bit 24. Add new code to use single. Move | |
42 | ldnr support inside single if statements. Fix ldnr register counts | |
43 | inside post if statement. Change HALT_NYI calls to HALT_UNALLOC. | |
44 | ||
fbf32f63 JW |
45 | 2017-01-23 Jim Wilson <jim.wilson@linaro.org> |
46 | ||
47 | * simulator.c (do_vec_compare): Add case 0x23 for CMTST. | |
48 | ||
05b3d79d JW |
49 | 2017-01-17 Jim Wilson <jim.wilson@linaro.org> |
50 | ||
51 | * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of | |
52 | aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In | |
53 | case 3, call HALT_UNALLOC unconditionally. | |
54 | (do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to | |
55 | i + 2. Delete if on bias, change index to i + bias * X. | |
56 | ||
a4fb5981 JW |
57 | 2017-01-09 Jim Wilson <jim.wilson@linaro.org> |
58 | ||
59 | * simulator.c (do_vec_UZP): Rewrite. | |
60 | ||
c0386d4d JW |
61 | 2017-01-04 Jim Wilson <jim.wilson@linaro.org> |
62 | ||
63 | * cpustate.c: Include math.h. | |
64 | (aarch64_set_FP_float): Use signbit to check for signed zero. | |
65 | (aarch64_set_FP_double): Likewise. | |
66 | * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break. | |
67 | (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth | |
68 | args same size as third arg. | |
69 | (fmaxnm): Use isnan instead of fpclassify. | |
70 | (fminnm, dmaxnm, dminnm): Likewise. | |
71 | (do_vec_MLS): Reverse order of subtraction operands. | |
72 | (dexSimpleFPCondSelect): Call aarch64_get_FP_double or | |
73 | aarch64_get_FP_float to get source register contents. | |
74 | (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN, | |
75 | DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN, | |
76 | DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New. | |
77 | (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in | |
78 | raise_exception calls. | |
79 | ||
87903eaf JW |
80 | 2016-12-21 Jim Wilson <jim.wilson@linaro.org> |
81 | ||
82 | * simulator.c (set_flags_for_float_compare): Add code to handle Inf. | |
83 | Add comment to document NaN issue. | |
84 | (set_flags_for_double_compare): Likewise. | |
85 | ||
963201cf JW |
86 | 2016-12-13 Jim Wilson <jim.wilson@linaro.org> |
87 | ||
88 | * simulator.c (NEG, POS): Move before set_flags_for_add64. | |
89 | (set_flags_for_add64): Replace with a modified copy of | |
90 | set_flags_for_sub64. | |
91 | ||
668650d5 JW |
92 | 2016-12-03 Jim Wilson <jim.wilson@linaro.org> |
93 | ||
94 | * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting. | |
95 | (dexTestBranchImmediate): Shift high bit of pos by 5 not 4. | |
96 | ||
88ddd4a1 JW |
97 | 2016-12-01 Jim Wilson <jim.wilson@linaro.org> |
98 | ||
88256e71 | 99 | * simulator.c (fsturs): Switch use of rn and st variables. |
88ddd4a1 JW |
100 | (fsturd, fsturq): Likewise |
101 | ||
5357150c MF |
102 | 2016-08-15 Mike Frysinger <vapier@gentoo.org> |
103 | ||
104 | * interp.c: Include bfd.h. | |
105 | (symcount, symtab, aarch64_get_sym_value): Delete. | |
106 | (remove_useless_symbols): Change count type to long. | |
107 | (aarch64_get_func): Add SIM_DESC to arg list. Add symcount | |
108 | and symtab local variables. | |
109 | (sim_create_inferior): Delete storage. Replace symbol code | |
110 | with a call to trace_load_symbols. | |
111 | * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h | |
112 | includes. | |
113 | (aarch64_get_heap_start): Change aarch64_get_sym_value to | |
114 | trace_sym_value. | |
115 | * memory.h: Delete bfd.h include. | |
116 | (mem_add_blk): Delete unused prototype. | |
117 | * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func. | |
118 | * simulator.c (aarch64_get_func): Add SIM_DESC to arg list. | |
119 | (aarch64_get_sym_value): Delete. | |
120 | ||
b14bdb3b NC |
121 | 2016-08-12 Nick Clifton <nickc@redhat.com> |
122 | ||
123 | * simulator.c (aarch64_step): Revert pervious delta. | |
124 | (aarch64_run): Call sim_events_tick after each | |
125 | instruction is simulated, and if necessary call | |
126 | sim_events_process. | |
127 | * simulator.h: Revert previous delta. | |
128 | ||
6a277579 NC |
129 | 2016-08-11 Nick Clifton <nickc@redhat.com> |
130 | ||
131 | * interp.c (sim_create_inferior): Allow for being called with a | |
132 | NULL abfd parameter. If a bfd is provided, initialise the sim | |
133 | with that start address. | |
134 | * simulator.c (HALT_NYI): Just print out the numeric value of the | |
135 | instruction when not tracing. | |
b14bdb3b NC |
136 | (aarch64_step): Change from static to global. |
137 | * simulator.h: Add a prototype for aarch64_step(). | |
6a277579 | 138 | |
293acfae AM |
139 | 2016-07-27 Alan Modra <amodra@gmail.com> |
140 | ||
141 | * memory.c: Don't include libbfd.h. | |
142 | ||
0f118bc7 NC |
143 | 2016-07-21 Nick Clifton <nickc@redhat.com> |
144 | ||
0c66ea4c | 145 | * simulator.c (fsqrts): Use sqrtf rather than sqrt. |
0f118bc7 | 146 | |
c7be4414 JW |
147 | 2016-06-30 Jim Wilson <jim.wilson@linaro.org> |
148 | ||
149 | * cpustate.h: Include config.h. | |
150 | (union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code | |
151 | use anonymous structs to align members. | |
152 | * simulator.c (aarch64_step): Use sim_core_read_buffer and | |
153 | endian_le2h_4 to read instruction from pc. | |
154 | ||
fd7ed446 NC |
155 | 2016-05-06 Nick Clifton <nickc@redhat.com> |
156 | ||
157 | * simulator.c (do_FMLA_by_element): New function. | |
158 | (do_vec_op2): Call it. | |
159 | ||
2cdad34c NC |
160 | 2016-04-27 Nick Clifton <nickc@redhat.com> |
161 | ||
162 | * simulator.c: Add TRACE_DECODE statements to all emulation | |
163 | functions. | |
164 | ||
7517e550 NC |
165 | 2016-03-30 Nick Clifton <nickc@redhat.com> |
166 | ||
167 | * cpustate.c (aarch64_set_reg_s32): New function. | |
168 | (aarch64_set_reg_u32): New function. | |
169 | (aarch64_get_FP_half): Place half precision value into the correct | |
170 | slot of the union. | |
171 | (aarch64_set_FP_half): Likewise. | |
172 | * cpustate.h: Add prototypes for aarch64_set_reg_s32 and | |
173 | aarch64_set_reg_u32. | |
174 | * memory.c (FETCH_FUNC): Cast the read value to the access type | |
175 | before converting it to the return type. Rename to FETCH_FUNC64. | |
176 | (FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit | |
177 | accesses. Use for 32-bit memory access functions. | |
178 | * simulator.c (ldrsb_wb): Use sign extension not zero extension. | |
179 | (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise. | |
180 | (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise. | |
181 | (ldrsh_scale_ext, ldrsw_abs): Likewise. | |
182 | (ldrh32_abs): Store 32 bit value not 64-bits. | |
183 | (ldrh32_wb, ldrh32_scale_ext): Likewise. | |
184 | (do_vec_MOV_immediate): Fix computation of val. | |
185 | (do_vec_MVNI): Likewise. | |
186 | (DO_VEC_WIDENING_MUL): New macro. | |
187 | (do_vec_mull): Use new macro. | |
188 | (do_vec_mul): Use new macro. | |
189 | (do_vec_MLA): Read values before writing. | |
190 | (do_vec_xtl): Likewise. | |
191 | (do_vec_SSHL): Select correct shift value. | |
192 | (do_vec_USHL): Likewise. | |
193 | (do_scalar_UCVTF): New function. | |
194 | (do_scalar_vec): Call new function. | |
195 | (store_pair_u64): Treat reads of SP as reads of XZR. | |
196 | ||
ef0d8ffc NC |
197 | 2016-03-29 Nick Clifton <nickc@redhat.com> |
198 | ||
199 | * cpustate.c: Remove space after asterisk in function parameters. | |
200 | * decode.h (greg): Delete unused function. | |
201 | (vreg, shift, extension, scaling, writeback, condcode): Likewise. | |
202 | * simulator.c: Use INSTR macro in more places. | |
203 | (HALT_NYI): Use sim_io_eprintf in place of fprintf. | |
204 | Remove extraneous whitespace. | |
205 | ||
5ab6d79e NC |
206 | 2016-03-23 Nick Clifton <nickc@redhat.com> |
207 | ||
208 | * cpustate.c (aarch64_get_FP_half): New function. Read a vector | |
209 | register as a half precision floating point number. | |
210 | (aarch64_set_FP_half): New function. Similar, but for setting | |
211 | a half precision register. | |
212 | (aarch64_get_thread_id): New function. Returns the value of the | |
213 | CPU's TPIDR register. | |
214 | (aarch64_get_FPCR): New function. Returns the value of the CPU's | |
215 | floating point control register. | |
216 | (aarch64_set_FPCR): New function. Set the value of the CPU's FPCR | |
217 | register. | |
218 | * cpustate.h: Add prototypes for new functions. | |
219 | * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields. | |
220 | * memory.c: Use unaligned core access functions for all memory | |
221 | reads and writes. | |
222 | * simulator.c (HALT_NYI): Generate an error message if tracing | |
223 | will not tell the user why the simulator is halting. | |
224 | (HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro. | |
225 | (INSTR): New time-saver macro. | |
226 | (fldrb_abs): New function. Loads an 8-bit value using a scaled | |
227 | offset. | |
228 | (fldrh_abs): New function. Likewise for 16-bit values. | |
229 | (do_vec_SSHL): Allow for negative shift values. | |
230 | (do_vec_USHL): Likewise. | |
231 | (do_vec_SHL): Correct computation of shift amount. | |
232 | (do_vec_SSHR_USHR): Correct decision of signed vs unsigned | |
233 | shifts and computation of shift value. | |
234 | (clz): New function. Counts leading zero bits. | |
235 | (do_vec_CLZ): New function. Implements CLZ (vector). | |
236 | (do_vec_MOV_element): Call do_vec_CLZ. | |
237 | (dexSimpleFPCondCompare): Implement. | |
238 | (do_FCVT_half_to_single): New function. Implements one of the | |
239 | FCVT operations. | |
240 | (do_FCVT_half_to_double): New function. Likewise. | |
241 | (do_FCVT_single_to_half): New function. Likewise. | |
242 | (do_FCVT_double_to_half): New function. Likewise. | |
243 | (dexSimpleFPDataProc1Source): Call new FCVT functions. | |
244 | (do_scalar_SHL): Handle negative shifts. | |
245 | (do_scalar_shift): Handle SSHR. | |
246 | (do_scalar_USHL): New function. | |
247 | (do_double_add): Simplify to just performing a double precision | |
248 | add operation. Move remaining code into... | |
249 | (do_scalar_vec): ... New function. | |
250 | (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs | |
251 | functions. | |
252 | (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR | |
253 | registers. | |
254 | (system_set): New function. | |
255 | (do_MSR_immediate): New function. Stub for now. | |
256 | (do_MSR_reg): New function. Likewise. Partially implements MSR | |
257 | instruction. | |
258 | (do_SYS): New function. Stub for now, | |
259 | (dexSystem): Call new functions. | |
260 | ||
e101a78b NC |
261 | 2016-03-18 Nick Clifton <nickc@redhat.com> |
262 | ||
263 | * cpustate.c: Remove spurious spaces from TRACE strings. | |
264 | Print hex equivalents of floats and doubles. | |
265 | Check element number against array size when accessing vector | |
266 | registers. | |
4c0ca98e NC |
267 | (GET_VEC_ELEMENT): Fix off by one error checking for an invalid |
268 | element index. | |
269 | (SET_VEC_ELEMENT): Likewise. | |
87bba7a5 | 270 | (GET_VEC_ELEMENT): And fix thinko using macro arguments. |
4c0ca98e | 271 | |
e101a78b NC |
272 | * memory.c: Trace memory reads when --trace-memory is enabled. |
273 | Remove float and double load and store functions. | |
274 | * memory.h (aarch64_get_mem_float): Delete prototype. | |
275 | (aarch64_get_mem_double): Likewise. | |
276 | (aarch64_set_mem_float): Likewise. | |
277 | (aarch64_set_mem_double): Likewise. | |
278 | * simulator (IS_SET): Always return either 0 or 1. | |
279 | (IS_CLEAR): Likewise. | |
280 | (fldrs_pcrel): Load and store floats using 32-bit memory accesses | |
281 | and doubles using 64-bit memory accesses. | |
282 | (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise. | |
283 | (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise. | |
284 | (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise. | |
285 | (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise. | |
286 | (store_pair_double, load_pair_float, load_pair_double): Likewise. | |
287 | (do_vec_MUL_by_element): New function. | |
288 | (do_vec_op2): Call do_vec_MUL_by_element. | |
289 | (do_scalar_NEG): New function. | |
290 | (do_double_add): Call do_scalar_NEG. | |
291 | ||
57aa1742 NC |
292 | 2016-03-03 Nick Clifton <nickc@redhat.com> |
293 | ||
294 | * simulator.c (set_flags_for_sub32): Correct type of signbit. | |
295 | (CondCompare): Swap interpretation of bit 30. | |
296 | (DO_ADDP): Delete macro. | |
297 | (do_vec_ADDP): Copy source registers before starting to update | |
298 | destination register. | |
299 | (do_vec_FADDP): Likewise. | |
300 | (do_vec_load_store): Fix computation of sizeof_operation. | |
301 | (rbit64): Fix type of constant. | |
302 | (aarch64_step): When displaying insn value, display all 32 bits. | |
303 | ||
ce39bd38 MF |
304 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
305 | ||
306 | * config.in, configure: Regenerate. | |
307 | ||
e19418e0 MF |
308 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
309 | ||
310 | * configure: Regenerate. | |
311 | ||
16f7876d MF |
312 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
313 | ||
314 | * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call. | |
315 | * configure: Regenerate. | |
316 | ||
99d8e879 MF |
317 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
318 | ||
319 | * configure: Regenerate. | |
35656e95 MF |
320 | |
321 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> | |
322 | ||
323 | * configure: Regenerate. | |
99d8e879 | 324 | |
347fe5bb MF |
325 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
326 | ||
327 | * configure.ac (SIM_AC_OPTION_INLINE): Delete call. | |
328 | * configure: Regenerate. | |
329 | ||
22be3fbe MF |
330 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
331 | ||
332 | * configure: Regenerate. | |
333 | ||
0dc73ef7 MF |
334 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
335 | ||
336 | * configure: Regenerate. | |
337 | ||
936df756 MF |
338 | 2016-01-09 Mike Frysinger <vapier@gentoo.org> |
339 | ||
340 | * config.in, configure: Regenerate. | |
341 | ||
2e3d4f4d MF |
342 | 2016-01-06 Mike Frysinger <vapier@gentoo.org> |
343 | ||
344 | * interp.c (sim_create_inferior): Mark argv and env const. | |
345 | (sim_open): Mark argv const. | |
346 | ||
1a846c62 MF |
347 | 2016-01-05 Mike Frysinger <vapier@gentoo.org> |
348 | ||
349 | * interp.c: Delete dis-asm.h include. | |
350 | (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete. | |
351 | (sim_create_inferior): Delete disassemble init logic. | |
352 | (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete. | |
353 | (sim_open): Delete sim_add_option_table call. | |
354 | * memory.c (mem_error): Delete disas check. | |
355 | * simulator.c: Delete dis-asm.h include. | |
356 | (disas): Delete. | |
357 | (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM. | |
358 | (HALT_NYI): Likewise. | |
359 | (handle_halt): Delete disas call. | |
360 | (aarch64_step): Replace disas logic with TRACE_DISASM. | |
361 | * simulator.h: Delete dis-asm.h include. | |
362 | (aarch64_print_insn): Delete. | |
363 | ||
bc273e17 MF |
364 | 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
365 | ||
366 | * simulator.c (MAX, MIN): Delete. | |
367 | (do_vec_maxv): Change MAX to max and MIN to min. | |
368 | (do_vec_fminmaxV): Likewise. | |
369 | ||
ac8eefeb TG |
370 | 2016-01-04 Tristan Gingold <gingold@adacore.com> |
371 | ||
372 | * simulator.c: Remove syscall.h include. | |
373 | ||
9bbf6f91 MF |
374 | 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
375 | ||
376 | * configure: Regenerate. | |
377 | ||
0cb8d851 MF |
378 | 2016-01-03 Mike Frysinger <vapier@gentoo.org> |
379 | ||
380 | * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete. | |
381 | * configure: Regenerate. | |
382 | ||
1ac72f06 MF |
383 | 2016-01-02 Mike Frysinger <vapier@gentoo.org> |
384 | ||
385 | * configure: Regenerate. | |
386 | ||
5d015275 MF |
387 | 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
388 | ||
389 | * interp.c (sim_dis_read): Change private_data to application_data. | |
390 | (sim_create_inferior): Likewise. | |
391 | ||
5e744ef8 MF |
392 | 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
393 | ||
394 | * Makefile.in (SIM_OBJS): Delete sim-hload.o. | |
395 | ||
1b393626 MF |
396 | 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
397 | ||
398 | * config.in, configure: Regenerate. | |
399 | ||
0e967299 MF |
400 | 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
401 | ||
402 | * interp.c (sim_create_inferior): Update comment and argv check. | |
403 | ||
f66affe9 MF |
404 | 2015-12-14 Nick Clifton <nickc@redhat.com> |
405 | ||
406 | * simulator.c (system_get): New function. Provides read | |
407 | access to the dczid system register. | |
408 | (do_mrs): New function - implements the MRS instruction. | |
409 | (dexSystem): Call do_mrs for the MRS instruction. Halt on | |
410 | unimplemented system instructions. | |
411 | ||
412 | 2015-11-24 Nick Clifton <nickc@redhat.com> | |
413 | ||
414 | * configure.ac: New configure template. | |
415 | * aclocal.m4: Generate. | |
416 | * config.in: Generate. | |
417 | * configure: Generate. | |
418 | * cpustate.c: New file - functions for accessing AArch64 registers. | |
419 | * cpustate.h: New header. | |
420 | * decode.h: New header. | |
421 | * interp.c: New file - interface between GDB and simulator. | |
422 | * Makefile.in: New makefile template. | |
423 | * memory.c: New file - functions for simulating aarch64 memory | |
424 | accesses. | |
425 | * memory.h: New header. | |
426 | * sim-main.h: New header. | |
427 | * simulator.c: New file - aarch64 simulator functions. | |
428 | * simulator.h: New header. |