Commit | Line | Data |
---|---|---|
b14bdb3b NC |
1 | 2016-08-12 Nick Clifton <nickc@redhat.com> |
2 | ||
3 | * simulator.c (aarch64_step): Revert pervious delta. | |
4 | (aarch64_run): Call sim_events_tick after each | |
5 | instruction is simulated, and if necessary call | |
6 | sim_events_process. | |
7 | * simulator.h: Revert previous delta. | |
8 | ||
6a277579 NC |
9 | 2016-08-11 Nick Clifton <nickc@redhat.com> |
10 | ||
11 | * interp.c (sim_create_inferior): Allow for being called with a | |
12 | NULL abfd parameter. If a bfd is provided, initialise the sim | |
13 | with that start address. | |
14 | * simulator.c (HALT_NYI): Just print out the numeric value of the | |
15 | instruction when not tracing. | |
b14bdb3b NC |
16 | (aarch64_step): Change from static to global. |
17 | * simulator.h: Add a prototype for aarch64_step(). | |
6a277579 | 18 | |
293acfae AM |
19 | 2016-07-27 Alan Modra <amodra@gmail.com> |
20 | ||
21 | * memory.c: Don't include libbfd.h. | |
22 | ||
0f118bc7 NC |
23 | 2016-07-21 Nick Clifton <nickc@redhat.com> |
24 | ||
0c66ea4c | 25 | * simulator.c (fsqrts): Use sqrtf rather than sqrt. |
0f118bc7 | 26 | |
c7be4414 JW |
27 | 2016-06-30 Jim Wilson <jim.wilson@linaro.org> |
28 | ||
29 | * cpustate.h: Include config.h. | |
30 | (union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code | |
31 | use anonymous structs to align members. | |
32 | * simulator.c (aarch64_step): Use sim_core_read_buffer and | |
33 | endian_le2h_4 to read instruction from pc. | |
34 | ||
fd7ed446 NC |
35 | 2016-05-06 Nick Clifton <nickc@redhat.com> |
36 | ||
37 | * simulator.c (do_FMLA_by_element): New function. | |
38 | (do_vec_op2): Call it. | |
39 | ||
2cdad34c NC |
40 | 2016-04-27 Nick Clifton <nickc@redhat.com> |
41 | ||
42 | * simulator.c: Add TRACE_DECODE statements to all emulation | |
43 | functions. | |
44 | ||
7517e550 NC |
45 | 2016-03-30 Nick Clifton <nickc@redhat.com> |
46 | ||
47 | * cpustate.c (aarch64_set_reg_s32): New function. | |
48 | (aarch64_set_reg_u32): New function. | |
49 | (aarch64_get_FP_half): Place half precision value into the correct | |
50 | slot of the union. | |
51 | (aarch64_set_FP_half): Likewise. | |
52 | * cpustate.h: Add prototypes for aarch64_set_reg_s32 and | |
53 | aarch64_set_reg_u32. | |
54 | * memory.c (FETCH_FUNC): Cast the read value to the access type | |
55 | before converting it to the return type. Rename to FETCH_FUNC64. | |
56 | (FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit | |
57 | accesses. Use for 32-bit memory access functions. | |
58 | * simulator.c (ldrsb_wb): Use sign extension not zero extension. | |
59 | (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise. | |
60 | (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise. | |
61 | (ldrsh_scale_ext, ldrsw_abs): Likewise. | |
62 | (ldrh32_abs): Store 32 bit value not 64-bits. | |
63 | (ldrh32_wb, ldrh32_scale_ext): Likewise. | |
64 | (do_vec_MOV_immediate): Fix computation of val. | |
65 | (do_vec_MVNI): Likewise. | |
66 | (DO_VEC_WIDENING_MUL): New macro. | |
67 | (do_vec_mull): Use new macro. | |
68 | (do_vec_mul): Use new macro. | |
69 | (do_vec_MLA): Read values before writing. | |
70 | (do_vec_xtl): Likewise. | |
71 | (do_vec_SSHL): Select correct shift value. | |
72 | (do_vec_USHL): Likewise. | |
73 | (do_scalar_UCVTF): New function. | |
74 | (do_scalar_vec): Call new function. | |
75 | (store_pair_u64): Treat reads of SP as reads of XZR. | |
76 | ||
ef0d8ffc NC |
77 | 2016-03-29 Nick Clifton <nickc@redhat.com> |
78 | ||
79 | * cpustate.c: Remove space after asterisk in function parameters. | |
80 | * decode.h (greg): Delete unused function. | |
81 | (vreg, shift, extension, scaling, writeback, condcode): Likewise. | |
82 | * simulator.c: Use INSTR macro in more places. | |
83 | (HALT_NYI): Use sim_io_eprintf in place of fprintf. | |
84 | Remove extraneous whitespace. | |
85 | ||
5ab6d79e NC |
86 | 2016-03-23 Nick Clifton <nickc@redhat.com> |
87 | ||
88 | * cpustate.c (aarch64_get_FP_half): New function. Read a vector | |
89 | register as a half precision floating point number. | |
90 | (aarch64_set_FP_half): New function. Similar, but for setting | |
91 | a half precision register. | |
92 | (aarch64_get_thread_id): New function. Returns the value of the | |
93 | CPU's TPIDR register. | |
94 | (aarch64_get_FPCR): New function. Returns the value of the CPU's | |
95 | floating point control register. | |
96 | (aarch64_set_FPCR): New function. Set the value of the CPU's FPCR | |
97 | register. | |
98 | * cpustate.h: Add prototypes for new functions. | |
99 | * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields. | |
100 | * memory.c: Use unaligned core access functions for all memory | |
101 | reads and writes. | |
102 | * simulator.c (HALT_NYI): Generate an error message if tracing | |
103 | will not tell the user why the simulator is halting. | |
104 | (HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro. | |
105 | (INSTR): New time-saver macro. | |
106 | (fldrb_abs): New function. Loads an 8-bit value using a scaled | |
107 | offset. | |
108 | (fldrh_abs): New function. Likewise for 16-bit values. | |
109 | (do_vec_SSHL): Allow for negative shift values. | |
110 | (do_vec_USHL): Likewise. | |
111 | (do_vec_SHL): Correct computation of shift amount. | |
112 | (do_vec_SSHR_USHR): Correct decision of signed vs unsigned | |
113 | shifts and computation of shift value. | |
114 | (clz): New function. Counts leading zero bits. | |
115 | (do_vec_CLZ): New function. Implements CLZ (vector). | |
116 | (do_vec_MOV_element): Call do_vec_CLZ. | |
117 | (dexSimpleFPCondCompare): Implement. | |
118 | (do_FCVT_half_to_single): New function. Implements one of the | |
119 | FCVT operations. | |
120 | (do_FCVT_half_to_double): New function. Likewise. | |
121 | (do_FCVT_single_to_half): New function. Likewise. | |
122 | (do_FCVT_double_to_half): New function. Likewise. | |
123 | (dexSimpleFPDataProc1Source): Call new FCVT functions. | |
124 | (do_scalar_SHL): Handle negative shifts. | |
125 | (do_scalar_shift): Handle SSHR. | |
126 | (do_scalar_USHL): New function. | |
127 | (do_double_add): Simplify to just performing a double precision | |
128 | add operation. Move remaining code into... | |
129 | (do_scalar_vec): ... New function. | |
130 | (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs | |
131 | functions. | |
132 | (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR | |
133 | registers. | |
134 | (system_set): New function. | |
135 | (do_MSR_immediate): New function. Stub for now. | |
136 | (do_MSR_reg): New function. Likewise. Partially implements MSR | |
137 | instruction. | |
138 | (do_SYS): New function. Stub for now, | |
139 | (dexSystem): Call new functions. | |
140 | ||
e101a78b NC |
141 | 2016-03-18 Nick Clifton <nickc@redhat.com> |
142 | ||
143 | * cpustate.c: Remove spurious spaces from TRACE strings. | |
144 | Print hex equivalents of floats and doubles. | |
145 | Check element number against array size when accessing vector | |
146 | registers. | |
4c0ca98e NC |
147 | (GET_VEC_ELEMENT): Fix off by one error checking for an invalid |
148 | element index. | |
149 | (SET_VEC_ELEMENT): Likewise. | |
87bba7a5 | 150 | (GET_VEC_ELEMENT): And fix thinko using macro arguments. |
4c0ca98e | 151 | |
e101a78b NC |
152 | * memory.c: Trace memory reads when --trace-memory is enabled. |
153 | Remove float and double load and store functions. | |
154 | * memory.h (aarch64_get_mem_float): Delete prototype. | |
155 | (aarch64_get_mem_double): Likewise. | |
156 | (aarch64_set_mem_float): Likewise. | |
157 | (aarch64_set_mem_double): Likewise. | |
158 | * simulator (IS_SET): Always return either 0 or 1. | |
159 | (IS_CLEAR): Likewise. | |
160 | (fldrs_pcrel): Load and store floats using 32-bit memory accesses | |
161 | and doubles using 64-bit memory accesses. | |
162 | (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise. | |
163 | (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise. | |
164 | (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise. | |
165 | (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise. | |
166 | (store_pair_double, load_pair_float, load_pair_double): Likewise. | |
167 | (do_vec_MUL_by_element): New function. | |
168 | (do_vec_op2): Call do_vec_MUL_by_element. | |
169 | (do_scalar_NEG): New function. | |
170 | (do_double_add): Call do_scalar_NEG. | |
171 | ||
57aa1742 NC |
172 | 2016-03-03 Nick Clifton <nickc@redhat.com> |
173 | ||
174 | * simulator.c (set_flags_for_sub32): Correct type of signbit. | |
175 | (CondCompare): Swap interpretation of bit 30. | |
176 | (DO_ADDP): Delete macro. | |
177 | (do_vec_ADDP): Copy source registers before starting to update | |
178 | destination register. | |
179 | (do_vec_FADDP): Likewise. | |
180 | (do_vec_load_store): Fix computation of sizeof_operation. | |
181 | (rbit64): Fix type of constant. | |
182 | (aarch64_step): When displaying insn value, display all 32 bits. | |
183 | ||
ce39bd38 MF |
184 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
185 | ||
186 | * config.in, configure: Regenerate. | |
187 | ||
e19418e0 MF |
188 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
189 | ||
190 | * configure: Regenerate. | |
191 | ||
16f7876d MF |
192 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
193 | ||
194 | * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call. | |
195 | * configure: Regenerate. | |
196 | ||
99d8e879 MF |
197 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
198 | ||
199 | * configure: Regenerate. | |
35656e95 MF |
200 | |
201 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> | |
202 | ||
203 | * configure: Regenerate. | |
99d8e879 | 204 | |
347fe5bb MF |
205 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
206 | ||
207 | * configure.ac (SIM_AC_OPTION_INLINE): Delete call. | |
208 | * configure: Regenerate. | |
209 | ||
22be3fbe MF |
210 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
211 | ||
212 | * configure: Regenerate. | |
213 | ||
0dc73ef7 MF |
214 | 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
215 | ||
216 | * configure: Regenerate. | |
217 | ||
936df756 MF |
218 | 2016-01-09 Mike Frysinger <vapier@gentoo.org> |
219 | ||
220 | * config.in, configure: Regenerate. | |
221 | ||
2e3d4f4d MF |
222 | 2016-01-06 Mike Frysinger <vapier@gentoo.org> |
223 | ||
224 | * interp.c (sim_create_inferior): Mark argv and env const. | |
225 | (sim_open): Mark argv const. | |
226 | ||
1a846c62 MF |
227 | 2016-01-05 Mike Frysinger <vapier@gentoo.org> |
228 | ||
229 | * interp.c: Delete dis-asm.h include. | |
230 | (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete. | |
231 | (sim_create_inferior): Delete disassemble init logic. | |
232 | (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete. | |
233 | (sim_open): Delete sim_add_option_table call. | |
234 | * memory.c (mem_error): Delete disas check. | |
235 | * simulator.c: Delete dis-asm.h include. | |
236 | (disas): Delete. | |
237 | (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM. | |
238 | (HALT_NYI): Likewise. | |
239 | (handle_halt): Delete disas call. | |
240 | (aarch64_step): Replace disas logic with TRACE_DISASM. | |
241 | * simulator.h: Delete dis-asm.h include. | |
242 | (aarch64_print_insn): Delete. | |
243 | ||
bc273e17 MF |
244 | 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
245 | ||
246 | * simulator.c (MAX, MIN): Delete. | |
247 | (do_vec_maxv): Change MAX to max and MIN to min. | |
248 | (do_vec_fminmaxV): Likewise. | |
249 | ||
ac8eefeb TG |
250 | 2016-01-04 Tristan Gingold <gingold@adacore.com> |
251 | ||
252 | * simulator.c: Remove syscall.h include. | |
253 | ||
9bbf6f91 MF |
254 | 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
255 | ||
256 | * configure: Regenerate. | |
257 | ||
0cb8d851 MF |
258 | 2016-01-03 Mike Frysinger <vapier@gentoo.org> |
259 | ||
260 | * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete. | |
261 | * configure: Regenerate. | |
262 | ||
1ac72f06 MF |
263 | 2016-01-02 Mike Frysinger <vapier@gentoo.org> |
264 | ||
265 | * configure: Regenerate. | |
266 | ||
5d015275 MF |
267 | 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
268 | ||
269 | * interp.c (sim_dis_read): Change private_data to application_data. | |
270 | (sim_create_inferior): Likewise. | |
271 | ||
5e744ef8 MF |
272 | 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
273 | ||
274 | * Makefile.in (SIM_OBJS): Delete sim-hload.o. | |
275 | ||
1b393626 MF |
276 | 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
277 | ||
278 | * config.in, configure: Regenerate. | |
279 | ||
0e967299 MF |
280 | 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
281 | ||
282 | * interp.c (sim_create_inferior): Update comment and argv check. | |
283 | ||
f66affe9 MF |
284 | 2015-12-14 Nick Clifton <nickc@redhat.com> |
285 | ||
286 | * simulator.c (system_get): New function. Provides read | |
287 | access to the dczid system register. | |
288 | (do_mrs): New function - implements the MRS instruction. | |
289 | (dexSystem): Call do_mrs for the MRS instruction. Halt on | |
290 | unimplemented system instructions. | |
291 | ||
292 | 2015-11-24 Nick Clifton <nickc@redhat.com> | |
293 | ||
294 | * configure.ac: New configure template. | |
295 | * aclocal.m4: Generate. | |
296 | * config.in: Generate. | |
297 | * configure: Generate. | |
298 | * cpustate.c: New file - functions for accessing AArch64 registers. | |
299 | * cpustate.h: New header. | |
300 | * decode.h: New header. | |
301 | * interp.c: New file - interface between GDB and simulator. | |
302 | * Makefile.in: New makefile template. | |
303 | * memory.c: New file - functions for simulating aarch64 memory | |
304 | accesses. | |
305 | * memory.h: New header. | |
306 | * sim-main.h: New header. | |
307 | * simulator.c: New file - aarch64 simulator functions. | |
308 | * simulator.h: New header. |