[deliverable/binutils-gdb.git] / sim / arm / armemu.h

/*  armemu.h -- ARMulator emulation macros:  ARM6 Instruction Emulator.
    Copyright (C) 1994 Advanced RISC Machines Ltd.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.
 
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */

extern ARMword isize;

/***************************************************************************\
*                           Condition code values                           *
\***************************************************************************/

#define EQ 0
#define NE 1
#define CS 2
#define CC 3
#define MI 4
#define PL 5
#define VS 6
#define VC 7
#define HI 8
#define LS 9
#define GE 10
#define LT 11
#define GT 12
#define LE 13
#define AL 14
#define NV 15

/***************************************************************************\
*                               Shift Opcodes                               *
\***************************************************************************/

#define LSL 0
#define LSR 1
#define ASR 2
#define ROR 3

/***************************************************************************\
*               Macros to twiddle the status flags and mode                 *
\***************************************************************************/

#define NBIT ((unsigned)1L << 31)
#define ZBIT (1L << 30)
#define CBIT (1L << 29)
#define VBIT (1L << 28)
#define IBIT (1L << 7)
#define FBIT (1L << 6)
#define IFBITS (3L << 6)
#define R15IBIT (1L << 27)
#define R15FBIT (1L << 26)
#define R15IFBITS (3L << 26)

#define POS(i) ( (~(i)) >> 31 )
#define NEG(i) ( (i) >> 31 )

#ifdef MODET			/* Thumb support */
/* ??? This bit is actually in the low order bit of the PC in the hardware.
   It isn't clear if the simulator needs to model that or not.  */
#define TBIT (1L << 5)
#define TFLAG state->TFlag
#define SETT state->TFlag = 1
#define CLEART state->TFlag = 0
#define ASSIGNT(res) state->TFlag = res
#define INSN_SIZE (TFLAG ? 2 : 4)
#else
#define INSN_SIZE 4
#endif

#define NFLAG state->NFlag
#define SETN state->NFlag = 1
#define CLEARN state->NFlag = 0
#define ASSIGNN(res) state->NFlag = res

#define ZFLAG state->ZFlag
#define SETZ state->ZFlag = 1
#define CLEARZ state->ZFlag = 0
#define ASSIGNZ(res) state->ZFlag = res

#define CFLAG state->CFlag
#define SETC state->CFlag = 1
#define CLEARC state->CFlag = 0
#define ASSIGNC(res) state->CFlag = res

#define VFLAG state->VFlag
#define SETV state->VFlag = 1
#define CLEARV state->VFlag = 0
#define ASSIGNV(res) state->VFlag = res


#define IFLAG (state->IFFlags >> 1)
#define FFLAG (state->IFFlags & 1)
#define IFFLAGS state->IFFlags
#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;

#define PSR_FBITS (0xff000000L)
#define PSR_SBITS (0x00ff0000L)
#define PSR_XBITS (0x0000ff00L)
#define PSR_CBITS (0x000000ffL)

#define CCBITS (0xf0000000L)
#define INTBITS (0xc0L)

#if defined MODET && defined MODE32
#define PCBITS (0xffffffffL)
#else
#define PCBITS (0xfffffffcL)
#endif

#define MODEBITS (0x1fL)
#define R15INTBITS (3L << 26)

#if defined MODET && defined MODE32
#define R15PCBITS (0x03ffffffL)
#else
#define R15PCBITS (0x03fffffcL)
#endif

#define R15PCMODEBITS (0x03ffffffL)
#define R15MODEBITS (0x3L)

#ifdef MODE32
#define PCMASK PCBITS
#define PCWRAP(pc) (pc)
#else
#define PCMASK R15PCBITS
#define PCWRAP(pc) ((pc) & R15PCBITS)
#endif

#define PC (state->Reg[15] & PCMASK)
#define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS))
#define R15INT (state->Reg[15] & R15INTBITS)
#define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS))
#define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS))
#define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS))
#define R15PC (state->Reg[15] & R15PCBITS)
#define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
#define R15MODE (state->Reg[15] & R15MODEBITS)

#define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28))
#define EINT (IFFLAGS << 6)
#define ER15INT (IFFLAGS << 26)
#define EMODE (state->Mode)

#ifdef MODET
#define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
#else
#define CPSR (ECC | EINT | EMODE)
#endif

#ifdef MODE32
#define PATCHR15
#else
#define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC
#endif

#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE))
#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS)
#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS)
#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS)
#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS)
#define SETR15PSR(s) if (state->Mode == USER26MODE) { \
                        state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE ; \
                        ASSIGNN((state->Reg[15] & NBIT) != 0) ; \
                        ASSIGNZ((state->Reg[15] & ZBIT) != 0) ; \
                        ASSIGNC((state->Reg[15] & CBIT) != 0) ; \
                        ASSIGNV((state->Reg[15] & VBIT) != 0) ; \
                        } \
                     else { \
                        state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)) ; \
                        ARMul_R15Altered (state) ; \
                        }
#define SETABORT(i,m,d) do { \
  int SETABORT_mode = (m); \
  ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \
  ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \
			 | (i) | SETABORT_mode)); \
  state->Reg[14] = temp - (d); \
} while (0)

#ifndef MODE32
#define VECTORS 0x20
#define LEGALADDR 0x03ffffff
#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
#define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
#endif

#define INTERNALABORT(address) if (address < VECTORS) \
                                  state->Aborted = ARMul_DataAbortV ; \
                               else \
                                  state->Aborted = ARMul_AddrExceptnV ;

#ifdef MODE32
#define TAKEABORT ARMul_Abort(state,ARMul_DataAbortV)
#else
#define TAKEABORT if (state->Aborted == ARMul_AddrExceptnV) \
                     ARMul_Abort(state,ARMul_AddrExceptnV) ; \
                  else \
                     ARMul_Abort(state,ARMul_DataAbortV)
#endif
#define CPTAKEABORT if (!state->Aborted) \
                       ARMul_Abort(state,ARMul_UndefinedInstrV) ; \
                    else if (state->Aborted == ARMul_AddrExceptnV) \
                       ARMul_Abort(state,ARMul_AddrExceptnV) ; \
                    else \
                       ARMul_Abort(state,ARMul_DataAbortV)


/***************************************************************************\
*               Different ways to start the next instruction                *
\***************************************************************************/

#define SEQ 0
#define NONSEQ 1
#define PCINCEDSEQ 2
#define PCINCEDNONSEQ 3
#define PRIMEPIPE 4
#define RESUME 8

#define NORMALCYCLE state->NextInstr = 0
#define BUSUSEDN state->NextInstr |= 1	/* the next fetch will be an N cycle */
#define BUSUSEDINCPCS do { if (! state->is_StrongARM) { \
			state->Reg[15] += isize ; /* a standard PC inc and an S cycle */ \
			state->NextInstr = (state->NextInstr & 0xff) | 2; \
		      } } while (0)
#define BUSUSEDINCPCN do { if (state->is_StrongARM) BUSUSEDN; else { \
			state->Reg[15] += isize ; /* a standard PC inc and an N cycle */ \
			state->NextInstr |= 3; \
		      } } while (0)
#define INCPC state->Reg[15] += isize ; /* a standard PC inc */ \
              state->NextInstr |= 2
#define FLUSHPIPE state->NextInstr |= PRIMEPIPE

/***************************************************************************\
*                          Cycle based emulation                            *
\***************************************************************************/

#define OUTPUTCP(i,a,b)
#define NCYCLE
#define SCYCLE
#define ICYCLE
#define CCYCLE
#define NEXTCYCLE(c)

/***************************************************************************\
*                 States of the cycle based state machine                   *
\***************************************************************************/


/***************************************************************************\
*                 Macros to extract parts of instructions                   *
\***************************************************************************/

#define DESTReg (BITS(12,15))
#define LHSReg (BITS(16,19))
#define RHSReg (BITS(0,3))

#define DEST (state->Reg[DESTReg])

#ifdef MODE32
#ifdef MODET
#define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
#else
#define LHS (state->Reg[LHSReg])
#endif
#else
#define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]) )
#endif

#define MULDESTReg (BITS(16,19))
#define MULLHSReg (BITS(0,3))
#define MULRHSReg (BITS(8,11))
#define MULACCReg (BITS(12,15))

#define DPImmRHS (ARMul_ImmedTable[BITS(0,11)])
#define DPSImmRHS temp = BITS(0,11) ; \
                  rhs = ARMul_ImmedTable[temp] ; \
                  if (temp > 255) /* there was a shift */ \
                     ASSIGNC(rhs >> 31) ;

#ifdef MODE32
#define DPRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
                                  : GetDPRegRHS(state, instr))
#define DPSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
                                   : GetDPSRegRHS(state, instr))
#else
#define DPRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
                                  : GetDPRegRHS(state, instr))
#define DPSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
                                   : GetDPSRegRHS(state, instr))
#endif

#define LSBase state->Reg[LHSReg]
#define LSImmRHS (BITS(0,11))

#ifdef MODE32
#define LSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
                                  : GetLSRegRHS(state, instr))
#else
#define LSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
                                  : GetLSRegRHS(state, instr))
#endif

#define LSMNumRegs ((ARMword)ARMul_BitList[BITS(0,7)] + \
                    (ARMword)ARMul_BitList[BITS(8,15)] )
#define LSMBaseFirst ((LHSReg == 0 && BIT(0)) || \
                      (BIT(LHSReg) && BITS(0,LHSReg-1) == 0))

#define SWAPSRC (state->Reg[RHSReg])

#define LSCOff (BITS(0,7) << 2)
#define CPNum BITS(8,11)

/***************************************************************************\
*                    Macro to rotate n right by b bits                      *
\***************************************************************************/

#define ROTATER(n,b) (((n)>>(b))|((n)<<(32-(b))))

/***************************************************************************\
*                 Macros to store results of instructions                   *
\***************************************************************************/

#define WRITEDEST(d) if (DESTReg==15) \
                        WriteR15(state, d) ; \
                     else \
                          DEST = d

#define WRITESDEST(d) if (DESTReg == 15) \
                         WriteSR15(state, d) ; \
                      else { \
                         DEST = d ; \
                         ARMul_NegZero(state, d) ; \
                         }

#define WRITEDESTB(d) if (DESTReg == 15) \
                        WriteR15Branch(state, d) ; \
                     else \
                          DEST = d

#define BYTETOBUS(data) ((data & 0xff) | \
                        ((data & 0xff) << 8) | \
                        ((data & 0xff) << 16) | \
                        ((data & 0xff) << 24))
#define BUSTOBYTE(address,data) \
           if (state->bigendSig) \
              temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff ; \
           else \
              temp = (data >> ((address & 3) << 3)) & 0xff

#define LOADMULT(instr,address,wb) LoadMult(state,instr,address,wb)
#define LOADSMULT(instr,address,wb) LoadSMult(state,instr,address,wb)
#define STOREMULT(instr,address,wb) StoreMult(state,instr,address,wb)
#define STORESMULT(instr,address,wb) StoreSMult(state,instr,address,wb)

#define POSBRANCH ((instr & 0x7fffff) << 2)
#define NEGBRANCH (0xfc000000 | ((instr & 0xffffff) << 2))

/***************************************************************************\
*                          Values for Emulate                               *
\***************************************************************************/

#define STOP            0	/* stop */
#define CHANGEMODE      1	/* change mode */
#define ONCE            2	/* execute just one interation */
#define RUN             3	/* continuous execution */

/***************************************************************************\
*                      Stuff that is shared across modes                    *
\***************************************************************************/

extern ARMword ARMul_Emulate26 (ARMul_State * state);
extern ARMword ARMul_Emulate32 (ARMul_State * state);
extern unsigned ARMul_MultTable[];	/* Number of I cycles for a mult */
extern ARMword ARMul_ImmedTable[];	/* immediate DP LHS values */
extern char ARMul_BitList[];	/* number of bits in a byte table */
extern void ARMul_Abort26 (ARMul_State * state, ARMword);
extern void ARMul_Abort32 (ARMul_State * state, ARMword);
extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
extern void ARMul_MSRCpsr (ARMul_State * state, ARMword instr, ARMword rhs);
extern void ARMul_NegZero (ARMul_State * state, ARMword result);
extern void ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b,
			    ARMword result);
extern int AddOverflow (ARMword a, ARMword b, ARMword result);
extern int SubOverflow (ARMword a, ARMword b, ARMword result);
extern void ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b,
			       ARMword result);
extern void ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b,
			    ARMword result);
extern void ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b,
			       ARMword result);
extern void ARMul_CPSRAltered (ARMul_State * state);
extern void ARMul_R15Altered (ARMul_State * state);
extern ARMword ARMul_SwitchMode (ARMul_State * state, ARMword oldmode,
				 ARMword newmode);
extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
extern void ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address);
extern void ARMul_STC (ARMul_State * state, ARMword instr, ARMword address);
extern void ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source);
extern ARMword ARMul_MRC (ARMul_State * state, ARMword instr);
extern void ARMul_CDP (ARMul_State * state, ARMword instr);
extern unsigned IntPending (ARMul_State * state);
extern ARMword ARMul_Align (ARMul_State * state, ARMword address,
			    ARMword data);
#define EVENTLISTSIZE 1024L

/* Thumb support: */

typedef enum
{
  t_undefined,			/* undefined Thumb instruction */
  t_decoded,			/* instruction decoded to ARM equivalent */
  t_branch			/* Thumb branch (already processed) */
}
tdstate;

extern tdstate ARMul_ThumbDecode (ARMul_State * state, ARMword pc,
				  ARMword tinstr, ARMword * ainstr);

/***************************************************************************\
*                      Macros to scrutinize instructions                    *
\***************************************************************************/


#define UNDEF_Test
#define UNDEF_Shift
#define UNDEF_MSRPC
#define UNDEF_MRSPC
#define UNDEF_MULPCDest
#define UNDEF_MULDestEQOp1
#define UNDEF_LSRBPC
#define UNDEF_LSRBaseEQOffWb
#define UNDEF_LSRBaseEQDestWb
#define UNDEF_LSRPCBaseWb
#define UNDEF_LSRPCOffWb
#define UNDEF_LSMNoRegs
#define UNDEF_LSMPCBase
#define UNDEF_LSMUserBankWb
#define UNDEF_LSMBaseInListWb
#define UNDEF_SWPPC
#define UNDEF_CoProHS
#define UNDEF_MCRPC
#define UNDEF_LSCPCBaseWb
#define UNDEF_UndefNotBounced
#define UNDEF_ShortInt
#define UNDEF_IllegalMode
#define UNDEF_Prog32SigChange
#define UNDEF_Data32SigChange
Commit	Line	Data
c906108c SS	1	/* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator.
	2	Copyright (C) 1994 Advanced RISC Machines Ltd.
	3
	4	This program is free software; you can redistribute it and/or modify
	5	it under the terms of the GNU General Public License as published by
	6	the Free Software Foundation; either version 2 of the License, or
	7	(at your option) any later version.
	8
	9	This program is distributed in the hope that it will be useful,
	10	but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	GNU General Public License for more details.
	13
	14	You should have received a copy of the GNU General Public License
	15	along with this program; if not, write to the Free Software
	16	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	17
	18	extern ARMword isize;
	19
	20	/***************************************************************************\
	21	* Condition code values *
	22	\***************************************************************************/
	23
	24	#define EQ 0
	25	#define NE 1
	26	#define CS 2
	27	#define CC 3
	28	#define MI 4
	29	#define PL 5
	30	#define VS 6
	31	#define VC 7
	32	#define HI 8
	33	#define LS 9
	34	#define GE 10
	35	#define LT 11
	36	#define GT 12
	37	#define LE 13
	38	#define AL 14
	39	#define NV 15
	40
	41	/***************************************************************************\
	42	* Shift Opcodes *
	43	\***************************************************************************/
	44
	45	#define LSL 0
	46	#define LSR 1
	47	#define ASR 2
	48	#define ROR 3
	49
	50	/***************************************************************************\
	51	* Macros to twiddle the status flags and mode *
	52	\***************************************************************************/
	53
	54	#define NBIT ((unsigned)1L << 31)
	55	#define ZBIT (1L << 30)
	56	#define CBIT (1L << 29)
	57	#define VBIT (1L << 28)
	58	#define IBIT (1L << 7)
	59	#define FBIT (1L << 6)
	60	#define IFBITS (3L << 6)
	61	#define R15IBIT (1L << 27)
	62	#define R15FBIT (1L << 26)
	63	#define R15IFBITS (3L << 26)
	64
65	#define POS(i) ( (~(i)) >> 31 )
66	#define NEG(i) ( (i) >> 31 )
67
dfcd3bfb	68	#ifdef MODET /* Thumb support */
c906108c SS	69	/* ??? This bit is actually in the low order bit of the PC in the hardware.
	70	It isn't clear if the simulator needs to model that or not. */
	71	#define TBIT (1L << 5)
	72	#define TFLAG state->TFlag
	73	#define SETT state->TFlag = 1
	74	#define CLEART state->TFlag = 0
	75	#define ASSIGNT(res) state->TFlag = res
e063aa3b AO	76	#define INSN_SIZE (TFLAG ? 2 : 4)
	77	#else
	78	#define INSN_SIZE 4
c906108c SS	79	#endif
	80
	81	#define NFLAG state->NFlag
	82	#define SETN state->NFlag = 1
	83	#define CLEARN state->NFlag = 0
	84	#define ASSIGNN(res) state->NFlag = res
	85
	86	#define ZFLAG state->ZFlag
	87	#define SETZ state->ZFlag = 1
	88	#define CLEARZ state->ZFlag = 0
	89	#define ASSIGNZ(res) state->ZFlag = res
	90
	91	#define CFLAG state->CFlag
	92	#define SETC state->CFlag = 1
	93	#define CLEARC state->CFlag = 0
	94	#define ASSIGNC(res) state->CFlag = res
	95
	96	#define VFLAG state->VFlag
	97	#define SETV state->VFlag = 1
	98	#define CLEARV state->VFlag = 0
	99	#define ASSIGNV(res) state->VFlag = res
	100
f743149e	101
c906108c SS	102	#define IFLAG (state->IFFlags >> 1)
	103	#define FFLAG (state->IFFlags & 1)
	104	#define IFFLAGS state->IFFlags
	105	#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
	106	#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
	107
4ef2594f AO	108	#define PSR_FBITS (0xff000000L)
	109	#define PSR_SBITS (0x00ff0000L)
	110	#define PSR_XBITS (0x0000ff00L)
	111	#define PSR_CBITS (0x000000ffL)
	112
c906108c SS	113	#define CCBITS (0xf0000000L)
	114	#define INTBITS (0xc0L)
	115
	116	#if defined MODET && defined MODE32
	117	#define PCBITS (0xffffffffL)
	118	#else
	119	#define PCBITS (0xfffffffcL)
	120	#endif
	121
	122	#define MODEBITS (0x1fL)
	123	#define R15INTBITS (3L << 26)
	124
	125	#if defined MODET && defined MODE32
	126	#define R15PCBITS (0x03ffffffL)
	127	#else
	128	#define R15PCBITS (0x03fffffcL)
	129	#endif
	130
	131	#define R15PCMODEBITS (0x03ffffffL)
	132	#define R15MODEBITS (0x3L)
	133
	134	#ifdef MODE32
	135	#define PCMASK PCBITS
	136	#define PCWRAP(pc) (pc)
	137	#else
	138	#define PCMASK R15PCBITS
	139	#define PCWRAP(pc) ((pc) & R15PCBITS)
	140	#endif
	141
	142	#define PC (state->Reg[15] & PCMASK)
	143	#define R15CCINTMODE (state->Reg[15] & (CCBITS \| R15INTBITS \| R15MODEBITS))
	144	#define R15INT (state->Reg[15] & R15INTBITS)
	145	#define R15INTPC (state->Reg[15] & (R15INTBITS \| R15PCBITS))
	146	#define R15INTPCMODE (state->Reg[15] & (R15INTBITS \| R15PCBITS \| R15MODEBITS))
	147	#define R15INTMODE (state->Reg[15] & (R15INTBITS \| R15MODEBITS))
	148	#define R15PC (state->Reg[15] & R15PCBITS)
	149	#define R15PCMODE (state->Reg[15] & (R15PCBITS \| R15MODEBITS))
	150	#define R15MODE (state->Reg[15] & R15MODEBITS)
	151
	152	#define ECC ((NFLAG << 31) \| (ZFLAG << 30) \| (CFLAG << 29) \| (VFLAG << 28))
	153	#define EINT (IFFLAGS << 6)
	154	#define ER15INT (IFFLAGS << 26)
	155	#define EMODE (state->Mode)
	156
	157	#ifdef MODET
	158	#define CPSR (ECC \| EINT \| EMODE \| (TFLAG << 5))
	159	#else
	160	#define CPSR (ECC \| EINT \| EMODE)
	161	#endif
	162
	163	#ifdef MODE32
	164	#define PATCHR15
	165	#else
	166	#define PATCHR15 state->Reg[15] = ECC \| ER15INT \| EMODE \| R15PC
	167	#endif
	168
cf52c765	169	#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE))
4ef2594f AO	170	#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) \| ((s) & PSR_FBITS)
	171	#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) \| ((s) & PSR_SBITS)
	172	#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) \| ((s) & PSR_XBITS)
	173	#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) \| ((s) & PSR_CBITS)
c906108c SS	174	#define SETR15PSR(s) if (state->Mode == USER26MODE) { \
	175	state->Reg[15] = ((s) & CCBITS) \| R15PC \| ER15INT \| EMODE ; \
	176	ASSIGNN((state->Reg[15] & NBIT) != 0) ; \
	177	ASSIGNZ((state->Reg[15] & ZBIT) != 0) ; \
	178	ASSIGNC((state->Reg[15] & CBIT) != 0) ; \
	179	ASSIGNV((state->Reg[15] & VBIT) != 0) ; \
	180	} \
	181	else { \
6d358e86 NC	182	state->Reg[15] = R15PC \| ((s) & (CCBITS \| R15INTBITS \| R15MODEBITS)) ; \
6d358e86 NC	183	ARMul_R15Altered (state) ; \
c906108c	184	}
e063aa3b AO	185	#define SETABORT(i,m,d) do { \
	186	int SETABORT_mode = (m); \
	187	ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \
	188	ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE \| TBIT)) \
	189	\| (i) \| SETABORT_mode)); \
	190	state->Reg[14] = temp - (d); \
	191	} while (0)
c906108c SS	192
	193	#ifndef MODE32
	194	#define VECTORS 0x20
	195	#define LEGALADDR 0x03ffffff
	196	#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
	197	#define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
	198	#endif
	199
	200	#define INTERNALABORT(address) if (address < VECTORS) \
	201	state->Aborted = ARMul_DataAbortV ; \
	202	else \
	203	state->Aborted = ARMul_AddrExceptnV ;
	204
	205	#ifdef MODE32
	206	#define TAKEABORT ARMul_Abort(state,ARMul_DataAbortV)
	207	#else
	208	#define TAKEABORT if (state->Aborted == ARMul_AddrExceptnV) \
	209	ARMul_Abort(state,ARMul_AddrExceptnV) ; \
	210	else \
	211	ARMul_Abort(state,ARMul_DataAbortV)
	212	#endif
	213	#define CPTAKEABORT if (!state->Aborted) \
	214	ARMul_Abort(state,ARMul_UndefinedInstrV) ; \
	215	else if (state->Aborted == ARMul_AddrExceptnV) \
	216	ARMul_Abort(state,ARMul_AddrExceptnV) ; \
	217	else \
	218	ARMul_Abort(state,ARMul_DataAbortV)
	219
	220
	221	/***************************************************************************\
	222	* Different ways to start the next instruction *
	223	\***************************************************************************/
	224
	225	#define SEQ 0
	226	#define NONSEQ 1
	227	#define PCINCEDSEQ 2
	228	#define PCINCEDNONSEQ 3
	229	#define PRIMEPIPE 4
	230	#define RESUME 8
	231
	232	#define NORMALCYCLE state->NextInstr = 0
dfcd3bfb	233	#define BUSUSEDN state->NextInstr \|= 1 /* the next fetch will be an N cycle */
1e6b544a AO	234	#define BUSUSEDINCPCS do { if (! state->is_StrongARM) { \
	235	state->Reg[15] += isize ; /* a standard PC inc and an S cycle */ \
	236	state->NextInstr = (state->NextInstr & 0xff) \| 2; \
	237	} } while (0)
	238	#define BUSUSEDINCPCN do { if (state->is_StrongARM) BUSUSEDN; else { \
	239	state->Reg[15] += isize ; /* a standard PC inc and an N cycle */ \
	240	state->NextInstr \|= 3; \
	241	} } while (0)
c906108c SS	242	#define INCPC state->Reg[15] += isize ; /* a standard PC inc */ \
	243	state->NextInstr \|= 2
	244	#define FLUSHPIPE state->NextInstr \|= PRIMEPIPE
	245
	246	/***************************************************************************\
	247	* Cycle based emulation *
	248	\***************************************************************************/
	249
	250	#define OUTPUTCP(i,a,b)
	251	#define NCYCLE
	252	#define SCYCLE
	253	#define ICYCLE
	254	#define CCYCLE
	255	#define NEXTCYCLE(c)
	256
	257	/***************************************************************************\
	258	* States of the cycle based state machine *
	259	\***************************************************************************/
	260
	261
	262	/***************************************************************************\
	263	* Macros to extract parts of instructions *
	264	\***************************************************************************/
	265
	266	#define DESTReg (BITS(12,15))
	267	#define LHSReg (BITS(16,19))
	268	#define RHSReg (BITS(0,3))
	269
	270	#define DEST (state->Reg[DESTReg])
	271
	272	#ifdef MODE32
	273	#ifdef MODET
	274	#define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
	275	#else
	276	#define LHS (state->Reg[LHSReg])
	277	#endif
	278	#else
	279	#define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]) )
	280	#endif
	281
	282	#define MULDESTReg (BITS(16,19))
	283	#define MULLHSReg (BITS(0,3))
	284	#define MULRHSReg (BITS(8,11))
	285	#define MULACCReg (BITS(12,15))
	286
	287	#define DPImmRHS (ARMul_ImmedTable[BITS(0,11)])
	288	#define DPSImmRHS temp = BITS(0,11) ; \
	289	rhs = ARMul_ImmedTable[temp] ; \
	290	if (temp > 255) /* there was a shift */ \
	291	ASSIGNC(rhs >> 31) ;
	292
	293	#ifdef MODE32
	294	#define DPRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
	295	: GetDPRegRHS(state, instr))
	296	#define DPSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
	297	: GetDPSRegRHS(state, instr))
	298	#else
	299	#define DPRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
	300	: GetDPRegRHS(state, instr))
	301	#define DPSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
	302	: GetDPSRegRHS(state, instr))
	303	#endif
	304
	305	#define LSBase state->Reg[LHSReg]
306	#define LSImmRHS (BITS(0,11))
307
308	#ifdef MODE32
309	#define LSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
310	: GetLSRegRHS(state, instr))
311	#else
312	#define LSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
313	: GetLSRegRHS(state, instr))
314	#endif
315
316	#define LSMNumRegs ((ARMword)ARMul_BitList[BITS(0,7)] + \
317	(ARMword)ARMul_BitList[BITS(8,15)] )
318	#define LSMBaseFirst ((LHSReg == 0 && BIT(0)) \|\| \
319	(BIT(LHSReg) && BITS(0,LHSReg-1) == 0))
320
321	#define SWAPSRC (state->Reg[RHSReg])
322
323	#define LSCOff (BITS(0,7) << 2)
324	#define CPNum BITS(8,11)
325
326	/***************************************************************************\
327	* Macro to rotate n right by b bits *
328	\***************************************************************************/
329
330	#define ROTATER(n,b) (((n)>>(b))\|((n)<<(32-(b))))
331
332	/***************************************************************************\
333	* Macros to store results of instructions *
334	\***************************************************************************/
335
336	#define WRITEDEST(d) if (DESTReg==15) \
337	WriteR15(state, d) ; \
338	else \
339	DEST = d
340
341	#define WRITESDEST(d) if (DESTReg == 15) \
342	WriteSR15(state, d) ; \
343	else { \
344	DEST = d ; \
345	ARMul_NegZero(state, d) ; \
346	}
347
892c6b9d AO	348	#define WRITEDESTB(d) if (DESTReg == 15) \
	349	WriteR15Branch(state, d) ; \
	350	else \
	351	DEST = d
	352
c906108c SS	353	#define BYTETOBUS(data) ((data & 0xff) \| \
	354	((data & 0xff) << 8) \| \
	355	((data & 0xff) << 16) \| \
	356	((data & 0xff) << 24))
	357	#define BUSTOBYTE(address,data) \
	358	if (state->bigendSig) \
	359	temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff ; \
	360	else \
	361	temp = (data >> ((address & 3) << 3)) & 0xff
	362
	363	#define LOADMULT(instr,address,wb) LoadMult(state,instr,address,wb)
	364	#define LOADSMULT(instr,address,wb) LoadSMult(state,instr,address,wb)
	365	#define STOREMULT(instr,address,wb) StoreMult(state,instr,address,wb)
	366	#define STORESMULT(instr,address,wb) StoreSMult(state,instr,address,wb)
	367
	368	#define POSBRANCH ((instr & 0x7fffff) << 2)
fe47e8df	369	#define NEGBRANCH (0xfc000000 \| ((instr & 0xffffff) << 2))
c906108c SS	370
	371	/***************************************************************************\
	372	* Values for Emulate *
	373	\***************************************************************************/
	374
dfcd3bfb JM	375	#define STOP 0 /* stop */
	376	#define CHANGEMODE 1 /* change mode */
	377	#define ONCE 2 /* execute just one interation */
	378	#define RUN 3 /* continuous execution */
c906108c SS	379
	380	/***************************************************************************\
	381	* Stuff that is shared across modes *
	382	\***************************************************************************/
	383
dfcd3bfb JM	384	extern ARMword ARMul_Emulate26 (ARMul_State * state);
	385	extern ARMword ARMul_Emulate32 (ARMul_State * state);
	386	extern unsigned ARMul_MultTable[]; /* Number of I cycles for a mult */
	387	extern ARMword ARMul_ImmedTable[]; /* immediate DP LHS values */
	388	extern char ARMul_BitList[]; /* number of bits in a byte table */
	389	extern void ARMul_Abort26 (ARMul_State * state, ARMword);
	390	extern void ARMul_Abort32 (ARMul_State * state, ARMword);
	391	extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
	392	extern void ARMul_MSRCpsr (ARMul_State * state, ARMword instr, ARMword rhs);
	393	extern void ARMul_NegZero (ARMul_State * state, ARMword result);
	394	extern void ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b,
	395	ARMword result);
	396	extern int AddOverflow (ARMword a, ARMword b, ARMword result);
	397	extern int SubOverflow (ARMword a, ARMword b, ARMword result);
	398	extern void ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b,
	399	ARMword result);
	400	extern void ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b,
	401	ARMword result);
	402	extern void ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b,
	403	ARMword result);
	404	extern void ARMul_CPSRAltered (ARMul_State * state);
	405	extern void ARMul_R15Altered (ARMul_State * state);
	406	extern ARMword ARMul_SwitchMode (ARMul_State * state, ARMword oldmode,
	407	ARMword newmode);
	408	extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
	409	extern void ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address);
	410	extern void ARMul_STC (ARMul_State * state, ARMword instr, ARMword address);
	411	extern void ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source);
	412	extern ARMword ARMul_MRC (ARMul_State * state, ARMword instr);
	413	extern void ARMul_CDP (ARMul_State * state, ARMword instr);
	414	extern unsigned IntPending (ARMul_State * state);
	415	extern ARMword ARMul_Align (ARMul_State * state, ARMword address,
	416	ARMword data);
c906108c SS	417	#define EVENTLISTSIZE 1024L
	418
	419	/* Thumb support: */
	420
dfcd3bfb JM	421	typedef enum
	422	{
	423	t_undefined, /* undefined Thumb instruction */
	424	t_decoded, /* instruction decoded to ARM equivalent */
	425	t_branch /* Thumb branch (already processed) */
	426	}
	427	tdstate;
c906108c	428
dfcd3bfb JM	429	extern tdstate ARMul_ThumbDecode (ARMul_State * state, ARMword pc,
dfcd3bfb JM	430	ARMword tinstr, ARMword * ainstr);
c906108c SS	431
	432	/***************************************************************************\
	433	* Macros to scrutinize instructions *
	434	\***************************************************************************/
	435
	436
	437	#define UNDEF_Test
	438	#define UNDEF_Shift
	439	#define UNDEF_MSRPC
	440	#define UNDEF_MRSPC
	441	#define UNDEF_MULPCDest
	442	#define UNDEF_MULDestEQOp1
	443	#define UNDEF_LSRBPC
	444	#define UNDEF_LSRBaseEQOffWb
	445	#define UNDEF_LSRBaseEQDestWb
	446	#define UNDEF_LSRPCBaseWb
	447	#define UNDEF_LSRPCOffWb
	448	#define UNDEF_LSMNoRegs
	449	#define UNDEF_LSMPCBase
	450	#define UNDEF_LSMUserBankWb
	451	#define UNDEF_LSMBaseInListWb
	452	#define UNDEF_SWPPC
	453	#define UNDEF_CoProHS
	454	#define UNDEF_MCRPC
	455	#define UNDEF_LSCPCBaseWb
	456	#define UNDEF_UndefNotBounced
	457	#define UNDEF_ShortInt
	458	#define UNDEF_IllegalMode
	459	#define UNDEF_Prog32SigChange
	460	#define UNDEF_Data32SigChange