[deliverable/binutils-gdb.git] / sim / arm / armemu.h

/*  armemu.h -- ARMulator emulation macros:  ARM6 Instruction Emulator.
    Copyright (C) 1994 Advanced RISC Machines Ltd.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.
 
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */

extern ARMword isize;

/***************************************************************************\
*                           Condition code values                           *
\***************************************************************************/

#define EQ 0
#define NE 1
#define CS 2
#define CC 3
#define MI 4
#define PL 5
#define VS 6
#define VC 7
#define HI 8
#define LS 9
#define GE 10
#define LT 11
#define GT 12
#define LE 13
#define AL 14
#define NV 15

/***************************************************************************\
*                               Shift Opcodes                               *
\***************************************************************************/

#define LSL 0
#define LSR 1
#define ASR 2
#define ROR 3

/***************************************************************************\
*               Macros to twiddle the status flags and mode                 *
\***************************************************************************/

#define NBIT ((unsigned)1L << 31)
#define ZBIT (1L << 30)
#define CBIT (1L << 29)
#define VBIT (1L << 28)
#define SBIT (1L << 27)
#define IBIT (1L << 7)
#define FBIT (1L << 6)
#define IFBITS (3L << 6)
#define R15IBIT (1L << 27)
#define R15FBIT (1L << 26)
#define R15IFBITS (3L << 26)

#define POS(i) ( (~(i)) >> 31 )
#define NEG(i) ( (i) >> 31 )

#ifdef MODET			/* Thumb support */
/* ??? This bit is actually in the low order bit of the PC in the hardware.
   It isn't clear if the simulator needs to model that or not.  */
#define TBIT (1L << 5)
#define TFLAG state->TFlag
#define SETT state->TFlag = 1
#define CLEART state->TFlag = 0
#define ASSIGNT(res) state->TFlag = res
#define INSN_SIZE (TFLAG ? 2 : 4)
#else
#define INSN_SIZE 4
#endif

#define NFLAG state->NFlag
#define SETN state->NFlag = 1
#define CLEARN state->NFlag = 0
#define ASSIGNN(res) state->NFlag = res

#define ZFLAG state->ZFlag
#define SETZ state->ZFlag = 1
#define CLEARZ state->ZFlag = 0
#define ASSIGNZ(res) state->ZFlag = res

#define CFLAG state->CFlag
#define SETC state->CFlag = 1
#define CLEARC state->CFlag = 0
#define ASSIGNC(res) state->CFlag = res

#define VFLAG state->VFlag
#define SETV state->VFlag = 1
#define CLEARV state->VFlag = 0
#define ASSIGNV(res) state->VFlag = res

#define SFLAG state->SFlag
#define SETS state->SFlag = 1
#define CLEARS state->SFlag = 0
#define ASSIGNS(res) state->SFlag = res

#define IFLAG (state->IFFlags >> 1)
#define FFLAG (state->IFFlags & 1)
#define IFFLAGS state->IFFlags
#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;

#define PSR_FBITS (0xff000000L)
#define PSR_SBITS (0x00ff0000L)
#define PSR_XBITS (0x0000ff00L)
#define PSR_CBITS (0x000000ffL)

#if defined MODE32 || defined MODET
#define CCBITS (0xf8000000L)
#else
#define CCBITS (0xf0000000L)
#endif

#define INTBITS (0xc0L)

#if defined MODET && defined MODE32
#define PCBITS (0xffffffffL)
#else
#define PCBITS (0xfffffffcL)
#endif

#define MODEBITS (0x1fL)
#define R15INTBITS (3L << 26)

#if defined MODET && defined MODE32
#define R15PCBITS (0x03ffffffL)
#else
#define R15PCBITS (0x03fffffcL)
#endif

#define R15PCMODEBITS (0x03ffffffL)
#define R15MODEBITS (0x3L)

#ifdef MODE32
#define PCMASK PCBITS
#define PCWRAP(pc) (pc)
#else
#define PCMASK R15PCBITS
#define PCWRAP(pc) ((pc) & R15PCBITS)
#endif

#define PC (state->Reg[15] & PCMASK)
#define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS))
#define R15INT (state->Reg[15] & R15INTBITS)
#define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS))
#define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS))
#define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS))
#define R15PC (state->Reg[15] & R15PCBITS)
#define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
#define R15MODE (state->Reg[15] & R15MODEBITS)

#define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28) | (SFLAG << 27))
#define EINT (IFFLAGS << 6)
#define ER15INT (IFFLAGS << 26)
#define EMODE (state->Mode)

#ifdef MODET
#define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
#else
#define CPSR (ECC | EINT | EMODE)
#endif

#ifdef MODE32
#define PATCHR15
#else
#define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC
#endif

#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE))
#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS)
#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS)
#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS)
#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS)
#define SETR15PSR(s) if (state->Mode == USER26MODE) { \
                        state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE ; \
                        ASSIGNN((state->Reg[15] & NBIT) != 0) ; \
                        ASSIGNZ((state->Reg[15] & ZBIT) != 0) ; \
                        ASSIGNC((state->Reg[15] & CBIT) != 0) ; \
                        ASSIGNV((state->Reg[15] & VBIT) != 0) ; \
                        } \
                     else { \
                        state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)) ; \
                        ARMul_R15Altered (state) ; \
                        }
#define SETABORT(i,m,d) do { \
  int SETABORT_mode = (m); \
  ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \
  ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \
			 | (i) | SETABORT_mode)); \
  state->Reg[14] = temp - (d); \
} while (0)

#ifndef MODE32
#define VECTORS 0x20
#define LEGALADDR 0x03ffffff
#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
#define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
#endif

#define INTERNALABORT(address) if (address < VECTORS) \
                                  state->Aborted = ARMul_DataAbortV ; \
                               else \
                                  state->Aborted = ARMul_AddrExceptnV ;

#ifdef MODE32
#define TAKEABORT ARMul_Abort(state,ARMul_DataAbortV)
#else
#define TAKEABORT if (state->Aborted == ARMul_AddrExceptnV) \
                     ARMul_Abort(state,ARMul_AddrExceptnV) ; \
                  else \
                     ARMul_Abort(state,ARMul_DataAbortV)
#endif
#define CPTAKEABORT if (!state->Aborted) \
                       ARMul_Abort(state,ARMul_UndefinedInstrV) ; \
                    else if (state->Aborted == ARMul_AddrExceptnV) \
                       ARMul_Abort(state,ARMul_AddrExceptnV) ; \
                    else \
                       ARMul_Abort(state,ARMul_DataAbortV)


/***************************************************************************\
*               Different ways to start the next instruction                *
\***************************************************************************/

#define SEQ 0
#define NONSEQ 1
#define PCINCEDSEQ 2
#define PCINCEDNONSEQ 3
#define PRIMEPIPE 4
#define RESUME 8

#define NORMALCYCLE state->NextInstr = 0
#define BUSUSEDN    state->NextInstr |= 1  /* The next fetch will be an N cycle.  */
#define BUSUSEDINCPCS								\
  do										\
    {										\
      if (! state->is_v4)							\
        { 									\
	  state->Reg[15] += isize ; /* A standard PC inc and an S cycle.  */ 	\
	  state->NextInstr = (state->NextInstr & 0xff) | 2; 			\
	}									\
    }										\
  while (0)
#define BUSUSEDINCPCN								\
  do										\
    {										\
      if (state->is_v4)								\
	BUSUSEDN;								\
      else									\
	{ 									\
	  state->Reg[15] += isize ; /* A standard PC inc and an N cycle.  */	\
	  state->NextInstr |= 3;						\
	}									\
    }										\
  while (0)
#define INCPC state->Reg[15] += isize ; /* a standard PC inc */ \
              state->NextInstr |= 2
#define FLUSHPIPE state->NextInstr |= PRIMEPIPE

/***************************************************************************\
*                          Cycle based emulation                            *
\***************************************************************************/

#define OUTPUTCP(i,a,b)
#define NCYCLE
#define SCYCLE
#define ICYCLE
#define CCYCLE
#define NEXTCYCLE(c)

/***************************************************************************\
*                 States of the cycle based state machine                   *
\***************************************************************************/


/***************************************************************************\
*                 Macros to extract parts of instructions                   *
\***************************************************************************/

#define DESTReg (BITS(12,15))
#define LHSReg (BITS(16,19))
#define RHSReg (BITS(0,3))

#define DEST (state->Reg[DESTReg])

#ifdef MODE32
#ifdef MODET
#define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
#else
#define LHS (state->Reg[LHSReg])
#endif
#else
#define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]) )
#endif

#define MULDESTReg (BITS(16,19))
#define MULLHSReg (BITS(0,3))
#define MULRHSReg (BITS(8,11))
#define MULACCReg (BITS(12,15))

#define DPImmRHS (ARMul_ImmedTable[BITS(0,11)])
#define DPSImmRHS temp = BITS(0,11) ; \
                  rhs = ARMul_ImmedTable[temp] ; \
                  if (temp > 255) /* there was a shift */ \
                     ASSIGNC(rhs >> 31) ;

#ifdef MODE32
#define DPRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
                                  : GetDPRegRHS(state, instr))
#define DPSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
                                   : GetDPSRegRHS(state, instr))
#else
#define DPRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
                                  : GetDPRegRHS(state, instr))
#define DPSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
                                   : GetDPSRegRHS(state, instr))
#endif

#define LSBase state->Reg[LHSReg]
#define LSImmRHS (BITS(0,11))

#ifdef MODE32
#define LSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
                                  : GetLSRegRHS(state, instr))
#else
#define LSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
                                  : GetLSRegRHS(state, instr))
#endif

#define LSMNumRegs ((ARMword)ARMul_BitList[BITS(0,7)] + \
                    (ARMword)ARMul_BitList[BITS(8,15)] )
#define LSMBaseFirst ((LHSReg == 0 && BIT(0)) || \
                      (BIT(LHSReg) && BITS(0,LHSReg-1) == 0))

#define SWAPSRC (state->Reg[RHSReg])

#define LSCOff (BITS(0,7) << 2)
#define CPNum BITS(8,11)

/***************************************************************************\
*                    Macro to rotate n right by b bits                      *
\***************************************************************************/

#define ROTATER(n,b) (((n)>>(b))|((n)<<(32-(b))))

/***************************************************************************\
*                 Macros to store results of instructions                   *
\***************************************************************************/

#define WRITEDEST(d) if (DESTReg==15) \
                        WriteR15(state, d) ; \
                     else \
                          DEST = d

#define WRITESDEST(d) if (DESTReg == 15) \
                         WriteSR15(state, d) ; \
                      else { \
                         DEST = d ; \
                         ARMul_NegZero(state, d) ; \
                         }

#define WRITEDESTB(d) if (DESTReg == 15) \
                        WriteR15Branch(state, d) ; \
                     else \
                          DEST = d

#define BYTETOBUS(data) ((data & 0xff) | \
                        ((data & 0xff) << 8) | \
                        ((data & 0xff) << 16) | \
                        ((data & 0xff) << 24))
#define BUSTOBYTE(address,data) \
           if (state->bigendSig) \
              temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff ; \
           else \
              temp = (data >> ((address & 3) << 3)) & 0xff

#define LOADMULT(instr,address,wb) LoadMult(state,instr,address,wb)
#define LOADSMULT(instr,address,wb) LoadSMult(state,instr,address,wb)
#define STOREMULT(instr,address,wb) StoreMult(state,instr,address,wb)
#define STORESMULT(instr,address,wb) StoreSMult(state,instr,address,wb)

#define POSBRANCH ((instr & 0x7fffff) << 2)
#define NEGBRANCH ((0xff000000 |(instr & 0xffffff)) << 2)


/***************************************************************************\
*                          Values for Emulate                               *
\***************************************************************************/

#define STOP            0	/* stop */
#define CHANGEMODE      1	/* change mode */
#define ONCE            2	/* execute just one interation */
#define RUN             3	/* continuous execution */

/***************************************************************************\
*                      Stuff that is shared across modes                    *
\***************************************************************************/

extern ARMword ARMul_Emulate26 (ARMul_State * state);
extern ARMword ARMul_Emulate32 (ARMul_State * state);
extern unsigned ARMul_MultTable[];	/* Number of I cycles for a mult */
extern ARMword ARMul_ImmedTable[];	/* immediate DP LHS values */
extern char ARMul_BitList[];	/* number of bits in a byte table */
extern void ARMul_Abort26 (ARMul_State * state, ARMword);
extern void ARMul_Abort32 (ARMul_State * state, ARMword);
extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
extern void ARMul_MSRCpsr (ARMul_State * state, ARMword instr, ARMword rhs);
extern void ARMul_NegZero (ARMul_State * state, ARMword result);
extern void ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b,
			    ARMword result);
extern int AddOverflow (ARMword a, ARMword b, ARMword result);
extern int SubOverflow (ARMword a, ARMword b, ARMword result);
extern void ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b,
			       ARMword result);
extern void ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b,
			    ARMword result);
extern void ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b,
			       ARMword result);
extern void ARMul_CPSRAltered (ARMul_State * state);
extern void ARMul_R15Altered (ARMul_State * state);
extern ARMword ARMul_SwitchMode (ARMul_State * state, ARMword oldmode,
				 ARMword newmode);
extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
extern void ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address);
extern void ARMul_STC (ARMul_State * state, ARMword instr, ARMword address);
extern void ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source);
extern ARMword ARMul_MRC (ARMul_State * state, ARMword instr);
extern void ARMul_CDP (ARMul_State * state, ARMword instr);
extern unsigned IntPending (ARMul_State * state);
extern ARMword ARMul_Align (ARMul_State * state, ARMword address,
			    ARMword data);
#define EVENTLISTSIZE 1024L

/* Thumb support: */

typedef enum
{
  t_undefined,			/* undefined Thumb instruction */
  t_decoded,			/* instruction decoded to ARM equivalent */
  t_branch			/* Thumb branch (already processed) */
}
tdstate;

extern tdstate ARMul_ThumbDecode (ARMul_State * state, ARMword pc,
				  ARMword tinstr, ARMword * ainstr);

/***************************************************************************\
*                      Macros to scrutinize instructions                    *
\***************************************************************************/


#define UNDEF_Test
#define UNDEF_Shift
#define UNDEF_MSRPC
#define UNDEF_MRSPC
#define UNDEF_MULPCDest
#define UNDEF_MULDestEQOp1
#define UNDEF_LSRBPC
#define UNDEF_LSRBaseEQOffWb
#define UNDEF_LSRBaseEQDestWb
#define UNDEF_LSRPCBaseWb
#define UNDEF_LSRPCOffWb
#define UNDEF_LSMNoRegs
#define UNDEF_LSMPCBase
#define UNDEF_LSMUserBankWb
#define UNDEF_LSMBaseInListWb
#define UNDEF_SWPPC
#define UNDEF_CoProHS
#define UNDEF_MCRPC
#define UNDEF_LSCPCBaseWb
#define UNDEF_UndefNotBounced
#define UNDEF_ShortInt
#define UNDEF_IllegalMode
#define UNDEF_Prog32SigChange
#define UNDEF_Data32SigChange

/* Coprocessor support functions.  */
extern unsigned ARMul_CoProInit (ARMul_State *);
extern void     ARMul_CoProExit (ARMul_State *);
extern void     ARMul_CoProAttach (ARMul_State *, unsigned, ARMul_CPInits *, ARMul_CPExits *,
				   ARMul_LDCs *, ARMul_STCs *, ARMul_MRCs *, ARMul_MCRs *,
				   ARMul_CDPs *, ARMul_CPReads *, ARMul_CPWrites *);
extern void     ARMul_CoProDetach (ARMul_State *, unsigned);
extern void     write_cp15_reg (ARMul_State *, unsigned, unsigned, unsigned, ARMword);
extern void     write_cp14_reg (unsigned, ARMword);
extern ARMword  read_cp14_reg  (unsigned);
Commit	Line	Data
c906108c SS	1	/* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator.
	2	Copyright (C) 1994 Advanced RISC Machines Ltd.
	3
	4	This program is free software; you can redistribute it and/or modify
	5	it under the terms of the GNU General Public License as published by
	6	the Free Software Foundation; either version 2 of the License, or
	7	(at your option) any later version.
	8
	9	This program is distributed in the hope that it will be useful,
	10	but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	GNU General Public License for more details.
	13
	14	You should have received a copy of the GNU General Public License
	15	along with this program; if not, write to the Free Software
	16	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	17
	18	extern ARMword isize;
	19
	20	/***************************************************************************\
	21	* Condition code values *
	22	\***************************************************************************/
	23
	24	#define EQ 0
	25	#define NE 1
	26	#define CS 2
	27	#define CC 3
	28	#define MI 4
	29	#define PL 5
	30	#define VS 6
	31	#define VC 7
	32	#define HI 8
	33	#define LS 9
	34	#define GE 10
	35	#define LT 11
	36	#define GT 12
	37	#define LE 13
	38	#define AL 14
	39	#define NV 15
	40
	41	/***************************************************************************\
	42	* Shift Opcodes *
	43	\***************************************************************************/
	44
	45	#define LSL 0
	46	#define LSR 1
	47	#define ASR 2
	48	#define ROR 3
	49
	50	/***************************************************************************\
	51	* Macros to twiddle the status flags and mode *
	52	\***************************************************************************/
	53
	54	#define NBIT ((unsigned)1L << 31)
	55	#define ZBIT (1L << 30)
	56	#define CBIT (1L << 29)
	57	#define VBIT (1L << 28)
f1129fb8	58	#define SBIT (1L << 27)
c906108c SS	59	#define IBIT (1L << 7)
	60	#define FBIT (1L << 6)
	61	#define IFBITS (3L << 6)
	62	#define R15IBIT (1L << 27)
	63	#define R15FBIT (1L << 26)
	64	#define R15IFBITS (3L << 26)
	65
	66	#define POS(i) ( (~(i)) >> 31 )
	67	#define NEG(i) ( (i) >> 31 )
	68
dfcd3bfb	69	#ifdef MODET /* Thumb support */
c906108c SS	70	/* ??? This bit is actually in the low order bit of the PC in the hardware.
	71	It isn't clear if the simulator needs to model that or not. */
	72	#define TBIT (1L << 5)
	73	#define TFLAG state->TFlag
	74	#define SETT state->TFlag = 1
	75	#define CLEART state->TFlag = 0
	76	#define ASSIGNT(res) state->TFlag = res
e063aa3b AO	77	#define INSN_SIZE (TFLAG ? 2 : 4)
	78	#else
	79	#define INSN_SIZE 4
c906108c SS	80	#endif
	81
	82	#define NFLAG state->NFlag
	83	#define SETN state->NFlag = 1
	84	#define CLEARN state->NFlag = 0
	85	#define ASSIGNN(res) state->NFlag = res
	86
	87	#define ZFLAG state->ZFlag
	88	#define SETZ state->ZFlag = 1
	89	#define CLEARZ state->ZFlag = 0
	90	#define ASSIGNZ(res) state->ZFlag = res
	91
	92	#define CFLAG state->CFlag
	93	#define SETC state->CFlag = 1
	94	#define CLEARC state->CFlag = 0
	95	#define ASSIGNC(res) state->CFlag = res
	96
	97	#define VFLAG state->VFlag
	98	#define SETV state->VFlag = 1
	99	#define CLEARV state->VFlag = 0
	100	#define ASSIGNV(res) state->VFlag = res
	101
f1129fb8 NC	102	#define SFLAG state->SFlag
	103	#define SETS state->SFlag = 1
	104	#define CLEARS state->SFlag = 0
	105	#define ASSIGNS(res) state->SFlag = res
f743149e	106
c906108c SS	107	#define IFLAG (state->IFFlags >> 1)
	108	#define FFLAG (state->IFFlags & 1)
	109	#define IFFLAGS state->IFFlags
	110	#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
	111	#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
	112
4ef2594f AO	113	#define PSR_FBITS (0xff000000L)
	114	#define PSR_SBITS (0x00ff0000L)
	115	#define PSR_XBITS (0x0000ff00L)
	116	#define PSR_CBITS (0x000000ffL)
	117
f1129fb8 NC	118	#if defined MODE32 \|\| defined MODET
	119	#define CCBITS (0xf8000000L)
	120	#else
c906108c	121	#define CCBITS (0xf0000000L)
f1129fb8 NC	122	#endif
f1129fb8 NC	123
c906108c SS	124	#define INTBITS (0xc0L)
	125
	126	#if defined MODET && defined MODE32
	127	#define PCBITS (0xffffffffL)
	128	#else
	129	#define PCBITS (0xfffffffcL)
	130	#endif
	131
	132	#define MODEBITS (0x1fL)
	133	#define R15INTBITS (3L << 26)
	134
	135	#if defined MODET && defined MODE32
	136	#define R15PCBITS (0x03ffffffL)
	137	#else
	138	#define R15PCBITS (0x03fffffcL)
	139	#endif
	140
	141	#define R15PCMODEBITS (0x03ffffffL)
	142	#define R15MODEBITS (0x3L)
	143
	144	#ifdef MODE32
	145	#define PCMASK PCBITS
	146	#define PCWRAP(pc) (pc)
	147	#else
	148	#define PCMASK R15PCBITS
	149	#define PCWRAP(pc) ((pc) & R15PCBITS)
	150	#endif
	151
	152	#define PC (state->Reg[15] & PCMASK)
	153	#define R15CCINTMODE (state->Reg[15] & (CCBITS \| R15INTBITS \| R15MODEBITS))
	154	#define R15INT (state->Reg[15] & R15INTBITS)
	155	#define R15INTPC (state->Reg[15] & (R15INTBITS \| R15PCBITS))
	156	#define R15INTPCMODE (state->Reg[15] & (R15INTBITS \| R15PCBITS \| R15MODEBITS))
	157	#define R15INTMODE (state->Reg[15] & (R15INTBITS \| R15MODEBITS))
	158	#define R15PC (state->Reg[15] & R15PCBITS)
	159	#define R15PCMODE (state->Reg[15] & (R15PCBITS \| R15MODEBITS))
	160	#define R15MODE (state->Reg[15] & R15MODEBITS)
	161
f1129fb8	162	#define ECC ((NFLAG << 31) \| (ZFLAG << 30) \| (CFLAG << 29) \| (VFLAG << 28) \| (SFLAG << 27))
c906108c SS	163	#define EINT (IFFLAGS << 6)
	164	#define ER15INT (IFFLAGS << 26)
	165	#define EMODE (state->Mode)
	166
	167	#ifdef MODET
	168	#define CPSR (ECC \| EINT \| EMODE \| (TFLAG << 5))
	169	#else
	170	#define CPSR (ECC \| EINT \| EMODE)
	171	#endif
	172
	173	#ifdef MODE32
	174	#define PATCHR15
	175	#else
	176	#define PATCHR15 state->Reg[15] = ECC \| ER15INT \| EMODE \| R15PC
	177	#endif
	178
cf52c765	179	#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE))
4ef2594f AO	180	#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) \| ((s) & PSR_FBITS)
	181	#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) \| ((s) & PSR_SBITS)
	182	#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) \| ((s) & PSR_XBITS)
	183	#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) \| ((s) & PSR_CBITS)
c906108c SS	184	#define SETR15PSR(s) if (state->Mode == USER26MODE) { \
	185	state->Reg[15] = ((s) & CCBITS) \| R15PC \| ER15INT \| EMODE ; \
	186	ASSIGNN((state->Reg[15] & NBIT) != 0) ; \
	187	ASSIGNZ((state->Reg[15] & ZBIT) != 0) ; \
	188	ASSIGNC((state->Reg[15] & CBIT) != 0) ; \
	189	ASSIGNV((state->Reg[15] & VBIT) != 0) ; \
	190	} \
	191	else { \
6d358e86 NC	192	state->Reg[15] = R15PC \| ((s) & (CCBITS \| R15INTBITS \| R15MODEBITS)) ; \
6d358e86 NC	193	ARMul_R15Altered (state) ; \
c906108c	194	}
e063aa3b AO	195	#define SETABORT(i,m,d) do { \
	196	int SETABORT_mode = (m); \
	197	ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \
	198	ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE \| TBIT)) \
	199	\| (i) \| SETABORT_mode)); \
	200	state->Reg[14] = temp - (d); \
	201	} while (0)
c906108c SS	202
	203	#ifndef MODE32
	204	#define VECTORS 0x20
	205	#define LEGALADDR 0x03ffffff
	206	#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
	207	#define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
	208	#endif
	209
	210	#define INTERNALABORT(address) if (address < VECTORS) \
	211	state->Aborted = ARMul_DataAbortV ; \
	212	else \
	213	state->Aborted = ARMul_AddrExceptnV ;
	214
	215	#ifdef MODE32
	216	#define TAKEABORT ARMul_Abort(state,ARMul_DataAbortV)
	217	#else
	218	#define TAKEABORT if (state->Aborted == ARMul_AddrExceptnV) \
	219	ARMul_Abort(state,ARMul_AddrExceptnV) ; \
	220	else \
	221	ARMul_Abort(state,ARMul_DataAbortV)
	222	#endif
	223	#define CPTAKEABORT if (!state->Aborted) \
	224	ARMul_Abort(state,ARMul_UndefinedInstrV) ; \
	225	else if (state->Aborted == ARMul_AddrExceptnV) \
	226	ARMul_Abort(state,ARMul_AddrExceptnV) ; \
	227	else \
	228	ARMul_Abort(state,ARMul_DataAbortV)
	229
	230
	231	/***************************************************************************\
	232	* Different ways to start the next instruction *
	233	\***************************************************************************/
	234
	235	#define SEQ 0
	236	#define NONSEQ 1
	237	#define PCINCEDSEQ 2
	238	#define PCINCEDNONSEQ 3
	239	#define PRIMEPIPE 4
	240	#define RESUME 8
	241
	242	#define NORMALCYCLE state->NextInstr = 0
3943c96b NC	243	#define BUSUSEDN state->NextInstr \|= 1 /* The next fetch will be an N cycle. */
	244	#define BUSUSEDINCPCS \
	245	do \
	246	{ \
	247	if (! state->is_v4) \
	248	{ \
	249	state->Reg[15] += isize ; /* A standard PC inc and an S cycle. */ \
	250	state->NextInstr = (state->NextInstr & 0xff) \| 2; \
	251	} \
	252	} \
	253	while (0)
	254	#define BUSUSEDINCPCN \
	255	do \
	256	{ \
	257	if (state->is_v4) \
	258	BUSUSEDN; \
	259	else \
	260	{ \
	261	state->Reg[15] += isize ; /* A standard PC inc and an N cycle. */ \
	262	state->NextInstr \|= 3; \
	263	} \
	264	} \
	265	while (0)
c906108c SS	266	#define INCPC state->Reg[15] += isize ; /* a standard PC inc */ \
	267	state->NextInstr \|= 2
	268	#define FLUSHPIPE state->NextInstr \|= PRIMEPIPE
	269
	270	/***************************************************************************\
	271	* Cycle based emulation *
	272	\***************************************************************************/
	273
	274	#define OUTPUTCP(i,a,b)
	275	#define NCYCLE
	276	#define SCYCLE
	277	#define ICYCLE
	278	#define CCYCLE
	279	#define NEXTCYCLE(c)
	280
	281	/***************************************************************************\
	282	* States of the cycle based state machine *
	283	\***************************************************************************/
	284
	285
	286	/***************************************************************************\
	287	* Macros to extract parts of instructions *
	288	\***************************************************************************/
	289
	290	#define DESTReg (BITS(12,15))
	291	#define LHSReg (BITS(16,19))
	292	#define RHSReg (BITS(0,3))
	293
	294	#define DEST (state->Reg[DESTReg])
	295
	296	#ifdef MODE32
	297	#ifdef MODET
	298	#define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
	299	#else
	300	#define LHS (state->Reg[LHSReg])
	301	#endif
	302	#else
	303	#define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]) )
	304	#endif
	305
	306	#define MULDESTReg (BITS(16,19))
	307	#define MULLHSReg (BITS(0,3))
	308	#define MULRHSReg (BITS(8,11))
	309	#define MULACCReg (BITS(12,15))
	310
	311	#define DPImmRHS (ARMul_ImmedTable[BITS(0,11)])
	312	#define DPSImmRHS temp = BITS(0,11) ; \
	313	rhs = ARMul_ImmedTable[temp] ; \
	314	if (temp > 255) /* there was a shift */ \
	315	ASSIGNC(rhs >> 31) ;
	316
	317	#ifdef MODE32
	318	#define DPRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
	319	: GetDPRegRHS(state, instr))
	320	#define DPSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
	321	: GetDPSRegRHS(state, instr))
	322	#else
	323	#define DPRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
	324	: GetDPRegRHS(state, instr))
	325	#define DPSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
	326	: GetDPSRegRHS(state, instr))
	327	#endif
	328
	329	#define LSBase state->Reg[LHSReg]
330	#define LSImmRHS (BITS(0,11))
331
332	#ifdef MODE32
333	#define LSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
334	: GetLSRegRHS(state, instr))
335	#else
336	#define LSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
337	: GetLSRegRHS(state, instr))
338	#endif
339
340	#define LSMNumRegs ((ARMword)ARMul_BitList[BITS(0,7)] + \
341	(ARMword)ARMul_BitList[BITS(8,15)] )
342	#define LSMBaseFirst ((LHSReg == 0 && BIT(0)) \|\| \
343	(BIT(LHSReg) && BITS(0,LHSReg-1) == 0))
344
345	#define SWAPSRC (state->Reg[RHSReg])
346
347	#define LSCOff (BITS(0,7) << 2)
348	#define CPNum BITS(8,11)
349
350	/***************************************************************************\
351	* Macro to rotate n right by b bits *
352	\***************************************************************************/
353
354	#define ROTATER(n,b) (((n)>>(b))\|((n)<<(32-(b))))
355
356	/***************************************************************************\
357	* Macros to store results of instructions *
358	\***************************************************************************/
359
360	#define WRITEDEST(d) if (DESTReg==15) \
361	WriteR15(state, d) ; \
362	else \
363	DEST = d
364
365	#define WRITESDEST(d) if (DESTReg == 15) \
366	WriteSR15(state, d) ; \
367	else { \
368	DEST = d ; \
369	ARMul_NegZero(state, d) ; \
370	}
371
892c6b9d AO	372	#define WRITEDESTB(d) if (DESTReg == 15) \
	373	WriteR15Branch(state, d) ; \
	374	else \
	375	DEST = d
	376
c906108c SS	377	#define BYTETOBUS(data) ((data & 0xff) \| \
	378	((data & 0xff) << 8) \| \
	379	((data & 0xff) << 16) \| \
	380	((data & 0xff) << 24))
	381	#define BUSTOBYTE(address,data) \
	382	if (state->bigendSig) \
	383	temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff ; \
	384	else \
	385	temp = (data >> ((address & 3) << 3)) & 0xff
	386
	387	#define LOADMULT(instr,address,wb) LoadMult(state,instr,address,wb)
	388	#define LOADSMULT(instr,address,wb) LoadSMult(state,instr,address,wb)
	389	#define STOREMULT(instr,address,wb) StoreMult(state,instr,address,wb)
	390	#define STORESMULT(instr,address,wb) StoreSMult(state,instr,address,wb)
	391
	392	#define POSBRANCH ((instr & 0x7fffff) << 2)
179ae6ea NC	393	#define NEGBRANCH ((0xff000000 \|(instr & 0xffffff)) << 2)
179ae6ea NC	394
c906108c SS	395
	396	/***************************************************************************\
	397	* Values for Emulate *
	398	\***************************************************************************/
	399
dfcd3bfb JM	400	#define STOP 0 /* stop */
	401	#define CHANGEMODE 1 /* change mode */
	402	#define ONCE 2 /* execute just one interation */
	403	#define RUN 3 /* continuous execution */
c906108c SS	404
	405	/***************************************************************************\
	406	* Stuff that is shared across modes *
	407	\***************************************************************************/
	408
dfcd3bfb JM	409	extern ARMword ARMul_Emulate26 (ARMul_State * state);
	410	extern ARMword ARMul_Emulate32 (ARMul_State * state);
	411	extern unsigned ARMul_MultTable[]; /* Number of I cycles for a mult */
	412	extern ARMword ARMul_ImmedTable[]; /* immediate DP LHS values */
	413	extern char ARMul_BitList[]; /* number of bits in a byte table */
	414	extern void ARMul_Abort26 (ARMul_State * state, ARMword);
	415	extern void ARMul_Abort32 (ARMul_State * state, ARMword);
	416	extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
	417	extern void ARMul_MSRCpsr (ARMul_State * state, ARMword instr, ARMword rhs);
	418	extern void ARMul_NegZero (ARMul_State * state, ARMword result);
	419	extern void ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b,
	420	ARMword result);
	421	extern int AddOverflow (ARMword a, ARMword b, ARMword result);
	422	extern int SubOverflow (ARMword a, ARMword b, ARMword result);
	423	extern void ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b,
	424	ARMword result);
	425	extern void ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b,
	426	ARMword result);
	427	extern void ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b,
	428	ARMword result);
	429	extern void ARMul_CPSRAltered (ARMul_State * state);
	430	extern void ARMul_R15Altered (ARMul_State * state);
	431	extern ARMword ARMul_SwitchMode (ARMul_State * state, ARMword oldmode,
	432	ARMword newmode);
	433	extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
	434	extern void ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address);
	435	extern void ARMul_STC (ARMul_State * state, ARMword instr, ARMword address);
	436	extern void ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source);
	437	extern ARMword ARMul_MRC (ARMul_State * state, ARMword instr);
	438	extern void ARMul_CDP (ARMul_State * state, ARMword instr);
	439	extern unsigned IntPending (ARMul_State * state);
	440	extern ARMword ARMul_Align (ARMul_State * state, ARMword address,
	441	ARMword data);
c906108c SS	442	#define EVENTLISTSIZE 1024L
	443
	444	/* Thumb support: */
	445
dfcd3bfb JM	446	typedef enum
	447	{
	448	t_undefined, /* undefined Thumb instruction */
	449	t_decoded, /* instruction decoded to ARM equivalent */
	450	t_branch /* Thumb branch (already processed) */
	451	}
	452	tdstate;
c906108c	453
dfcd3bfb JM	454	extern tdstate ARMul_ThumbDecode (ARMul_State * state, ARMword pc,
dfcd3bfb JM	455	ARMword tinstr, ARMword * ainstr);
c906108c SS	456
	457	/***************************************************************************\
	458	* Macros to scrutinize instructions *
	459	\***************************************************************************/
	460
	461
	462	#define UNDEF_Test
	463	#define UNDEF_Shift
	464	#define UNDEF_MSRPC
	465	#define UNDEF_MRSPC
	466	#define UNDEF_MULPCDest
	467	#define UNDEF_MULDestEQOp1
	468	#define UNDEF_LSRBPC
	469	#define UNDEF_LSRBaseEQOffWb
	470	#define UNDEF_LSRBaseEQDestWb
	471	#define UNDEF_LSRPCBaseWb
	472	#define UNDEF_LSRPCOffWb
	473	#define UNDEF_LSMNoRegs
	474	#define UNDEF_LSMPCBase
	475	#define UNDEF_LSMUserBankWb
	476	#define UNDEF_LSMBaseInListWb
	477	#define UNDEF_SWPPC
	478	#define UNDEF_CoProHS
	479	#define UNDEF_MCRPC
	480	#define UNDEF_LSCPCBaseWb
	481	#define UNDEF_UndefNotBounced
	482	#define UNDEF_ShortInt
	483	#define UNDEF_IllegalMode
	484	#define UNDEF_Prog32SigChange
	485	#define UNDEF_Data32SigChange
f1129fb8 NC	486
	487	/* Coprocessor support functions. */
	488	extern unsigned ARMul_CoProInit (ARMul_State *);
	489	extern void ARMul_CoProExit (ARMul_State *);
	490	extern void ARMul_CoProAttach (ARMul_State , unsigned, ARMul_CPInits , ARMul_CPExits *,
	491	ARMul_LDCs , ARMul_STCs , ARMul_MRCs , ARMul_MCRs ,
	492	ARMul_CDPs , ARMul_CPReads , ARMul_CPWrites *);
	493	extern void ARMul_CoProDetach (ARMul_State *, unsigned);
917bca4f	494	extern void write_cp15_reg (ARMul_State *, unsigned, unsigned, unsigned, ARMword);
f1129fb8 NC	495	extern void write_cp14_reg (unsigned, ARMword);
f1129fb8 NC	496	extern ARMword read_cp14_reg (unsigned);