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c906108c SS |
1 | /* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator. |
2 | Copyright (C) 1994 Advanced RISC Machines Ltd. | |
3 | ||
4 | This program is free software; you can redistribute it and/or modify | |
5 | it under the terms of the GNU General Public License as published by | |
6 | the Free Software Foundation; either version 2 of the License, or | |
7 | (at your option) any later version. | |
8 | ||
9 | This program is distributed in the hope that it will be useful, | |
10 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | GNU General Public License for more details. | |
13 | ||
14 | You should have received a copy of the GNU General Public License | |
15 | along with this program; if not, write to the Free Software | |
16 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
17 | ||
18 | #include "armdefs.h" | |
19 | #include "armemu.h" | |
0f026fd0 | 20 | #include "dbg_rdi.h" |
c906108c SS |
21 | |
22 | /***************************************************************************\ | |
23 | * Definitions for the emulator architecture * | |
24 | \***************************************************************************/ | |
25 | ||
dfcd3bfb JM |
26 | void ARMul_EmulateInit (void); |
27 | ARMul_State *ARMul_NewState (void); | |
28 | void ARMul_Reset (ARMul_State * state); | |
29 | ARMword ARMul_DoCycle (ARMul_State * state); | |
30 | unsigned ARMul_DoCoPro (ARMul_State * state); | |
31 | ARMword ARMul_DoProg (ARMul_State * state); | |
32 | ARMword ARMul_DoInstr (ARMul_State * state); | |
33 | void ARMul_Abort (ARMul_State * state, ARMword address); | |
34 | ||
35 | unsigned ARMul_MultTable[32] = | |
36 | { 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, | |
37 | 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16 | |
38 | }; | |
39 | ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */ | |
40 | char ARMul_BitList[256]; /* number of bits in a byte table */ | |
c906108c SS |
41 | |
42 | /***************************************************************************\ | |
43 | * Call this routine once to set up the emulator's tables. * | |
44 | \***************************************************************************/ | |
45 | ||
dfcd3bfb JM |
46 | void |
47 | ARMul_EmulateInit (void) | |
48 | { | |
49 | unsigned long i, j; | |
c906108c | 50 | |
dfcd3bfb JM |
51 | for (i = 0; i < 4096; i++) |
52 | { /* the values of 12 bit dp rhs's */ | |
53 | ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL); | |
c906108c SS |
54 | } |
55 | ||
dfcd3bfb JM |
56 | for (i = 0; i < 256; ARMul_BitList[i++] = 0); /* how many bits in LSM */ |
57 | for (j = 1; j < 256; j <<= 1) | |
58 | for (i = 0; i < 256; i++) | |
59 | if ((i & j) > 0) | |
60 | ARMul_BitList[i]++; | |
61 | ||
62 | for (i = 0; i < 256; i++) | |
63 | ARMul_BitList[i] *= 4; /* you always need 4 times these values */ | |
c906108c | 64 | |
c906108c SS |
65 | } |
66 | ||
67 | /***************************************************************************\ | |
68 | * Returns a new instantiation of the ARMulator's state * | |
69 | \***************************************************************************/ | |
70 | ||
dfcd3bfb JM |
71 | ARMul_State * |
72 | ARMul_NewState (void) | |
73 | { | |
74 | ARMul_State *state; | |
75 | unsigned i, j; | |
76 | ||
77 | state = (ARMul_State *) malloc (sizeof (ARMul_State)); | |
78 | memset (state, 0, sizeof (ARMul_State)); | |
79 | ||
80 | state->Emulate = RUN; | |
81 | for (i = 0; i < 16; i++) | |
82 | { | |
83 | state->Reg[i] = 0; | |
84 | for (j = 0; j < 7; j++) | |
85 | state->RegBank[j][i] = 0; | |
c906108c | 86 | } |
dfcd3bfb JM |
87 | for (i = 0; i < 7; i++) |
88 | state->Spsr[i] = 0; | |
3943c96b | 89 | |
f1129fb8 NC |
90 | /* state->Mode = USER26MODE; */ |
91 | state->Mode = USER32MODE; | |
dfcd3bfb JM |
92 | |
93 | state->CallDebug = FALSE; | |
94 | state->Debug = FALSE; | |
95 | state->VectorCatch = 0; | |
96 | state->Aborted = FALSE; | |
97 | state->Reseted = FALSE; | |
98 | state->Inted = 3; | |
99 | state->LastInted = 3; | |
100 | ||
101 | state->MemDataPtr = NULL; | |
102 | state->MemInPtr = NULL; | |
103 | state->MemOutPtr = NULL; | |
104 | state->MemSparePtr = NULL; | |
105 | state->MemSize = 0; | |
106 | ||
107 | state->OSptr = NULL; | |
108 | state->CommandLine = NULL; | |
109 | ||
c3ae2f98 MG |
110 | state->CP14R0_CCD = -1; |
111 | state->LastTime = 0; | |
112 | ||
dfcd3bfb JM |
113 | state->EventSet = 0; |
114 | state->Now = 0; | |
115 | state->EventPtr = (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE * | |
116 | sizeof (struct EventNode | |
117 | *)); | |
118 | for (i = 0; i < EVENTLISTSIZE; i++) | |
119 | *(state->EventPtr + i) = NULL; | |
c906108c | 120 | |
dfcd3bfb JM |
121 | state->prog32Sig = HIGH; |
122 | state->data32Sig = HIGH; | |
c906108c | 123 | |
dfcd3bfb JM |
124 | state->lateabtSig = LOW; |
125 | state->bigendSig = LOW; | |
c906108c | 126 | |
3943c96b NC |
127 | state->is_v4 = LOW; |
128 | state->is_v5 = LOW; | |
f1129fb8 NC |
129 | state->is_v5e = LOW; |
130 | state->is_XScale = LOW; | |
0f026fd0 | 131 | state->is_iWMMXt = LOW; |
1e6b544a | 132 | |
dfcd3bfb | 133 | ARMul_Reset (state); |
3943c96b NC |
134 | |
135 | return state; | |
dfcd3bfb | 136 | } |
c906108c SS |
137 | |
138 | /***************************************************************************\ | |
3943c96b | 139 | Call this routine to set ARMulator to model certain processor properities |
c906108c | 140 | \***************************************************************************/ |
dfcd3bfb JM |
141 | |
142 | void | |
3943c96b | 143 | ARMul_SelectProcessor (ARMul_State * state, unsigned properties) |
dfcd3bfb | 144 | { |
3943c96b | 145 | if (properties & ARM_Fix26_Prop) |
dfcd3bfb JM |
146 | { |
147 | state->prog32Sig = LOW; | |
148 | state->data32Sig = LOW; | |
149 | } | |
150 | else | |
151 | { | |
152 | state->prog32Sig = HIGH; | |
153 | state->data32Sig = HIGH; | |
154 | } | |
155 | ||
c906108c | 156 | state->lateabtSig = LOW; |
1e6b544a | 157 | |
3943c96b NC |
158 | state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW; |
159 | state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW; | |
f1129fb8 NC |
160 | state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW; |
161 | state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW; | |
0f026fd0 | 162 | state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) ? HIGH : LOW; |
f603c8fe NC |
163 | state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW; |
164 | ||
165 | /* Only initialse the coprocessor support once we | |
166 | know what kind of chip we are dealing with. */ | |
167 | ARMul_CoProInit (state); | |
c906108c SS |
168 | } |
169 | ||
170 | /***************************************************************************\ | |
171 | * Call this routine to set up the initial machine state (or perform a RESET * | |
172 | \***************************************************************************/ | |
173 | ||
dfcd3bfb JM |
174 | void |
175 | ARMul_Reset (ARMul_State * state) | |
176 | { | |
177 | state->NextInstr = 0; | |
c1a72ffd | 178 | |
dfcd3bfb JM |
179 | if (state->prog32Sig) |
180 | { | |
181 | state->Reg[15] = 0; | |
182 | state->Cpsr = INTBITS | SVC32MODE; | |
c1a72ffd | 183 | state->Mode = SVC32MODE; |
c906108c | 184 | } |
dfcd3bfb JM |
185 | else |
186 | { | |
187 | state->Reg[15] = R15INTBITS | SVC26MODE; | |
188 | state->Cpsr = INTBITS | SVC26MODE; | |
c1a72ffd | 189 | state->Mode = SVC26MODE; |
c906108c | 190 | } |
c1a72ffd | 191 | |
dfcd3bfb JM |
192 | ARMul_CPSRAltered (state); |
193 | state->Bank = SVCBANK; | |
c1a72ffd | 194 | |
dfcd3bfb JM |
195 | FLUSHPIPE; |
196 | ||
197 | state->EndCondition = 0; | |
198 | state->ErrorCode = 0; | |
199 | ||
200 | state->Exception = FALSE; | |
201 | state->NresetSig = HIGH; | |
202 | state->NfiqSig = HIGH; | |
203 | state->NirqSig = HIGH; | |
204 | state->NtransSig = (state->Mode & 3) ? HIGH : LOW; | |
205 | state->abortSig = LOW; | |
206 | state->AbortAddr = 1; | |
207 | ||
208 | state->NumInstrs = 0; | |
209 | state->NumNcycles = 0; | |
210 | state->NumScycles = 0; | |
211 | state->NumIcycles = 0; | |
212 | state->NumCcycles = 0; | |
213 | state->NumFcycles = 0; | |
214 | #ifdef ASIM | |
215 | (void) ARMul_MemoryInit (); | |
216 | ARMul_OSInit (state); | |
217 | #endif | |
c906108c SS |
218 | } |
219 | ||
220 | ||
221 | /***************************************************************************\ | |
222 | * Emulate the execution of an entire program. Start the correct emulator * | |
223 | * (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the * | |
224 | * address of the last instruction that is executed. * | |
225 | \***************************************************************************/ | |
226 | ||
dfcd3bfb JM |
227 | ARMword |
228 | ARMul_DoProg (ARMul_State * state) | |
229 | { | |
230 | ARMword pc = 0; | |
231 | ||
232 | state->Emulate = RUN; | |
233 | while (state->Emulate != STOP) | |
234 | { | |
235 | state->Emulate = RUN; | |
236 | if (state->prog32Sig && ARMul_MODE32BIT) | |
237 | pc = ARMul_Emulate32 (state); | |
238 | else | |
239 | pc = ARMul_Emulate26 (state); | |
c906108c | 240 | } |
dfcd3bfb JM |
241 | return (pc); |
242 | } | |
c906108c SS |
243 | |
244 | /***************************************************************************\ | |
245 | * Emulate the execution of one instruction. Start the correct emulator * | |
246 | * (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the * | |
247 | * address of the instruction that is executed. * | |
248 | \***************************************************************************/ | |
249 | ||
dfcd3bfb JM |
250 | ARMword |
251 | ARMul_DoInstr (ARMul_State * state) | |
252 | { | |
253 | ARMword pc = 0; | |
c906108c | 254 | |
dfcd3bfb JM |
255 | state->Emulate = ONCE; |
256 | if (state->prog32Sig && ARMul_MODE32BIT) | |
257 | pc = ARMul_Emulate32 (state); | |
258 | else | |
259 | pc = ARMul_Emulate26 (state); | |
c906108c | 260 | |
dfcd3bfb JM |
261 | return (pc); |
262 | } | |
c906108c SS |
263 | |
264 | /***************************************************************************\ | |
265 | * This routine causes an Abort to occur, including selecting the correct * | |
266 | * mode, register bank, and the saving of registers. Call with the * | |
267 | * appropriate vector's memory address (0,4,8 ....) * | |
268 | \***************************************************************************/ | |
269 | ||
dfcd3bfb JM |
270 | void |
271 | ARMul_Abort (ARMul_State * state, ARMword vector) | |
272 | { | |
273 | ARMword temp; | |
e063aa3b | 274 | int isize = INSN_SIZE; |
f1129fb8 NC |
275 | int esize = (TFLAG ? 0 : 4); |
276 | int e2size = (TFLAG ? -4 : 0); | |
c906108c | 277 | |
dfcd3bfb | 278 | state->Aborted = FALSE; |
c906108c | 279 | |
dfcd3bfb JM |
280 | if (ARMul_OSException (state, vector, ARMul_GetPC (state))) |
281 | return; | |
c906108c | 282 | |
dfcd3bfb | 283 | if (state->prog32Sig) |
c906108c | 284 | if (ARMul_MODE26BIT) |
dfcd3bfb | 285 | temp = R15PC; |
c906108c | 286 | else |
dfcd3bfb JM |
287 | temp = state->Reg[15]; |
288 | else | |
289 | temp = R15PC | ECC | ER15INT | EMODE; | |
290 | ||
291 | switch (vector) | |
292 | { | |
293 | case ARMul_ResetV: /* RESET */ | |
e063aa3b | 294 | SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE, 0); |
dfcd3bfb JM |
295 | break; |
296 | case ARMul_UndefinedInstrV: /* Undefined Instruction */ | |
e063aa3b | 297 | SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE, isize); |
dfcd3bfb JM |
298 | break; |
299 | case ARMul_SWIV: /* Software Interrupt */ | |
e063aa3b | 300 | SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, isize); |
dfcd3bfb JM |
301 | break; |
302 | case ARMul_PrefetchAbortV: /* Prefetch Abort */ | |
303 | state->AbortAddr = 1; | |
f1129fb8 | 304 | SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, esize); |
dfcd3bfb JM |
305 | break; |
306 | case ARMul_DataAbortV: /* Data Abort */ | |
f1129fb8 | 307 | SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, e2size); |
dfcd3bfb JM |
308 | break; |
309 | case ARMul_AddrExceptnV: /* Address Exception */ | |
e063aa3b | 310 | SETABORT (IBIT, SVC26MODE, isize); |
dfcd3bfb JM |
311 | break; |
312 | case ARMul_IRQV: /* IRQ */ | |
57165fb4 NC |
313 | if ( ! state->is_XScale |
314 | || ! state->CPRead[13] (state, 0, & temp) | |
315 | || (temp & ARMul_CP13_R0_IRQ)) | |
c3ae2f98 | 316 | SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, esize); |
dfcd3bfb JM |
317 | break; |
318 | case ARMul_FIQV: /* FIQ */ | |
57165fb4 NC |
319 | if ( ! state->is_XScale |
320 | || ! state->CPRead[13] (state, 0, & temp) | |
321 | || (temp & ARMul_CP13_R0_FIQ)) | |
c3ae2f98 | 322 | SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, esize); |
dfcd3bfb | 323 | break; |
c906108c | 324 | } |
dfcd3bfb JM |
325 | if (ARMul_MODE32BIT) |
326 | ARMul_SetR15 (state, vector); | |
327 | else | |
328 | ARMul_SetR15 (state, R15CCINTMODE | vector); | |
0f026fd0 NC |
329 | |
330 | if (ARMul_ReadWord (state, ARMul_GetPC (state)) == 0) | |
331 | { | |
332 | /* No vector has been installed. Rather than simulating whatever | |
333 | random bits might happen to be at address 0x20 onwards we elect | |
334 | to stop. */ | |
335 | switch (vector) | |
336 | { | |
337 | case ARMul_ResetV: state->EndCondition = RDIError_Reset; break; | |
338 | case ARMul_UndefinedInstrV: state->EndCondition = RDIError_UndefinedInstruction; break; | |
339 | case ARMul_SWIV: state->EndCondition = RDIError_SoftwareInterrupt; break; | |
340 | case ARMul_PrefetchAbortV: state->EndCondition = RDIError_PrefetchAbort; break; | |
341 | case ARMul_DataAbortV: state->EndCondition = RDIError_DataAbort; break; | |
342 | case ARMul_AddrExceptnV: state->EndCondition = RDIError_AddressException; break; | |
343 | case ARMul_IRQV: state->EndCondition = RDIError_IRQ; break; | |
344 | case ARMul_FIQV: state->EndCondition = RDIError_FIQ; break; | |
345 | default: break; | |
346 | } | |
347 | state->Emulate = FALSE; | |
348 | } | |
c906108c | 349 | } |