Commit | Line | Data |
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c906108c SS |
1 | /* armos.c -- ARMulator OS interface: ARM6 Instruction Emulator. |
2 | Copyright (C) 1994 Advanced RISC Machines Ltd. | |
454de2ee | 3 | |
c906108c SS |
4 | This program is free software; you can redistribute it and/or modify |
5 | it under the terms of the GNU General Public License as published by | |
3fd725ef | 6 | the Free Software Foundation; either version 3 of the License, or |
c906108c | 7 | (at your option) any later version. |
454de2ee | 8 | |
c906108c SS |
9 | This program is distributed in the hope that it will be useful, |
10 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | GNU General Public License for more details. | |
454de2ee | 13 | |
c906108c | 14 | You should have received a copy of the GNU General Public License |
51b318de | 15 | along with this program; if not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
16 | |
17 | /* This file contains a model of Demon, ARM Ltd's Debug Monitor, | |
7f53bc35 NC |
18 | including all the SWI's required to support the C library. The code in |
19 | it is not really for the faint-hearted (especially the abort handling | |
20 | code), but it is a complete example. Defining NOOS will disable all the | |
21 | fun, and definign VAILDATE will define SWI 1 to enter SVC mode, and SWI | |
22 | 0x11 to halt the emulator. */ | |
c906108c SS |
23 | |
24 | #include "config.h" | |
6d358e86 | 25 | #include "ansidecl.h" |
c906108c SS |
26 | |
27 | #include <time.h> | |
28 | #include <errno.h> | |
2be701a3 | 29 | #include <limits.h> |
c906108c | 30 | #include <string.h> |
a4c9740c | 31 | #include "targ-vals.h" |
c906108c | 32 | |
a4c9740c MM |
33 | #ifndef TARGET_O_BINARY |
34 | #define TARGET_O_BINARY 0 | |
c906108c SS |
35 | #endif |
36 | ||
c906108c | 37 | #ifdef HAVE_UNISTD_H |
d8512e6a | 38 | #include <unistd.h> /* For SEEK_SET etc. */ |
c906108c SS |
39 | #endif |
40 | ||
c906108c SS |
41 | #include "armdefs.h" |
42 | #include "armos.h" | |
f1129fb8 NC |
43 | #include "armemu.h" |
44 | ||
c906108c SS |
45 | #ifndef NOOS |
46 | #ifndef VALIDATE | |
47 | /* #ifndef ASIM */ | |
48 | #include "armfpe.h" | |
49 | /* #endif */ | |
50 | #endif | |
51 | #endif | |
52 | ||
53 | /* For RDIError_BreakpointReached. */ | |
54 | #include "dbg_rdi.h" | |
55 | ||
3c25f8c7 | 56 | #include "gdb/callback.h" |
b3ba81f8 KS |
57 | extern host_callback *sim_callback; |
58 | ||
d8512e6a | 59 | extern unsigned ARMul_OSInit (ARMul_State *); |
d8512e6a | 60 | extern unsigned ARMul_OSHandleSWI (ARMul_State *, ARMword); |
c906108c | 61 | |
c906108c SS |
62 | #ifndef FOPEN_MAX |
63 | #define FOPEN_MAX 64 | |
64 | #endif | |
2be701a3 DJ |
65 | #ifndef PATH_MAX |
66 | #define PATH_MAX 1024 | |
67 | #endif | |
c906108c | 68 | |
7f53bc35 | 69 | /* OS private Information. */ |
c906108c | 70 | |
dfcd3bfb JM |
71 | struct OSblock |
72 | { | |
dfcd3bfb | 73 | ARMword ErrorNo; |
dfcd3bfb | 74 | }; |
c906108c | 75 | |
de4112fa NC |
76 | /* Bit mask of enabled SWI implementations. */ |
77 | unsigned int swi_mask = -1; | |
78 | ||
79 | ||
6d358e86 | 80 | static ARMword softvectorcode[] = |
7f53bc35 | 81 | { |
0f026fd0 NC |
82 | /* Installed instructions: |
83 | swi tidyexception + event; | |
84 | mov lr, pc; | |
85 | ldmia fp, {fp, pc}; | |
86 | swi generateexception + event. */ | |
7f53bc35 NC |
87 | 0xef000090, 0xe1a0e00f, 0xe89b8800, 0xef000080, /* Reset */ |
88 | 0xef000091, 0xe1a0e00f, 0xe89b8800, 0xef000081, /* Undef */ | |
89 | 0xef000092, 0xe1a0e00f, 0xe89b8800, 0xef000082, /* SWI */ | |
90 | 0xef000093, 0xe1a0e00f, 0xe89b8800, 0xef000083, /* Prefetch abort */ | |
91 | 0xef000094, 0xe1a0e00f, 0xe89b8800, 0xef000084, /* Data abort */ | |
92 | 0xef000095, 0xe1a0e00f, 0xe89b8800, 0xef000085, /* Address exception */ | |
93 | 0xef000096, 0xe1a0e00f, 0xe89b8800, 0xef000086, /* IRQ */ | |
94 | 0xef000097, 0xe1a0e00f, 0xe89b8800, 0xef000087, /* FIQ */ | |
95 | 0xef000098, 0xe1a0e00f, 0xe89b8800, 0xef000088, /* Error */ | |
96 | 0xe1a0f00e /* Default handler */ | |
c906108c SS |
97 | }; |
98 | ||
7f53bc35 | 99 | /* Time for the Operating System to initialise itself. */ |
c906108c | 100 | |
dfcd3bfb JM |
101 | unsigned |
102 | ARMul_OSInit (ARMul_State * state) | |
c906108c SS |
103 | { |
104 | #ifndef NOOS | |
105 | #ifndef VALIDATE | |
dfcd3bfb JM |
106 | ARMword instr, i, j; |
107 | struct OSblock *OSptr = (struct OSblock *) state->OSptr; | |
108 | ||
109 | if (state->OSptr == NULL) | |
110 | { | |
111 | state->OSptr = (unsigned char *) malloc (sizeof (struct OSblock)); | |
112 | if (state->OSptr == NULL) | |
113 | { | |
114 | perror ("OS Memory"); | |
115 | exit (15); | |
116 | } | |
c906108c | 117 | } |
454de2ee | 118 | |
dfcd3bfb | 119 | OSptr = (struct OSblock *) state->OSptr; |
d8512e6a NC |
120 | state->Reg[13] = ADDRSUPERSTACK; /* Set up a stack for the current mode... */ |
121 | ARMul_SetReg (state, SVC32MODE, 13, ADDRSUPERSTACK);/* ...and for supervisor mode... */ | |
122 | ARMul_SetReg (state, ABORT32MODE, 13, ADDRSUPERSTACK);/* ...and for abort 32 mode... */ | |
123 | ARMul_SetReg (state, UNDEF32MODE, 13, ADDRSUPERSTACK);/* ...and for undef 32 mode... */ | |
124 | ARMul_SetReg (state, SYSTEMMODE, 13, ADDRSUPERSTACK);/* ...and for system mode. */ | |
125 | instr = 0xe59ff000 | (ADDRSOFTVECTORS - 8); /* Load pc from soft vector */ | |
454de2ee | 126 | |
dfcd3bfb | 127 | for (i = ARMul_ResetV; i <= ARMFIQV; i += 4) |
ace4f296 NC |
128 | /* Write hardware vectors. */ |
129 | ARMul_WriteWord (state, i, instr); | |
454de2ee | 130 | |
88694af3 NC |
131 | SWI_vector_installed = 0; |
132 | ||
dfcd3bfb JM |
133 | for (i = ARMul_ResetV; i <= ARMFIQV + 4; i += 4) |
134 | { | |
135 | ARMul_WriteWord (state, ADDRSOFTVECTORS + i, SOFTVECTORCODE + i * 4); | |
136 | ARMul_WriteWord (state, ADDRSOFHANDLERS + 2 * i + 4L, | |
137 | SOFTVECTORCODE + sizeof (softvectorcode) - 4L); | |
c906108c | 138 | } |
7f53bc35 | 139 | |
dfcd3bfb JM |
140 | for (i = 0; i < sizeof (softvectorcode); i += 4) |
141 | ARMul_WriteWord (state, SOFTVECTORCODE + i, softvectorcode[i / 4]); | |
7f53bc35 | 142 | |
dfcd3bfb | 143 | ARMul_ConsolePrint (state, ", Demon 1.01"); |
c906108c SS |
144 | |
145 | /* #ifndef ASIM */ | |
146 | ||
d8512e6a NC |
147 | /* Install FPE. */ |
148 | for (i = 0; i < fpesize; i += 4) | |
149 | /* Copy the code. */ | |
dfcd3bfb | 150 | ARMul_WriteWord (state, FPESTART + i, fpecode[i >> 2]); |
7f53bc35 | 151 | |
0f026fd0 | 152 | /* Scan backwards from the end of the code. */ |
dfcd3bfb | 153 | for (i = FPESTART + fpesize;; i -= 4) |
d8512e6a | 154 | { |
0f026fd0 NC |
155 | /* When we reach the marker value, break out of |
156 | the loop, leaving i pointing at the maker. */ | |
dfcd3bfb JM |
157 | if ((j = ARMul_ReadWord (state, i)) == 0xffffffff) |
158 | break; | |
0f026fd0 NC |
159 | |
160 | /* If necessary, reverse the error strings. */ | |
dfcd3bfb | 161 | if (state->bigendSig && j < 0x80000000) |
d8512e6a NC |
162 | { |
163 | /* It's part of the string so swap it. */ | |
dfcd3bfb JM |
164 | j = ((j >> 0x18) & 0x000000ff) | |
165 | ((j >> 0x08) & 0x0000ff00) | | |
166 | ((j << 0x08) & 0x00ff0000) | ((j << 0x18) & 0xff000000); | |
167 | ARMul_WriteWord (state, i, j); | |
168 | } | |
c906108c | 169 | } |
7f53bc35 | 170 | |
d8512e6a | 171 | /* Copy old illegal instr vector. */ |
0f026fd0 | 172 | ARMul_WriteWord (state, FPEOLDVECT, ARMul_ReadWord (state, ARMUndefinedInstrV)); |
d8512e6a | 173 | /* Install new vector. */ |
0f026fd0 | 174 | ARMul_WriteWord (state, ARMUndefinedInstrV, FPENEWVECT (ARMul_ReadWord (state, i - 4))); |
dfcd3bfb | 175 | ARMul_ConsolePrint (state, ", FPE"); |
c906108c | 176 | |
6d358e86 | 177 | /* #endif ASIM */ |
c906108c SS |
178 | #endif /* VALIDATE */ |
179 | #endif /* NOOS */ | |
180 | ||
de4112fa NC |
181 | /* Intel do not want DEMON SWI support. */ |
182 | if (state->is_XScale) | |
183 | swi_mask = SWI_MASK_ANGEL; | |
10b57fcb NC |
184 | |
185 | return TRUE; | |
c906108c SS |
186 | } |
187 | ||
7f53bc35 NC |
188 | static int translate_open_mode[] = |
189 | { | |
a4c9740c MM |
190 | TARGET_O_RDONLY, /* "r" */ |
191 | TARGET_O_RDONLY + TARGET_O_BINARY, /* "rb" */ | |
192 | TARGET_O_RDWR, /* "r+" */ | |
193 | TARGET_O_RDWR + TARGET_O_BINARY, /* "r+b" */ | |
194 | TARGET_O_WRONLY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w" */ | |
195 | TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "wb" */ | |
196 | TARGET_O_RDWR + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w+" */ | |
197 | TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w+b" */ | |
198 | TARGET_O_WRONLY + TARGET_O_APPEND + TARGET_O_CREAT, /* "a" */ | |
199 | TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT, /* "ab" */ | |
200 | TARGET_O_RDWR + TARGET_O_APPEND + TARGET_O_CREAT, /* "a+" */ | |
201 | TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT /* "a+b" */ | |
c906108c SS |
202 | }; |
203 | ||
dfcd3bfb JM |
204 | static void |
205 | SWIWrite0 (ARMul_State * state, ARMword addr) | |
c906108c SS |
206 | { |
207 | ARMword temp; | |
dfcd3bfb | 208 | struct OSblock *OSptr = (struct OSblock *) state->OSptr; |
c906108c | 209 | |
917bca4f | 210 | while ((temp = ARMul_SafeReadByte (state, addr++)) != 0) |
0d9fd8f1 NC |
211 | { |
212 | char buffer = temp; | |
213 | /* Note - we cannot just cast 'temp' to a (char *) here, | |
214 | since on a big-endian host the byte value will end | |
215 | up in the wrong place and a nul character will be printed. */ | |
216 | (void) sim_callback->write_stdout (sim_callback, & buffer, 1); | |
217 | } | |
c906108c | 218 | |
b3ba81f8 | 219 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); |
c906108c SS |
220 | } |
221 | ||
dfcd3bfb JM |
222 | static void |
223 | WriteCommandLineTo (ARMul_State * state, ARMword addr) | |
c906108c SS |
224 | { |
225 | ARMword temp; | |
226 | char *cptr = state->CommandLine; | |
7f53bc35 | 227 | |
c906108c SS |
228 | if (cptr == NULL) |
229 | cptr = "\0"; | |
dfcd3bfb JM |
230 | do |
231 | { | |
232 | temp = (ARMword) * cptr++; | |
917bca4f | 233 | ARMul_SafeWriteByte (state, addr++, temp); |
dfcd3bfb JM |
234 | } |
235 | while (temp != 0); | |
c906108c SS |
236 | } |
237 | ||
2be701a3 DJ |
238 | static int |
239 | ReadFileName (ARMul_State * state, char *buf, ARMword src, size_t n) | |
240 | { | |
241 | struct OSblock *OSptr = (struct OSblock *) state->OSptr; | |
242 | char *p = buf; | |
243 | ||
244 | while (n--) | |
245 | if ((*p++ = ARMul_SafeReadByte (state, src++)) == '\0') | |
246 | return 0; | |
247 | OSptr->ErrorNo = cb_host_to_target_errno (sim_callback, ENAMETOOLONG); | |
248 | state->Reg[0] = -1; | |
249 | return -1; | |
250 | } | |
251 | ||
dfcd3bfb JM |
252 | static void |
253 | SWIopen (ARMul_State * state, ARMword name, ARMword SWIflags) | |
c906108c | 254 | { |
dfcd3bfb | 255 | struct OSblock *OSptr = (struct OSblock *) state->OSptr; |
2be701a3 | 256 | char buf[PATH_MAX]; |
c906108c | 257 | int flags; |
c906108c | 258 | |
2be701a3 DJ |
259 | if (ReadFileName (state, buf, name, sizeof buf) == -1) |
260 | return; | |
c906108c | 261 | |
7f53bc35 | 262 | /* Now we need to decode the Demon open mode. */ |
c906108c SS |
263 | flags = translate_open_mode[SWIflags]; |
264 | ||
7f53bc35 | 265 | /* Filename ":tt" is special: it denotes stdin/out. */ |
2be701a3 | 266 | if (strcmp (buf, ":tt") == 0) |
c906108c | 267 | { |
a4c9740c | 268 | if (flags == TARGET_O_RDONLY) /* opening tty "r" */ |
dfcd3bfb JM |
269 | state->Reg[0] = 0; /* stdin */ |
270 | else | |
271 | state->Reg[0] = 1; /* stdout */ | |
c906108c SS |
272 | } |
273 | else | |
274 | { | |
2be701a3 | 275 | state->Reg[0] = sim_callback->open (sim_callback, buf, flags); |
b3ba81f8 | 276 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); |
c906108c SS |
277 | } |
278 | } | |
279 | ||
dfcd3bfb JM |
280 | static void |
281 | SWIread (ARMul_State * state, ARMword f, ARMword ptr, ARMword len) | |
c906108c | 282 | { |
dfcd3bfb | 283 | struct OSblock *OSptr = (struct OSblock *) state->OSptr; |
c906108c SS |
284 | int res; |
285 | int i; | |
286 | char *local = malloc (len); | |
287 | ||
c2d11a7d JM |
288 | if (local == NULL) |
289 | { | |
d8512e6a NC |
290 | sim_callback->printf_filtered |
291 | (sim_callback, | |
292 | "sim: Unable to read 0x%ulx bytes - out of memory\n", | |
293 | len); | |
c2d11a7d JM |
294 | return; |
295 | } | |
dfcd3bfb | 296 | |
b3ba81f8 | 297 | res = sim_callback->read (sim_callback, f, local, len); |
c906108c | 298 | if (res > 0) |
dfcd3bfb | 299 | for (i = 0; i < res; i++) |
917bca4f | 300 | ARMul_SafeWriteByte (state, ptr + i, local[i]); |
7f53bc35 | 301 | |
c906108c SS |
302 | free (local); |
303 | state->Reg[0] = res == -1 ? -1 : len - res; | |
b3ba81f8 | 304 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); |
c906108c SS |
305 | } |
306 | ||
dfcd3bfb JM |
307 | static void |
308 | SWIwrite (ARMul_State * state, ARMword f, ARMword ptr, ARMword len) | |
c906108c | 309 | { |
dfcd3bfb | 310 | struct OSblock *OSptr = (struct OSblock *) state->OSptr; |
c906108c | 311 | int res; |
6d358e86 | 312 | ARMword i; |
c906108c SS |
313 | char *local = malloc (len); |
314 | ||
c2d11a7d | 315 | if (local == NULL) |
c906108c | 316 | { |
d8512e6a NC |
317 | sim_callback->printf_filtered |
318 | (sim_callback, | |
319 | "sim: Unable to write 0x%lx bytes - out of memory\n", | |
320 | (long) len); | |
c2d11a7d | 321 | return; |
c906108c | 322 | } |
dfcd3bfb JM |
323 | |
324 | for (i = 0; i < len; i++) | |
917bca4f | 325 | local[i] = ARMul_SafeReadByte (state, ptr + i); |
c2d11a7d | 326 | |
b3ba81f8 | 327 | res = sim_callback->write (sim_callback, f, local, len); |
c906108c SS |
328 | state->Reg[0] = res == -1 ? -1 : len - res; |
329 | free (local); | |
7f53bc35 | 330 | |
b3ba81f8 | 331 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); |
c906108c SS |
332 | } |
333 | ||
dfcd3bfb JM |
334 | static void |
335 | SWIflen (ARMul_State * state, ARMword fh) | |
c906108c | 336 | { |
dfcd3bfb | 337 | struct OSblock *OSptr = (struct OSblock *) state->OSptr; |
c906108c SS |
338 | ARMword addr; |
339 | ||
e1c9b6f1 | 340 | if (fh > FOPEN_MAX) |
c906108c SS |
341 | { |
342 | OSptr->ErrorNo = EBADF; | |
343 | state->Reg[0] = -1L; | |
344 | return; | |
345 | } | |
346 | ||
b3ba81f8 | 347 | addr = sim_callback->lseek (sim_callback, fh, 0, SEEK_CUR); |
6d358e86 | 348 | |
b3ba81f8 KS |
349 | state->Reg[0] = sim_callback->lseek (sim_callback, fh, 0L, SEEK_END); |
350 | (void) sim_callback->lseek (sim_callback, fh, addr, SEEK_SET); | |
c906108c | 351 | |
b3ba81f8 | 352 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); |
c906108c SS |
353 | } |
354 | ||
2be701a3 DJ |
355 | static void |
356 | SWIremove (ARMul_State * state, ARMword path) | |
357 | { | |
358 | char buf[PATH_MAX]; | |
359 | ||
360 | if (ReadFileName (state, buf, path, sizeof buf) != -1) | |
361 | { | |
362 | struct OSblock *OSptr = (struct OSblock *) state->OSptr; | |
363 | state->Reg[0] = sim_callback->unlink (sim_callback, buf); | |
364 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); | |
365 | } | |
366 | } | |
367 | ||
368 | static void | |
369 | SWIrename (ARMul_State * state, ARMword old, ARMword new) | |
370 | { | |
371 | char oldbuf[PATH_MAX], newbuf[PATH_MAX]; | |
372 | ||
373 | if (ReadFileName (state, oldbuf, old, sizeof oldbuf) != -1 | |
374 | && ReadFileName (state, newbuf, new, sizeof newbuf) != -1) | |
375 | { | |
376 | struct OSblock *OSptr = (struct OSblock *) state->OSptr; | |
377 | state->Reg[0] = sim_callback->rename (sim_callback, oldbuf, newbuf); | |
378 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); | |
379 | } | |
380 | } | |
381 | ||
7f53bc35 NC |
382 | /* The emulator calls this routine when a SWI instruction is encuntered. |
383 | The parameter passed is the SWI number (lower 24 bits of the instruction). */ | |
c906108c | 384 | |
dfcd3bfb JM |
385 | unsigned |
386 | ARMul_OSHandleSWI (ARMul_State * state, ARMword number) | |
c906108c | 387 | { |
1e5d4e46 | 388 | struct OSblock * OSptr = (struct OSblock *) state->OSptr; |
de4112fa NC |
389 | int unhandled = FALSE; |
390 | ||
c906108c SS |
391 | switch (number) |
392 | { | |
393 | case SWI_Read: | |
de4112fa NC |
394 | if (swi_mask & SWI_MASK_DEMON) |
395 | SWIread (state, state->Reg[0], state->Reg[1], state->Reg[2]); | |
396 | else | |
397 | unhandled = TRUE; | |
1e5d4e46 | 398 | break; |
c906108c SS |
399 | |
400 | case SWI_Write: | |
de4112fa NC |
401 | if (swi_mask & SWI_MASK_DEMON) |
402 | SWIwrite (state, state->Reg[0], state->Reg[1], state->Reg[2]); | |
403 | else | |
404 | unhandled = TRUE; | |
1e5d4e46 | 405 | break; |
c906108c SS |
406 | |
407 | case SWI_Open: | |
de4112fa NC |
408 | if (swi_mask & SWI_MASK_DEMON) |
409 | SWIopen (state, state->Reg[0], state->Reg[1]); | |
410 | else | |
411 | unhandled = TRUE; | |
1e5d4e46 | 412 | break; |
c906108c | 413 | |
dfcd3bfb | 414 | case SWI_Clock: |
de4112fa NC |
415 | if (swi_mask & SWI_MASK_DEMON) |
416 | { | |
417 | /* Return number of centi-seconds. */ | |
418 | state->Reg[0] = | |
c906108c | 419 | #ifdef CLOCKS_PER_SEC |
de4112fa NC |
420 | (CLOCKS_PER_SEC >= 100) |
421 | ? (ARMword) (clock () / (CLOCKS_PER_SEC / 100)) | |
422 | : (ARMword) ((clock () * 100) / CLOCKS_PER_SEC); | |
c906108c | 423 | #else |
de4112fa NC |
424 | /* Presume unix... clock() returns microseconds. */ |
425 | (ARMword) (clock () / 10000); | |
c906108c | 426 | #endif |
de4112fa NC |
427 | OSptr->ErrorNo = errno; |
428 | } | |
429 | else | |
430 | unhandled = TRUE; | |
1e5d4e46 | 431 | break; |
dfcd3bfb JM |
432 | |
433 | case SWI_Time: | |
de4112fa NC |
434 | if (swi_mask & SWI_MASK_DEMON) |
435 | { | |
436 | state->Reg[0] = (ARMword) sim_callback->time (sim_callback, NULL); | |
437 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); | |
438 | } | |
439 | else | |
440 | unhandled = TRUE; | |
1e5d4e46 | 441 | break; |
dfcd3bfb | 442 | |
c906108c | 443 | case SWI_Close: |
de4112fa NC |
444 | if (swi_mask & SWI_MASK_DEMON) |
445 | { | |
446 | state->Reg[0] = sim_callback->close (sim_callback, state->Reg[0]); | |
447 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); | |
448 | } | |
449 | else | |
450 | unhandled = TRUE; | |
1e5d4e46 | 451 | break; |
c906108c | 452 | |
dfcd3bfb | 453 | case SWI_Flen: |
de4112fa NC |
454 | if (swi_mask & SWI_MASK_DEMON) |
455 | SWIflen (state, state->Reg[0]); | |
456 | else | |
457 | unhandled = TRUE; | |
1e5d4e46 | 458 | break; |
c906108c SS |
459 | |
460 | case SWI_Exit: | |
de4112fa NC |
461 | if (swi_mask & SWI_MASK_DEMON) |
462 | state->Emulate = FALSE; | |
463 | else | |
464 | unhandled = TRUE; | |
1e5d4e46 | 465 | break; |
c906108c SS |
466 | |
467 | case SWI_Seek: | |
de4112fa NC |
468 | if (swi_mask & SWI_MASK_DEMON) |
469 | { | |
470 | /* We must return non-zero for failure. */ | |
471 | state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, state->Reg[0], state->Reg[1], SEEK_SET); | |
472 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); | |
473 | } | |
474 | else | |
475 | unhandled = TRUE; | |
1e5d4e46 | 476 | break; |
c906108c | 477 | |
dfcd3bfb | 478 | case SWI_WriteC: |
de4112fa NC |
479 | if (swi_mask & SWI_MASK_DEMON) |
480 | { | |
481 | char tmp = state->Reg[0]; | |
482 | (void) sim_callback->write_stdout (sim_callback, &tmp, 1); | |
483 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); | |
484 | } | |
485 | else | |
486 | unhandled = TRUE; | |
1e5d4e46 | 487 | break; |
c906108c | 488 | |
dfcd3bfb | 489 | case SWI_Write0: |
de4112fa NC |
490 | if (swi_mask & SWI_MASK_DEMON) |
491 | SWIWrite0 (state, state->Reg[0]); | |
492 | else | |
493 | unhandled = TRUE; | |
1e5d4e46 | 494 | break; |
c906108c | 495 | |
dfcd3bfb | 496 | case SWI_GetErrno: |
de4112fa NC |
497 | if (swi_mask & SWI_MASK_DEMON) |
498 | state->Reg[0] = OSptr->ErrorNo; | |
499 | else | |
500 | unhandled = TRUE; | |
1e5d4e46 | 501 | break; |
c906108c | 502 | |
dfcd3bfb | 503 | case SWI_GetEnv: |
de4112fa NC |
504 | if (swi_mask & SWI_MASK_DEMON) |
505 | { | |
506 | state->Reg[0] = ADDRCMDLINE; | |
507 | if (state->MemSize) | |
508 | state->Reg[1] = state->MemSize; | |
509 | else | |
510 | state->Reg[1] = ADDRUSERSTACK; | |
c906108c | 511 | |
de4112fa NC |
512 | WriteCommandLineTo (state, state->Reg[0]); |
513 | } | |
514 | else | |
515 | unhandled = TRUE; | |
1e5d4e46 | 516 | break; |
7f53bc35 | 517 | |
f1129fb8 NC |
518 | case SWI_Breakpoint: |
519 | state->EndCondition = RDIError_BreakpointReached; | |
520 | state->Emulate = FALSE; | |
1e5d4e46 | 521 | break; |
c906108c | 522 | |
2be701a3 DJ |
523 | case SWI_Remove: |
524 | if (swi_mask & SWI_MASK_DEMON) | |
525 | SWIremove (state, state->Reg[0]); | |
526 | else | |
527 | unhandled = TRUE; | |
528 | break; | |
529 | ||
530 | case SWI_Rename: | |
531 | if (swi_mask & SWI_MASK_DEMON) | |
532 | SWIrename (state, state->Reg[0], state->Reg[1]); | |
533 | else | |
534 | unhandled = TRUE; | |
535 | break; | |
536 | ||
537 | case SWI_IsTTY: | |
538 | if (swi_mask & SWI_MASK_DEMON) | |
539 | { | |
540 | state->Reg[0] = sim_callback->isatty (sim_callback, state->Reg[0]); | |
541 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); | |
542 | } | |
543 | else | |
544 | unhandled = TRUE; | |
545 | break; | |
546 | ||
7f53bc35 | 547 | /* Handle Angel SWIs as well as Demon ones. */ |
c906108c SS |
548 | case AngelSWI_ARM: |
549 | case AngelSWI_Thumb: | |
de4112fa | 550 | if (swi_mask & SWI_MASK_ANGEL) |
c906108c | 551 | { |
de4112fa NC |
552 | ARMword addr; |
553 | ARMword temp; | |
554 | ||
555 | /* R1 is almost always a parameter block. */ | |
556 | addr = state->Reg[1]; | |
557 | /* R0 is a reason code. */ | |
558 | switch (state->Reg[0]) | |
559 | { | |
c7a7b500 NC |
560 | case -1: |
561 | /* This can happen when a SWI is interrupted (eg receiving a | |
562 | ctrl-C whilst processing SWIRead()). The SWI will complete | |
563 | returning -1 in r0 to the caller. If GDB is then used to | |
564 | resume the system call the reason code will now be -1. */ | |
2ec3c90a | 565 | return TRUE; |
454de2ee | 566 | |
de4112fa NC |
567 | /* Unimplemented reason codes. */ |
568 | case AngelSWI_Reason_ReadC: | |
de4112fa | 569 | case AngelSWI_Reason_TmpNam: |
de4112fa NC |
570 | case AngelSWI_Reason_System: |
571 | case AngelSWI_Reason_EnterSVC: | |
572 | default: | |
573 | state->Emulate = FALSE; | |
574 | return FALSE; | |
575 | ||
576 | case AngelSWI_Reason_Clock: | |
577 | /* Return number of centi-seconds. */ | |
578 | state->Reg[0] = | |
c906108c | 579 | #ifdef CLOCKS_PER_SEC |
de4112fa NC |
580 | (CLOCKS_PER_SEC >= 100) |
581 | ? (ARMword) (clock () / (CLOCKS_PER_SEC / 100)) | |
582 | : (ARMword) ((clock () * 100) / CLOCKS_PER_SEC); | |
c906108c | 583 | #else |
de4112fa NC |
584 | /* Presume unix... clock() returns microseconds. */ |
585 | (ARMword) (clock () / 10000); | |
c906108c | 586 | #endif |
de4112fa NC |
587 | OSptr->ErrorNo = errno; |
588 | break; | |
589 | ||
590 | case AngelSWI_Reason_Time: | |
591 | state->Reg[0] = (ARMword) sim_callback->time (sim_callback, NULL); | |
592 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); | |
593 | break; | |
594 | ||
595 | case AngelSWI_Reason_WriteC: | |
596 | { | |
597 | char tmp = ARMul_SafeReadByte (state, addr); | |
598 | (void) sim_callback->write_stdout (sim_callback, &tmp, 1); | |
599 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); | |
600 | break; | |
601 | } | |
602 | ||
603 | case AngelSWI_Reason_Write0: | |
604 | SWIWrite0 (state, addr); | |
605 | break; | |
606 | ||
607 | case AngelSWI_Reason_Close: | |
608 | state->Reg[0] = sim_callback->close (sim_callback, ARMul_ReadWord (state, addr)); | |
609 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); | |
610 | break; | |
611 | ||
612 | case AngelSWI_Reason_Seek: | |
613 | state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, ARMul_ReadWord (state, addr), | |
614 | ARMul_ReadWord (state, addr + 4), | |
615 | SEEK_SET); | |
616 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); | |
617 | break; | |
618 | ||
619 | case AngelSWI_Reason_FLen: | |
620 | SWIflen (state, ARMul_ReadWord (state, addr)); | |
621 | break; | |
622 | ||
623 | case AngelSWI_Reason_GetCmdLine: | |
624 | WriteCommandLineTo (state, ARMul_ReadWord (state, addr)); | |
625 | break; | |
626 | ||
627 | case AngelSWI_Reason_HeapInfo: | |
628 | /* R1 is a pointer to a pointer. */ | |
629 | addr = ARMul_ReadWord (state, addr); | |
630 | ||
631 | /* Pick up the right memory limit. */ | |
632 | if (state->MemSize) | |
633 | temp = state->MemSize; | |
634 | else | |
635 | temp = ADDRUSERSTACK; | |
636 | ||
637 | ARMul_WriteWord (state, addr, 0); /* Heap base. */ | |
638 | ARMul_WriteWord (state, addr + 4, temp); /* Heap limit. */ | |
639 | ARMul_WriteWord (state, addr + 8, temp); /* Stack base. */ | |
640 | ARMul_WriteWord (state, addr + 12, temp); /* Stack limit. */ | |
641 | break; | |
642 | ||
643 | case AngelSWI_Reason_ReportException: | |
644 | if (state->Reg[1] == ADP_Stopped_ApplicationExit) | |
645 | state->Reg[0] = 0; | |
646 | else | |
647 | state->Reg[0] = -1; | |
648 | state->Emulate = FALSE; | |
649 | break; | |
650 | ||
651 | case ADP_Stopped_ApplicationExit: | |
652 | state->Reg[0] = 0; | |
653 | state->Emulate = FALSE; | |
654 | break; | |
655 | ||
656 | case ADP_Stopped_RunTimeError: | |
657 | state->Reg[0] = -1; | |
658 | state->Emulate = FALSE; | |
659 | break; | |
660 | ||
661 | case AngelSWI_Reason_Errno: | |
662 | state->Reg[0] = OSptr->ErrorNo; | |
663 | break; | |
664 | ||
665 | case AngelSWI_Reason_Open: | |
666 | SWIopen (state, | |
667 | ARMul_ReadWord (state, addr), | |
668 | ARMul_ReadWord (state, addr + 4)); | |
669 | break; | |
670 | ||
671 | case AngelSWI_Reason_Read: | |
672 | SWIread (state, | |
673 | ARMul_ReadWord (state, addr), | |
674 | ARMul_ReadWord (state, addr + 4), | |
675 | ARMul_ReadWord (state, addr + 8)); | |
676 | break; | |
677 | ||
678 | case AngelSWI_Reason_Write: | |
679 | SWIwrite (state, | |
680 | ARMul_ReadWord (state, addr), | |
681 | ARMul_ReadWord (state, addr + 4), | |
682 | ARMul_ReadWord (state, addr + 8)); | |
683 | break; | |
2be701a3 DJ |
684 | |
685 | case AngelSWI_Reason_IsTTY: | |
4b1d9c58 PB |
686 | state->Reg[0] = sim_callback->isatty (sim_callback, |
687 | ARMul_ReadWord (state, addr)); | |
2be701a3 DJ |
688 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); |
689 | break; | |
690 | ||
691 | case AngelSWI_Reason_Remove: | |
692 | SWIremove (state, | |
693 | ARMul_ReadWord (state, addr)); | |
694 | ||
695 | case AngelSWI_Reason_Rename: | |
696 | SWIrename (state, | |
697 | ARMul_ReadWord (state, addr), | |
698 | ARMul_ReadWord (state, addr + 4)); | |
de4112fa | 699 | } |
c906108c | 700 | } |
de4112fa NC |
701 | else |
702 | unhandled = TRUE; | |
703 | break; | |
c906108c | 704 | |
0f026fd0 NC |
705 | /* The following SWIs are generated by the softvectorcode[] |
706 | installed by default by the simulator. */ | |
707 | case 0x91: /* Undefined Instruction. */ | |
708 | { | |
709 | ARMword addr = state->RegBank[UNDEFBANK][14] - 4; | |
710 | ||
711 | sim_callback->printf_filtered | |
712 | (sim_callback, "sim: exception: Unhandled Instruction '0x%08x' at 0x%08x. Stopping.\n", | |
713 | ARMul_ReadWord (state, addr), addr); | |
714 | state->EndCondition = RDIError_SoftwareInterrupt; | |
715 | state->Emulate = FALSE; | |
716 | return FALSE; | |
454de2ee | 717 | } |
0f026fd0 NC |
718 | |
719 | case 0x90: /* Reset. */ | |
720 | case 0x92: /* SWI. */ | |
721 | /* These two can be safely ignored. */ | |
722 | break; | |
723 | ||
724 | case 0x93: /* Prefetch Abort. */ | |
725 | case 0x94: /* Data Abort. */ | |
726 | case 0x95: /* Address Exception. */ | |
727 | case 0x96: /* IRQ. */ | |
728 | case 0x97: /* FIQ. */ | |
729 | case 0x98: /* Error. */ | |
730 | unhandled = TRUE; | |
1e5d4e46 | 731 | break; |
0f026fd0 | 732 | |
c7a7b500 NC |
733 | case -1: |
734 | /* This can happen when a SWI is interrupted (eg receiving a | |
735 | ctrl-C whilst processing SWIRead()). The SWI will complete | |
736 | returning -1 in r0 to the caller. If GDB is then used to | |
737 | resume the system call the reason code will now be -1. */ | |
2ec3c90a | 738 | return TRUE; |
454de2ee | 739 | |
d8512e6a | 740 | case 0x180001: /* RedBoot's Syscall SWI in ARM mode. */ |
de4112fa | 741 | if (swi_mask & SWI_MASK_REDBOOT) |
d8512e6a | 742 | { |
de4112fa NC |
743 | switch (state->Reg[0]) |
744 | { | |
745 | /* These numbers are defined in libgloss/syscall.h | |
746 | but the simulator should not be dependend upon | |
747 | libgloss being installed. */ | |
748 | case 1: /* Exit. */ | |
749 | state->Emulate = FALSE; | |
750 | /* Copy exit code into r0. */ | |
751 | state->Reg[0] = state->Reg[1]; | |
752 | break; | |
753 | ||
754 | case 2: /* Open. */ | |
755 | SWIopen (state, state->Reg[1], state->Reg[2]); | |
756 | break; | |
757 | ||
758 | case 3: /* Close. */ | |
759 | state->Reg[0] = sim_callback->close (sim_callback, state->Reg[1]); | |
760 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); | |
761 | break; | |
762 | ||
763 | case 4: /* Read. */ | |
764 | SWIread (state, state->Reg[1], state->Reg[2], state->Reg[3]); | |
765 | break; | |
766 | ||
767 | case 5: /* Write. */ | |
768 | SWIwrite (state, state->Reg[1], state->Reg[2], state->Reg[3]); | |
769 | break; | |
770 | ||
771 | case 6: /* Lseek. */ | |
772 | state->Reg[0] = sim_callback->lseek (sim_callback, | |
773 | state->Reg[1], | |
774 | state->Reg[2], | |
775 | state->Reg[3]); | |
776 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); | |
777 | break; | |
778 | ||
779 | case 17: /* Utime. */ | |
73cb0348 | 780 | state->Reg[0] = state->Reg[1] = (ARMword) sim_callback->time (sim_callback, NULL); |
de4112fa NC |
781 | OSptr->ErrorNo = sim_callback->get_errno (sim_callback); |
782 | break; | |
783 | ||
784 | case 7: /* Unlink. */ | |
785 | case 8: /* Getpid. */ | |
786 | case 9: /* Kill. */ | |
787 | case 10: /* Fstat. */ | |
788 | case 11: /* Sbrk. */ | |
789 | case 12: /* Argvlen. */ | |
790 | case 13: /* Argv. */ | |
791 | case 14: /* ChDir. */ | |
792 | case 15: /* Stat. */ | |
793 | case 16: /* Chmod. */ | |
794 | case 18: /* Time. */ | |
795 | sim_callback->printf_filtered | |
796 | (sim_callback, | |
eeea4660 DJ |
797 | "sim: unhandled RedBoot syscall `%d' encountered - " |
798 | "returning ENOSYS\n", | |
de4112fa | 799 | state->Reg[0]); |
eeea4660 DJ |
800 | state->Reg[0] = -1; |
801 | OSptr->ErrorNo = cb_host_to_target_errno | |
802 | (sim_callback, ENOSYS); | |
803 | break; | |
804 | case 1001: /* Meminfo. */ | |
805 | { | |
806 | ARMword totmem = state->Reg[1], | |
807 | topmem = state->Reg[2]; | |
808 | ARMword stack = state->MemSize > 0 | |
809 | ? state->MemSize : ADDRUSERSTACK; | |
810 | if (totmem != 0) | |
811 | ARMul_WriteWord (state, totmem, stack); | |
812 | if (topmem != 0) | |
813 | ARMul_WriteWord (state, topmem, stack); | |
814 | state->Reg[0] = 0; | |
815 | break; | |
816 | } | |
de4112fa NC |
817 | |
818 | default: | |
819 | sim_callback->printf_filtered | |
820 | (sim_callback, | |
821 | "sim: unknown RedBoot syscall '%d' encountered - ignoring\n", | |
822 | state->Reg[0]); | |
823 | return FALSE; | |
824 | } | |
825 | break; | |
d8512e6a | 826 | } |
454de2ee | 827 | |
dfcd3bfb | 828 | default: |
de4112fa NC |
829 | unhandled = TRUE; |
830 | } | |
454de2ee | 831 | |
de4112fa NC |
832 | if (unhandled) |
833 | { | |
834 | if (SWI_vector_installed) | |
1e5d4e46 NC |
835 | { |
836 | ARMword cpsr; | |
837 | ARMword i_size; | |
94ab9d7b | 838 | |
1e5d4e46 NC |
839 | cpsr = ARMul_GetCPSR (state); |
840 | i_size = INSN_SIZE; | |
94ab9d7b | 841 | |
1e5d4e46 | 842 | ARMul_SetSPSR (state, SVC32MODE, cpsr); |
94ab9d7b | 843 | |
1e5d4e46 NC |
844 | cpsr &= ~0xbf; |
845 | cpsr |= SVC32MODE | 0x80; | |
846 | ARMul_SetCPSR (state, cpsr); | |
94ab9d7b | 847 | |
1e5d4e46 NC |
848 | state->RegBank[SVCBANK][14] = state->Reg[14] = state->Reg[15] - i_size; |
849 | state->NextInstr = RESUME; | |
850 | state->Reg[15] = state->pc = ARMSWIV; | |
851 | FLUSHPIPE; | |
852 | } | |
853 | else | |
854 | { | |
d8512e6a NC |
855 | sim_callback->printf_filtered |
856 | (sim_callback, | |
857 | "sim: unknown SWI encountered - %x - ignoring\n", | |
858 | number); | |
1e5d4e46 NC |
859 | return FALSE; |
860 | } | |
c906108c | 861 | } |
1e5d4e46 | 862 | |
1e5d4e46 | 863 | return TRUE; |
c906108c | 864 | } |