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c906108c SS |
1 | /* armrdi.c -- ARMulator RDI interface: ARM6 Instruction Emulator. |
2 | Copyright (C) 1994 Advanced RISC Machines Ltd. | |
3 | ||
4 | This program is free software; you can redistribute it and/or modify | |
5 | it under the terms of the GNU General Public License as published by | |
6 | the Free Software Foundation; either version 2 of the License, or | |
7 | (at your option) any later version. | |
8 | ||
9 | This program is distributed in the hope that it will be useful, | |
10 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | GNU General Public License for more details. | |
13 | ||
14 | You should have received a copy of the GNU General Public License | |
15 | along with this program; if not, write to the Free Software | |
16 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
17 | ||
18 | #include <string.h> | |
19 | #include <ctype.h> | |
20 | #include "armdefs.h" | |
21 | #include "armemu.h" | |
22 | #include "armos.h" | |
23 | #include "dbg_cp.h" | |
24 | #include "dbg_conf.h" | |
25 | #include "dbg_rdi.h" | |
26 | #include "dbg_hif.h" | |
27 | #include "communicate.h" | |
28 | ||
29 | /***************************************************************************\ | |
30 | * Declarations * | |
31 | \***************************************************************************/ | |
32 | ||
33 | #define Watch_AnyRead (RDIWatch_ByteRead+RDIWatch_HalfRead+RDIWatch_WordRead) | |
34 | #define Watch_AnyWrite (RDIWatch_ByteWrite+RDIWatch_HalfWrite+RDIWatch_WordWrite) | |
35 | ||
dfcd3bfb | 36 | static unsigned FPRegsAddr; /* last known address of FPE regs */ |
c906108c SS |
37 | #define FPESTART 0x2000L |
38 | #define FPEEND 0x8000L | |
39 | ||
40 | #define IGNORE(d) (d = d) | |
41 | #ifdef RDI_VERBOSE | |
42 | #define TracePrint(s) \ | |
43 | if (rdi_log & 1) ARMul_DebugPrint s | |
44 | #else | |
45 | #define TracePrint(s) | |
46 | #endif | |
47 | ||
dfcd3bfb JM |
48 | static ARMul_State *state = NULL; |
49 | static unsigned BreaksSet; /* The number of breakpoints set */ | |
c906108c | 50 | |
dfcd3bfb | 51 | static int rdi_log = 0; /* debugging ? */ |
c906108c SS |
52 | |
53 | #define LOWEST_RDI_LEVEL 0 | |
54 | #define HIGHEST_RDI_LEVEL 1 | |
55 | static int MYrdi_level = LOWEST_RDI_LEVEL; | |
56 | ||
57 | typedef struct BreakNode BreakNode; | |
58 | typedef struct WatchNode WatchNode; | |
59 | ||
dfcd3bfb JM |
60 | struct BreakNode |
61 | { /* A breakpoint list node */ | |
62 | BreakNode *next; | |
63 | ARMword address; /* The address of this breakpoint */ | |
64 | unsigned type; /* The type of comparison */ | |
65 | ARMword bound; /* The other address for a range */ | |
66 | ARMword inst; | |
67 | }; | |
68 | ||
69 | struct WatchNode | |
70 | { /* A watchpoint list node */ | |
71 | WatchNode *next; | |
72 | ARMword address; /* The address of this watchpoint */ | |
73 | unsigned type; /* The type of comparison */ | |
74 | unsigned datatype; /* The type of access to watch for */ | |
75 | ARMword bound; /* The other address for a range */ | |
76 | }; | |
77 | ||
78 | BreakNode *BreakList = NULL; | |
79 | WatchNode *WatchList = NULL; | |
80 | ||
81 | void | |
82 | ARMul_DebugPrint_i (const Dbg_HostosInterface * hostif, const char *format, | |
83 | ...) | |
84 | { | |
85 | va_list ap; | |
86 | va_start (ap, format); | |
87 | hostif->dbgprint (hostif->dbgarg, format, ap); | |
88 | va_end (ap); | |
c906108c SS |
89 | } |
90 | ||
dfcd3bfb JM |
91 | void |
92 | ARMul_DebugPrint (ARMul_State * state, const char *format, ...) | |
93 | { | |
94 | va_list ap; | |
95 | va_start (ap, format); | |
96 | if (!(rdi_log & 8)) | |
97 | state->hostif->dbgprint (state->hostif->dbgarg, format, ap); | |
98 | va_end (ap); | |
c906108c SS |
99 | } |
100 | ||
101 | #define CONSOLE_PRINT_MAX_LEN 128 | |
102 | ||
dfcd3bfb JM |
103 | void |
104 | ARMul_ConsolePrint (ARMul_State * state, const char *format, ...) | |
c906108c SS |
105 | { |
106 | va_list ap; | |
107 | int ch; | |
108 | char *str, buf[CONSOLE_PRINT_MAX_LEN]; | |
109 | int i, j; | |
110 | ARMword junk; | |
111 | ||
dfcd3bfb JM |
112 | va_start (ap, format); |
113 | vsprintf (buf, format, ap); | |
114 | ||
115 | for (i = 0; buf[i]; i++); /* The string is i chars long */ | |
c906108c | 116 | |
c906108c | 117 | str = buf; |
dfcd3bfb JM |
118 | while (i >= 32) |
119 | { | |
120 | MYwrite_char (kidmum[1], RDP_OSOp); | |
121 | MYwrite_word (kidmum[1], SWI_Write0); | |
122 | MYwrite_char (kidmum[1], OS_SendString); | |
123 | MYwrite_char (kidmum[1], 32); /* Send string 32bytes at a time */ | |
124 | for (j = 0; j < 32; j++, str++) | |
125 | MYwrite_char (kidmum[1], *str); | |
126 | wait_for_osreply (&junk); | |
127 | i -= 32; | |
128 | } | |
129 | ||
130 | if (i > 0) | |
131 | { | |
132 | MYwrite_char (kidmum[1], RDP_OSOp); | |
133 | MYwrite_word (kidmum[1], SWI_Write0); | |
134 | MYwrite_char (kidmum[1], OS_SendString); | |
135 | MYwrite_char (kidmum[1], (unsigned char) i); /* Send remainder of string */ | |
136 | for (j = 0; j < i; j++, str++) | |
137 | MYwrite_char (kidmum[1], *str); | |
138 | wait_for_osreply (&junk); | |
139 | } | |
c906108c SS |
140 | |
141 | va_end (ap); | |
142 | return; | |
143 | ||
144 | /* str = buf; */ | |
145 | /* while ((ch=*str++) != 0) */ | |
146 | /* state->hostif->writec(state->hostif->hostosarg, ch); */ | |
147 | } | |
148 | ||
dfcd3bfb JM |
149 | void |
150 | ARMul_DebugPause (ARMul_State * state) | |
c906108c | 151 | { |
dfcd3bfb JM |
152 | if (!(rdi_log & 8)) |
153 | state->hostif->dbgpause (state->hostif->dbgarg); | |
c906108c SS |
154 | } |
155 | ||
156 | /***************************************************************************\ | |
157 | * RDI_open * | |
158 | \***************************************************************************/ | |
159 | ||
dfcd3bfb JM |
160 | static void |
161 | InitFail (int exitcode, char const *which) | |
162 | { | |
163 | ARMul_ConsolePrint (state, "%s interface failed to initialise. Exiting\n", | |
164 | which); | |
165 | exit (exitcode); | |
c906108c SS |
166 | } |
167 | ||
dfcd3bfb JM |
168 | static void |
169 | RDIInit (unsigned type) | |
170 | { | |
171 | if (type == 0) | |
172 | { /* cold start */ | |
173 | state->CallDebug = state->MemReadDebug = state->MemWriteDebug = 0; | |
174 | BreaksSet = 0; | |
c906108c | 175 | } |
dfcd3bfb | 176 | } |
c906108c SS |
177 | |
178 | #define UNKNOWNPROC 0 | |
179 | ||
dfcd3bfb JM |
180 | typedef struct |
181 | { | |
182 | char name[16]; | |
183 | unsigned val; | |
184 | } | |
185 | Processor; | |
186 | ||
187 | Processor const p_arm2 = { "ARM2", ARM2 }; | |
188 | Processor const p_arm2as = { "ARM2AS", ARM2as }; | |
189 | Processor const p_arm61 = { "ARM61", ARM61 }; | |
190 | Processor const p_arm3 = { "ARM3", ARM3 }; | |
191 | Processor const p_arm6 = { "ARM6", ARM6 }; | |
192 | Processor const p_arm60 = { "ARM60", ARM60 }; | |
193 | Processor const p_arm600 = { "ARM600", ARM600 }; | |
194 | Processor const p_arm610 = { "ARM610", ARM610 }; | |
195 | Processor const p_arm620 = { "ARM620", ARM620 }; | |
196 | Processor const p_unknown = { "", UNKNOWNPROC }; | |
c906108c SS |
197 | |
198 | Processor const *const processors[] = { | |
dfcd3bfb | 199 | &p_arm6, /* default: must come first */ |
c906108c SS |
200 | &p_arm2, |
201 | &p_arm2as, | |
202 | &p_arm61, | |
203 | &p_arm3, | |
204 | &p_arm60, | |
205 | &p_arm600, | |
206 | &p_arm610, | |
207 | &p_arm620, | |
208 | &p_unknown | |
209 | }; | |
210 | ||
211 | typedef struct ProcessorConfig ProcessorConfig; | |
dfcd3bfb JM |
212 | struct ProcessorConfig |
213 | { | |
c906108c SS |
214 | long id[2]; |
215 | ProcessorConfig const *self; | |
216 | long count; | |
dfcd3bfb | 217 | Processor const *const *processors; |
c906108c SS |
218 | }; |
219 | ||
220 | ProcessorConfig const processorconfig = { | |
dfcd3bfb JM |
221 | {((((((long) 'x' << 8) | ' ') << 8) | 'c') << 8) | 'p', |
222 | ((((((long) 'u' << 8) | 's') << 8) | ' ') << 8) | 'x'}, | |
c906108c SS |
223 | &processorconfig, |
224 | 16, | |
225 | processors | |
226 | }; | |
227 | ||
dfcd3bfb JM |
228 | static int |
229 | RDI_open (unsigned type, const Dbg_ConfigBlock * config, | |
230 | const Dbg_HostosInterface * hostif, struct Dbg_MCState *dbg_state) | |
c906108c | 231 | /* Initialise everything */ |
dfcd3bfb JM |
232 | { |
233 | int virgin = (state == NULL); | |
234 | IGNORE (dbg_state); | |
c906108c SS |
235 | |
236 | #ifdef RDI_VERBOSE | |
dfcd3bfb JM |
237 | if (rdi_log & 1) |
238 | { | |
239 | if (virgin) | |
240 | ARMul_DebugPrint_i (hostif, "RDI_open: type = %d\n", type); | |
241 | else | |
242 | ARMul_DebugPrint (state, "RDI_open: type = %d\n", type); | |
243 | } | |
c906108c SS |
244 | #endif |
245 | ||
dfcd3bfb JM |
246 | if (type & 1) |
247 | { /* Warm start */ | |
248 | ARMul_Reset (state); | |
249 | RDIInit (1); | |
c906108c | 250 | } |
dfcd3bfb JM |
251 | else |
252 | { | |
253 | if (virgin) | |
254 | { | |
255 | ARMul_EmulateInit (); | |
256 | state = ARMul_NewState (); | |
257 | state->hostif = hostif; | |
258 | { | |
259 | int req = config->processor; | |
260 | unsigned processor = processors[req]->val; | |
261 | ARMul_SelectProcessor (state, processor); | |
262 | ARMul_Reset (state); | |
263 | ARMul_ConsolePrint (state, "ARMulator V1.50, %s", | |
264 | processors[req]->name); | |
265 | } | |
266 | if (ARMul_MemoryInit (state, config->memorysize) == FALSE) | |
267 | InitFail (1, "Memory"); | |
268 | if (config->bytesex != RDISex_DontCare) | |
269 | state->bigendSig = config->bytesex; | |
270 | if (ARMul_CoProInit (state) == FALSE) | |
271 | InitFail (2, "Co-Processor"); | |
272 | if (ARMul_OSInit (state) == FALSE) | |
273 | InitFail (3, "Operating System"); | |
274 | } | |
275 | ARMul_Reset (state); | |
276 | RDIInit (0); | |
277 | } | |
278 | if (type & 2) | |
279 | { /* Reset the comms link */ | |
280 | /* what comms link ? */ | |
281 | } | |
282 | if (virgin && (type & 1) == 0) /* Cold start */ | |
283 | ARMul_ConsolePrint (state, ", %s endian.\n", | |
284 | state->bigendSig ? "Big" : "Little"); | |
c906108c SS |
285 | |
286 | if (config->bytesex == RDISex_DontCare) | |
dfcd3bfb | 287 | return (state->bigendSig ? RDIError_BigEndian : RDIError_LittleEndian); |
c906108c | 288 | else |
dfcd3bfb | 289 | return (RDIError_NoError); |
c906108c SS |
290 | } |
291 | ||
292 | /***************************************************************************\ | |
293 | * RDI_close * | |
294 | \***************************************************************************/ | |
295 | ||
dfcd3bfb JM |
296 | static int |
297 | RDI_close (void) | |
c906108c | 298 | { |
dfcd3bfb JM |
299 | TracePrint ((state, "RDI_close\n")); |
300 | ARMul_OSExit (state); | |
301 | ARMul_CoProExit (state); | |
302 | ARMul_MemoryExit (state); | |
303 | return (RDIError_NoError); | |
304 | } | |
c906108c SS |
305 | |
306 | /***************************************************************************\ | |
307 | * RDI_read * | |
308 | \***************************************************************************/ | |
309 | ||
dfcd3bfb JM |
310 | static int |
311 | RDI_read (ARMword source, void *dest, unsigned *nbytes) | |
312 | { | |
313 | unsigned i; | |
314 | char *memptr = (char *) dest; | |
315 | ||
316 | TracePrint ((state, "RDI_read: source=%.8lx dest=%p nbytes=%.8x\n", | |
317 | source, dest, *nbytes)); | |
318 | ||
319 | for (i = 0; i < *nbytes; i++) | |
320 | *memptr++ = (char) ARMul_ReadByte (state, source++); | |
321 | if (state->abortSig) | |
322 | { | |
323 | state->abortSig = LOW; | |
324 | return (RDIError_DataAbort); | |
c906108c | 325 | } |
dfcd3bfb JM |
326 | return (RDIError_NoError); |
327 | } | |
c906108c SS |
328 | |
329 | /***************************************************************************\ | |
330 | * RDI_write * | |
331 | \***************************************************************************/ | |
332 | ||
dfcd3bfb JM |
333 | static int |
334 | RDI_write (const void *source, ARMword dest, unsigned *nbytes) | |
335 | { | |
336 | unsigned i; | |
337 | char *memptr = (char *) source; | |
c906108c | 338 | |
dfcd3bfb JM |
339 | TracePrint ((state, "RDI_write: source=%p dest=%.8lx nbytes=%.8x\n", |
340 | source, dest, *nbytes)); | |
c906108c | 341 | |
dfcd3bfb JM |
342 | for (i = 0; i < *nbytes; i++) |
343 | ARMul_WriteByte (state, (ARMword) dest++, (ARMword) * memptr++); | |
c906108c | 344 | |
dfcd3bfb JM |
345 | if (state->abortSig) |
346 | { | |
347 | state->abortSig = LOW; | |
348 | return (RDIError_DataAbort); | |
c906108c | 349 | } |
dfcd3bfb JM |
350 | return (RDIError_NoError); |
351 | } | |
c906108c SS |
352 | |
353 | /***************************************************************************\ | |
354 | * RDI_CPUread * | |
355 | \***************************************************************************/ | |
356 | ||
dfcd3bfb JM |
357 | static int |
358 | RDI_CPUread (unsigned mode, unsigned long mask, ARMword buffer[]) | |
359 | { | |
360 | unsigned i, upto; | |
c906108c | 361 | |
dfcd3bfb JM |
362 | if (mode == RDIMode_Curr) |
363 | mode = (unsigned) (ARMul_GetCPSR (state) & MODEBITS); | |
c906108c | 364 | |
dfcd3bfb JM |
365 | for (upto = 0, i = 0; i < 15; i++) |
366 | if (mask & (1L << i)) | |
367 | { | |
368 | buffer[upto++] = ARMul_GetReg (state, mode, i); | |
369 | } | |
c906108c | 370 | |
dfcd3bfb JM |
371 | if (mask & RDIReg_R15) |
372 | { | |
373 | buffer[upto++] = ARMul_GetR15 (state); | |
374 | } | |
c906108c | 375 | |
dfcd3bfb JM |
376 | if (mask & RDIReg_PC) |
377 | { | |
378 | buffer[upto++] = ARMul_GetPC (state); | |
379 | } | |
c906108c | 380 | |
dfcd3bfb JM |
381 | if (mask & RDIReg_CPSR) |
382 | buffer[upto++] = ARMul_GetCPSR (state); | |
c906108c | 383 | |
dfcd3bfb JM |
384 | if (mask & RDIReg_SPSR) |
385 | buffer[upto++] = ARMul_GetSPSR (state, mode); | |
c906108c | 386 | |
dfcd3bfb | 387 | TracePrint ((state, "RDI_CPUread: mode=%.8x mask=%.8lx", mode, mask)); |
c906108c | 388 | #ifdef RDI_VERBOSE |
dfcd3bfb JM |
389 | if (rdi_log & 1) |
390 | { | |
391 | for (upto = 0, i = 0; i <= 20; i++) | |
392 | if (mask & (1L << i)) | |
393 | { | |
394 | ARMul_DebugPrint (state, "%c%.8lx", upto % 4 == 0 ? '\n' : ' ', | |
395 | buffer[upto]); | |
396 | upto++; | |
397 | } | |
398 | ARMul_DebugPrint (state, "\n"); | |
c906108c SS |
399 | } |
400 | #endif | |
401 | ||
dfcd3bfb | 402 | return (RDIError_NoError); |
c906108c SS |
403 | } |
404 | ||
405 | /***************************************************************************\ | |
406 | * RDI_CPUwrite * | |
407 | \***************************************************************************/ | |
408 | ||
dfcd3bfb JM |
409 | static int |
410 | RDI_CPUwrite (unsigned mode, unsigned long mask, ARMword const buffer[]) | |
411 | { | |
412 | int i, upto; | |
c906108c SS |
413 | |
414 | ||
dfcd3bfb | 415 | TracePrint ((state, "RDI_CPUwrite: mode=%.8x mask=%.8lx", mode, mask)); |
c906108c | 416 | #ifdef RDI_VERBOSE |
dfcd3bfb JM |
417 | if (rdi_log & 1) |
418 | { | |
419 | for (upto = 0, i = 0; i <= 20; i++) | |
420 | if (mask & (1L << i)) | |
421 | { | |
422 | ARMul_DebugPrint (state, "%c%.8lx", upto % 4 == 0 ? '\n' : ' ', | |
423 | buffer[upto]); | |
424 | upto++; | |
425 | } | |
426 | ARMul_DebugPrint (state, "\n"); | |
c906108c SS |
427 | } |
428 | #endif | |
429 | ||
dfcd3bfb JM |
430 | if (mode == RDIMode_Curr) |
431 | mode = (unsigned) (ARMul_GetCPSR (state) & MODEBITS); | |
c906108c | 432 | |
dfcd3bfb | 433 | for (upto = 0, i = 0; i < 15; i++) |
c906108c | 434 | if (mask & (1L << i)) |
dfcd3bfb | 435 | ARMul_SetReg (state, mode, i, buffer[upto++]); |
c906108c | 436 | |
dfcd3bfb JM |
437 | if (mask & RDIReg_R15) |
438 | ARMul_SetR15 (state, buffer[upto++]); | |
c906108c | 439 | |
dfcd3bfb JM |
440 | if (mask & RDIReg_PC) |
441 | { | |
c906108c | 442 | |
dfcd3bfb JM |
443 | ARMul_SetPC (state, buffer[upto++]); |
444 | } | |
445 | if (mask & RDIReg_CPSR) | |
446 | ARMul_SetCPSR (state, buffer[upto++]); | |
c906108c | 447 | |
dfcd3bfb JM |
448 | if (mask & RDIReg_SPSR) |
449 | ARMul_SetSPSR (state, mode, buffer[upto++]); | |
c906108c | 450 | |
dfcd3bfb | 451 | return (RDIError_NoError); |
c906108c SS |
452 | } |
453 | ||
454 | /***************************************************************************\ | |
455 | * RDI_CPread * | |
456 | \***************************************************************************/ | |
457 | ||
dfcd3bfb JM |
458 | static int |
459 | RDI_CPread (unsigned CPnum, unsigned long mask, ARMword buffer[]) | |
460 | { | |
461 | ARMword fpregsaddr, word[4]; | |
462 | ||
463 | unsigned r, w; | |
464 | unsigned upto; | |
465 | ||
466 | if (CPnum != 1 && CPnum != 2) | |
467 | { | |
468 | unsigned char const *rmap = state->CPRegWords[CPnum]; | |
469 | if (rmap == NULL) | |
470 | return (RDIError_UnknownCoPro); | |
471 | for (upto = 0, r = 0; r < rmap[-1]; r++) | |
472 | if (mask & (1L << r)) | |
473 | { | |
474 | (void) state->CPRead[CPnum] (state, r, &buffer[upto]); | |
475 | upto += rmap[r]; | |
476 | } | |
477 | TracePrint ((state, "RDI_CPread: CPnum=%d mask=%.8lx", CPnum, mask)); | |
c906108c | 478 | #ifdef RDI_VERBOSE |
dfcd3bfb JM |
479 | if (rdi_log & 1) |
480 | { | |
481 | w = 0; | |
482 | for (upto = 0, r = 0; r < rmap[-1]; r++) | |
483 | if (mask & (1L << r)) | |
484 | { | |
485 | int words = rmap[r]; | |
486 | ARMul_DebugPrint (state, "%c%2d", | |
487 | (w >= 4 ? (w = 0, '\n') : ' '), r); | |
488 | while (--words >= 0) | |
489 | { | |
490 | ARMul_DebugPrint (state, " %.8lx", buffer[upto++]); | |
491 | w++; | |
492 | } | |
493 | } | |
494 | ARMul_DebugPrint (state, "\n"); | |
495 | } | |
c906108c | 496 | #endif |
dfcd3bfb JM |
497 | return RDIError_NoError; |
498 | } | |
c906108c SS |
499 | |
500 | #ifdef NOFPE | |
dfcd3bfb | 501 | return RDIError_UnknownCoPro; |
c906108c SS |
502 | |
503 | #else | |
dfcd3bfb JM |
504 | if (FPRegsAddr == 0) |
505 | { | |
506 | fpregsaddr = ARMul_ReadWord (state, 4L); | |
507 | if ((fpregsaddr & 0xff800000) != 0xea000000) /* Must be a forward branch */ | |
508 | return RDIError_UnknownCoPro; | |
509 | fpregsaddr = ((fpregsaddr & 0xffffff) << 2) + 8; /* address in __fp_decode - 4 */ | |
510 | if ((fpregsaddr < FPESTART) || (fpregsaddr >= FPEEND)) | |
511 | return RDIError_UnknownCoPro; | |
512 | fpregsaddr = ARMul_ReadWord (state, fpregsaddr); /* pointer to fp registers */ | |
513 | FPRegsAddr = fpregsaddr; | |
c906108c | 514 | } |
dfcd3bfb JM |
515 | else |
516 | fpregsaddr = FPRegsAddr; | |
517 | ||
518 | if (fpregsaddr == 0) | |
519 | return RDIError_UnknownCoPro; | |
520 | for (upto = 0, r = 0; r < 8; r++) | |
521 | if (mask & (1L << r)) | |
522 | { | |
523 | for (w = 0; w < 4; w++) | |
524 | word[w] = | |
525 | ARMul_ReadWord (state, | |
526 | fpregsaddr + (ARMword) r * 16 + (ARMword) w * 4); | |
527 | switch ((int) (word[3] >> 29)) | |
528 | { | |
529 | case 0: | |
530 | case 2: | |
531 | case 4: | |
532 | case 6: /* its unpacked, convert to extended */ | |
533 | buffer[upto++] = 2; /* mark as extended */ | |
534 | buffer[upto++] = (word[3] & 0x7fff) | (word[0] & 0x80000000); /* exp and sign */ | |
535 | buffer[upto++] = word[1]; /* mantissa 1 */ | |
536 | buffer[upto++] = word[2]; /* mantissa 2 */ | |
537 | break; | |
538 | case 1: /* packed single */ | |
539 | buffer[upto++] = 0; /* mark as single */ | |
540 | buffer[upto++] = word[0]; /* sign, exp and mantissa */ | |
541 | buffer[upto++] = word[1]; /* padding */ | |
542 | buffer[upto++] = word[2]; /* padding */ | |
543 | break; | |
544 | case 3: /* packed double */ | |
545 | buffer[upto++] = 1; /* mark as double */ | |
546 | buffer[upto++] = word[0]; /* sign, exp and mantissa1 */ | |
547 | buffer[upto++] = word[1]; /* mantissa 2 */ | |
548 | buffer[upto++] = word[2]; /* padding */ | |
549 | break; | |
550 | case 5: /* packed extended */ | |
551 | buffer[upto++] = 2; /* mark as extended */ | |
552 | buffer[upto++] = word[0]; /* sign and exp */ | |
553 | buffer[upto++] = word[1]; /* mantissa 1 */ | |
554 | buffer[upto++] = word[2]; /* mantissa 2 */ | |
555 | break; | |
556 | case 7: /* packed decimal */ | |
557 | buffer[upto++] = 3; /* mark as packed decimal */ | |
558 | buffer[upto++] = word[0]; /* sign, exp and mantissa1 */ | |
559 | buffer[upto++] = word[1]; /* mantissa 2 */ | |
560 | buffer[upto++] = word[2]; /* mantissa 3 */ | |
561 | break; | |
562 | } | |
563 | } | |
564 | if (mask & (1L << r)) | |
565 | buffer[upto++] = ARMul_ReadWord (state, fpregsaddr + 128); /* fpsr */ | |
566 | if (mask & (1L << (r + 1))) | |
567 | buffer[upto++] = 0; /* fpcr */ | |
c906108c | 568 | |
dfcd3bfb | 569 | TracePrint ((state, "RDI_CPread: CPnum=%d mask=%.8lx\n", CPnum, mask)); |
c906108c | 570 | #ifdef RDI_VERBOSE |
dfcd3bfb JM |
571 | if (rdi_log & 1) |
572 | { | |
573 | for (upto = 0, r = 0; r < 9; r++) | |
574 | if (mask & (1L << r)) | |
575 | { | |
576 | if (r != 8) | |
577 | { | |
578 | ARMul_DebugPrint (state, "%08lx ", buffer[upto++]); | |
579 | ARMul_DebugPrint (state, "%08lx ", buffer[upto++]); | |
580 | ARMul_DebugPrint (state, "%08lx ", buffer[upto++]); | |
581 | } | |
582 | ARMul_DebugPrint (state, "%08lx\n", buffer[upto++]); | |
583 | } | |
584 | ARMul_DebugPrint (state, "\n"); | |
c906108c SS |
585 | } |
586 | #endif | |
dfcd3bfb | 587 | return (RDIError_NoError); |
c906108c | 588 | #endif /* NOFPE */ |
dfcd3bfb | 589 | } |
c906108c SS |
590 | |
591 | /***************************************************************************\ | |
592 | * RDI_CPwrite * | |
593 | \***************************************************************************/ | |
594 | ||
dfcd3bfb JM |
595 | static int |
596 | RDI_CPwrite (unsigned CPnum, unsigned long mask, ARMword const buffer[]) | |
597 | { | |
598 | unsigned r; | |
599 | unsigned upto; | |
600 | ARMword fpregsaddr; | |
601 | ||
602 | if (CPnum != 1 && CPnum != 2) | |
603 | { | |
604 | unsigned char const *rmap = state->CPRegWords[CPnum]; | |
605 | if (rmap == NULL) | |
606 | return (RDIError_UnknownCoPro); | |
607 | TracePrint ((state, "RDI_CPwrite: CPnum=%d mask=%.8lx", CPnum, mask)); | |
c906108c | 608 | #ifdef RDI_VERBOSE |
dfcd3bfb JM |
609 | if (rdi_log & 1) |
610 | { | |
611 | int w = 0; | |
612 | for (upto = 0, r = 0; r < rmap[-1]; r++) | |
613 | if (mask & (1L << r)) | |
614 | { | |
615 | int words = rmap[r]; | |
616 | ARMul_DebugPrint (state, "%c%2d", | |
617 | (w >= 4 ? (w = 0, '\n') : ' '), r); | |
618 | while (--words >= 0) | |
619 | { | |
620 | ARMul_DebugPrint (state, " %.8lx", buffer[upto++]); | |
621 | w++; | |
622 | } | |
623 | } | |
624 | ARMul_DebugPrint (state, "\n"); | |
625 | } | |
c906108c | 626 | #endif |
dfcd3bfb JM |
627 | for (upto = 0, r = 0; r < rmap[-1]; r++) |
628 | if (mask & (1L << r)) | |
629 | { | |
630 | (void) state->CPWrite[CPnum] (state, r, &buffer[upto]); | |
631 | upto += rmap[r]; | |
632 | } | |
633 | return RDIError_NoError; | |
634 | } | |
c906108c SS |
635 | |
636 | #ifdef NOFPE | |
dfcd3bfb | 637 | return RDIError_UnknownCoPro; |
c906108c SS |
638 | |
639 | #else | |
dfcd3bfb | 640 | TracePrint ((state, "RDI_CPwrite: CPnum=%d mask=%.8lx", CPnum, mask)); |
c906108c | 641 | #ifdef RDI_VERBOSE |
dfcd3bfb JM |
642 | if (rdi_log & 1) |
643 | { | |
644 | for (upto = 0, r = 0; r < 9; r++) | |
645 | if (mask & (1L << r)) | |
646 | { | |
647 | if (r != 8) | |
648 | { | |
649 | ARMul_DebugPrint (state, "%08lx ", buffer[upto++]); | |
650 | ARMul_DebugPrint (state, "%08lx ", buffer[upto++]); | |
651 | ARMul_DebugPrint (state, "%08lx ", buffer[upto++]); | |
652 | } | |
653 | ARMul_DebugPrint (state, "%08lx\n", buffer[upto++]); | |
654 | } | |
655 | ARMul_DebugPrint (state, "\n"); | |
656 | } | |
c906108c SS |
657 | #endif |
658 | ||
dfcd3bfb JM |
659 | if (FPRegsAddr == 0) |
660 | { | |
661 | fpregsaddr = ARMul_ReadWord (state, 4L); | |
662 | if ((fpregsaddr & 0xff800000) != 0xea000000) /* Must be a forward branch */ | |
663 | return RDIError_UnknownCoPro; | |
664 | fpregsaddr = ((fpregsaddr & 0xffffff) << 2) + 8; /* address in __fp_decode - 4 */ | |
665 | if ((fpregsaddr < FPESTART) || (fpregsaddr >= FPEEND)) | |
666 | return RDIError_UnknownCoPro; | |
667 | fpregsaddr = ARMul_ReadWord (state, fpregsaddr); /* pointer to fp registers */ | |
668 | FPRegsAddr = fpregsaddr; | |
c906108c | 669 | } |
dfcd3bfb JM |
670 | else |
671 | fpregsaddr = FPRegsAddr; | |
672 | ||
673 | if (fpregsaddr == 0) | |
674 | return RDIError_UnknownCoPro; | |
675 | for (upto = 0, r = 0; r < 8; r++) | |
676 | if (mask & (1L << r)) | |
677 | { | |
678 | ARMul_WriteWord (state, fpregsaddr + (ARMword) r * 16, | |
679 | buffer[upto + 1]); | |
680 | ARMul_WriteWord (state, fpregsaddr + (ARMword) r * 16 + 4, | |
681 | buffer[upto + 2]); | |
682 | ARMul_WriteWord (state, fpregsaddr + (ARMword) r * 16 + 8, | |
683 | buffer[upto + 3]); | |
684 | ARMul_WriteWord (state, fpregsaddr + (ARMword) r * 16 + 12, | |
685 | (buffer[upto] * 2 + 1) << 29); /* mark type */ | |
686 | upto += 4; | |
687 | } | |
688 | if (mask & (1L << r)) | |
689 | ARMul_WriteWord (state, fpregsaddr + 128, buffer[upto++]); /* fpsr */ | |
690 | return (RDIError_NoError); | |
c906108c SS |
691 | #endif /* NOFPE */ |
692 | } | |
693 | ||
dfcd3bfb JM |
694 | static void |
695 | deletebreaknode (BreakNode ** prevp) | |
696 | { | |
c906108c SS |
697 | BreakNode *p = *prevp; |
698 | *prevp = p->next; | |
dfcd3bfb JM |
699 | ARMul_WriteWord (state, p->address, p->inst); |
700 | free ((char *) p); | |
701 | BreaksSet--; | |
702 | state->CallDebug--; | |
c906108c SS |
703 | } |
704 | ||
dfcd3bfb JM |
705 | static int |
706 | removebreak (ARMword address, unsigned type) | |
707 | { | |
708 | BreakNode *p, **prevp = &BreakList; | |
709 | for (; (p = *prevp) != NULL; prevp = &p->next) | |
710 | if (p->address == address && p->type == type) | |
711 | { | |
712 | deletebreaknode (prevp); | |
713 | return TRUE; | |
714 | } | |
c906108c SS |
715 | return FALSE; |
716 | } | |
717 | ||
718 | /* This routine installs a breakpoint into the breakpoint table */ | |
719 | ||
dfcd3bfb JM |
720 | static BreakNode * |
721 | installbreak (ARMword address, unsigned type, ARMword bound) | |
722 | { | |
723 | BreakNode *p = (BreakNode *) malloc (sizeof (BreakNode)); | |
c906108c SS |
724 | p->next = BreakList; |
725 | BreakList = p; | |
726 | p->address = address; | |
727 | p->type = type; | |
728 | p->bound = bound; | |
dfcd3bfb JM |
729 | p->inst = ARMul_ReadWord (state, address); |
730 | ARMul_WriteWord (state, address, 0xee000000L); | |
c906108c SS |
731 | return p; |
732 | } | |
733 | ||
734 | /***************************************************************************\ | |
735 | * RDI_setbreak * | |
736 | \***************************************************************************/ | |
737 | ||
dfcd3bfb JM |
738 | static int |
739 | RDI_setbreak (ARMword address, unsigned type, ARMword bound, | |
740 | PointHandle * handle) | |
741 | { | |
742 | BreakNode *p; | |
743 | TracePrint ((state, "RDI_setbreak: address=%.8lx type=%d bound=%.8lx\n", | |
744 | address, type, bound)); | |
745 | ||
746 | removebreak (address, type); | |
747 | p = installbreak (address, type, bound); | |
748 | BreaksSet++; | |
749 | state->CallDebug++; | |
750 | *handle = (PointHandle) p; | |
751 | TracePrint ((state, " returns %.8lx\n", *handle)); | |
c906108c SS |
752 | return RDIError_NoError; |
753 | } | |
754 | ||
755 | /***************************************************************************\ | |
756 | * RDI_clearbreak * | |
757 | \***************************************************************************/ | |
758 | ||
dfcd3bfb JM |
759 | static int |
760 | RDI_clearbreak (PointHandle handle) | |
761 | { | |
762 | TracePrint ((state, "RDI_clearbreak: address=%.8lx\n", handle)); | |
763 | { | |
764 | BreakNode *p, **prevp = &BreakList; | |
c906108c | 765 | for (; (p = *prevp) != NULL; prevp = &p->next) |
dfcd3bfb JM |
766 | if (p == (BreakNode *) handle) |
767 | break; | |
768 | if (p == NULL) | |
769 | return RDIError_NoSuchPoint; | |
770 | deletebreaknode (prevp); | |
c906108c SS |
771 | return RDIError_NoError; |
772 | } | |
773 | } | |
774 | ||
775 | /***************************************************************************\ | |
776 | * Internal functions for breakpoint table manipulation * | |
777 | \***************************************************************************/ | |
778 | ||
dfcd3bfb JM |
779 | static void |
780 | deletewatchnode (WatchNode ** prevp) | |
781 | { | |
782 | WatchNode *p = *prevp; | |
783 | if (p->datatype & Watch_AnyRead) | |
784 | state->MemReadDebug--; | |
785 | if (p->datatype & Watch_AnyWrite) | |
786 | state->MemWriteDebug--; | |
c906108c | 787 | *prevp = p->next; |
dfcd3bfb | 788 | free ((char *) p); |
c906108c SS |
789 | } |
790 | ||
dfcd3bfb JM |
791 | int |
792 | removewatch (ARMword address, unsigned type) | |
793 | { | |
794 | WatchNode *p, **prevp = &WatchList; | |
795 | for (; (p = *prevp) != NULL; prevp = &p->next) | |
796 | if (p->address == address && p->type == type) | |
797 | { /* found a match */ | |
798 | deletewatchnode (prevp); | |
799 | return TRUE; | |
800 | } | |
801 | return FALSE; /* never found a match */ | |
c906108c SS |
802 | } |
803 | ||
dfcd3bfb JM |
804 | static WatchNode * |
805 | installwatch (ARMword address, unsigned type, unsigned datatype, | |
806 | ARMword bound) | |
807 | { | |
808 | WatchNode *p = (WatchNode *) malloc (sizeof (WatchNode)); | |
c906108c SS |
809 | p->next = WatchList; |
810 | WatchList = p; | |
811 | p->address = address; | |
812 | p->type = type; | |
813 | p->datatype = datatype; | |
814 | p->bound = bound; | |
815 | return p; | |
816 | } | |
817 | ||
818 | /***************************************************************************\ | |
819 | * RDI_setwatch * | |
820 | \***************************************************************************/ | |
821 | ||
dfcd3bfb JM |
822 | static int |
823 | RDI_setwatch (ARMword address, unsigned type, unsigned datatype, | |
824 | ARMword bound, PointHandle * handle) | |
825 | { | |
826 | WatchNode *p; | |
827 | TracePrint ( | |
828 | (state, | |
829 | "RDI_setwatch: address=%.8lx type=%d datatype=%d bound=%.8lx", | |
830 | address, type, datatype, bound)); | |
c906108c | 831 | |
dfcd3bfb JM |
832 | if (!state->CanWatch) |
833 | return RDIError_UnimplementedMessage; | |
c906108c | 834 | |
dfcd3bfb JM |
835 | removewatch (address, type); |
836 | p = installwatch (address, type, datatype, bound); | |
837 | if (datatype & Watch_AnyRead) | |
838 | state->MemReadDebug++; | |
839 | if (datatype & Watch_AnyWrite) | |
840 | state->MemWriteDebug++; | |
841 | *handle = (PointHandle) p; | |
842 | TracePrint ((state, " returns %.8lx\n", *handle)); | |
c906108c SS |
843 | return RDIError_NoError; |
844 | } | |
845 | ||
846 | /***************************************************************************\ | |
847 | * RDI_clearwatch * | |
848 | \***************************************************************************/ | |
849 | ||
dfcd3bfb JM |
850 | static int |
851 | RDI_clearwatch (PointHandle handle) | |
852 | { | |
853 | TracePrint ((state, "RDI_clearwatch: address=%.8lx\n", handle)); | |
854 | { | |
855 | WatchNode *p, **prevp = &WatchList; | |
c906108c | 856 | for (; (p = *prevp) != NULL; prevp = &p->next) |
dfcd3bfb JM |
857 | if (p == (WatchNode *) handle) |
858 | break; | |
859 | if (p == NULL) | |
860 | return RDIError_NoSuchPoint; | |
861 | deletewatchnode (prevp); | |
c906108c SS |
862 | return RDIError_NoError; |
863 | } | |
864 | } | |
865 | ||
866 | /***************************************************************************\ | |
867 | * RDI_execute * | |
868 | \***************************************************************************/ | |
869 | ||
dfcd3bfb JM |
870 | static int |
871 | RDI_execute (PointHandle * handle) | |
c906108c | 872 | { |
dfcd3bfb JM |
873 | TracePrint ((state, "RDI_execute\n")); |
874 | if (rdi_log & 4) | |
875 | { | |
876 | state->CallDebug++; | |
877 | state->Debug = TRUE; | |
878 | } | |
879 | state->EndCondition = RDIError_NoError; | |
c906108c SS |
880 | state->StopHandle = 0; |
881 | ||
dfcd3bfb | 882 | ARMul_DoProg (state); |
c906108c SS |
883 | |
884 | *handle = state->StopHandle; | |
dfcd3bfb JM |
885 | state->Reg[15] -= 8; /* undo the pipeline */ |
886 | if (rdi_log & 4) | |
887 | { | |
888 | state->CallDebug--; | |
889 | state->Debug = FALSE; | |
890 | } | |
891 | return (state->EndCondition); | |
c906108c SS |
892 | } |
893 | ||
894 | /***************************************************************************\ | |
895 | * RDI_step * | |
896 | \***************************************************************************/ | |
897 | ||
dfcd3bfb JM |
898 | static int |
899 | RDI_step (unsigned ninstr, PointHandle * handle) | |
c906108c SS |
900 | { |
901 | ||
dfcd3bfb JM |
902 | TracePrint ((state, "RDI_step\n")); |
903 | if (ninstr != 1) | |
904 | return RDIError_UnimplementedMessage; | |
905 | if (rdi_log & 4) | |
906 | { | |
907 | state->CallDebug++; | |
908 | state->Debug = TRUE; | |
909 | } | |
910 | state->EndCondition = RDIError_NoError; | |
c906108c | 911 | state->StopHandle = 0; |
dfcd3bfb | 912 | ARMul_DoInstr (state); |
c906108c | 913 | *handle = state->StopHandle; |
dfcd3bfb JM |
914 | state->Reg[15] -= 8; /* undo the pipeline */ |
915 | if (rdi_log & 4) | |
916 | { | |
917 | state->CallDebug--; | |
918 | state->Debug = FALSE; | |
919 | } | |
920 | return (state->EndCondition); | |
c906108c SS |
921 | } |
922 | ||
923 | /***************************************************************************\ | |
924 | * RDI_info * | |
925 | \***************************************************************************/ | |
926 | ||
dfcd3bfb JM |
927 | static int |
928 | RDI_info (unsigned type, ARMword * arg1, ARMword * arg2) | |
c906108c | 929 | { |
dfcd3bfb JM |
930 | switch (type) |
931 | { | |
932 | case RDIInfo_Target: | |
933 | TracePrint ((state, "RDI_Info_Target\n")); | |
934 | /* Emulator, speed 10**5 IPS */ | |
935 | *arg1 = 5 | HIGHEST_RDI_LEVEL << 5 | LOWEST_RDI_LEVEL << 8; | |
936 | *arg2 = 1298224434; | |
937 | return RDIError_NoError; | |
938 | ||
939 | case RDIInfo_Points: | |
940 | { | |
941 | ARMword n = RDIPointCapability_Comparison | RDIPointCapability_Range | | |
942 | RDIPointCapability_Mask | RDIPointCapability_Status; | |
943 | TracePrint ((state, "RDI_Info_Points\n")); | |
944 | if (state->CanWatch) | |
945 | n |= (Watch_AnyRead + Watch_AnyWrite) << 2; | |
946 | *arg1 = n; | |
947 | return RDIError_NoError; | |
948 | } | |
c906108c | 949 | |
dfcd3bfb JM |
950 | case RDIInfo_Step: |
951 | TracePrint ((state, "RDI_Info_Step\n")); | |
952 | *arg1 = RDIStep_Single; | |
953 | return RDIError_NoError; | |
954 | ||
955 | case RDIInfo_MMU: | |
956 | TracePrint ((state, "RDI_Info_MMU\n")); | |
957 | *arg1 = 1313820229; | |
958 | return RDIError_NoError; | |
959 | ||
960 | case RDISignal_Stop: | |
961 | TracePrint ((state, "RDISignal_Stop\n")); | |
962 | state->CallDebug++; | |
963 | state->EndCondition = RDIError_UserInterrupt; | |
964 | return RDIError_NoError; | |
965 | ||
966 | case RDIVector_Catch: | |
967 | TracePrint ((state, "RDIVector_Catch %.8lx\n", *arg1)); | |
968 | state->VectorCatch = (unsigned) *arg1; | |
969 | return RDIError_NoError; | |
970 | ||
971 | case RDISet_Cmdline: | |
972 | TracePrint ((state, "RDI_Set_Cmdline %s\n", (char *) arg1)); | |
973 | state->CommandLine = | |
974 | (char *) malloc ((unsigned) strlen ((char *) arg1) + 1); | |
975 | (void) strcpy (state->CommandLine, (char *) arg1); | |
976 | return RDIError_NoError; | |
977 | ||
978 | case RDICycles: | |
979 | TracePrint ((state, "RDI_Info_Cycles\n")); | |
980 | arg1[0] = 0; | |
981 | arg1[1] = state->NumInstrs; | |
982 | arg1[2] = 0; | |
983 | arg1[3] = state->NumScycles; | |
984 | arg1[4] = 0; | |
985 | arg1[5] = state->NumNcycles; | |
986 | arg1[6] = 0; | |
987 | arg1[7] = state->NumIcycles; | |
988 | arg1[8] = 0; | |
989 | arg1[9] = state->NumCcycles; | |
990 | arg1[10] = 0; | |
991 | arg1[11] = state->NumFcycles; | |
992 | return RDIError_NoError; | |
993 | ||
994 | case RDIErrorP: | |
995 | *arg1 = ARMul_OSLastErrorP (state); | |
996 | TracePrint ((state, "RDI_ErrorP returns %ld\n", *arg1)); | |
997 | return RDIError_NoError; | |
998 | ||
999 | case RDIInfo_DescribeCoPro: | |
1000 | { | |
1001 | int cpnum = *(int *) arg1; | |
1002 | struct Dbg_CoProDesc *cpd = (struct Dbg_CoProDesc *) arg2; | |
1003 | int i; | |
1004 | unsigned char const *map = state->CPRegWords[cpnum]; | |
1005 | if (map == NULL) | |
1006 | return RDIError_UnknownCoPro; | |
1007 | for (i = 0; i < cpd->entries; i++) | |
1008 | { | |
1009 | unsigned r, w = cpd->regdesc[i].nbytes / sizeof (ARMword); | |
1010 | for (r = cpd->regdesc[i].rmin; r <= cpd->regdesc[i].rmax; r++) | |
1011 | if (map[r] != w) | |
1012 | return RDIError_BadCoProState; | |
1013 | } | |
1014 | return RDIError_NoError; | |
1015 | } | |
c906108c | 1016 | |
dfcd3bfb JM |
1017 | case RDIInfo_RequestCoProDesc: |
1018 | { | |
1019 | int cpnum = *(int *) arg1; | |
1020 | struct Dbg_CoProDesc *cpd = (struct Dbg_CoProDesc *) arg2; | |
1021 | int i = -1, lastw = -1, r; | |
1022 | unsigned char const *map; | |
1023 | if ((unsigned) cpnum >= 16) | |
1024 | return RDIError_UnknownCoPro; | |
1025 | map = state->CPRegWords[cpnum]; | |
1026 | if (map == NULL) | |
1027 | return RDIError_UnknownCoPro; | |
1028 | for (r = 0; r < map[-1]; r++) | |
1029 | { | |
1030 | int words = map[r]; | |
1031 | if (words == lastw) | |
1032 | cpd->regdesc[i].rmax = r; | |
1033 | else | |
1034 | { | |
1035 | if (++i >= cpd->entries) | |
1036 | return RDIError_BufferFull; | |
1037 | cpd->regdesc[i].rmax = cpd->regdesc[i].rmin = r; | |
1038 | cpd->regdesc[i].nbytes = words * sizeof (ARMword); | |
1039 | cpd->regdesc[i].access = | |
1040 | Dbg_Access_Readable + Dbg_Access_Writable; | |
1041 | } | |
1042 | } | |
1043 | cpd->entries = i + 1; | |
1044 | return RDIError_NoError; | |
1045 | } | |
c906108c | 1046 | |
dfcd3bfb JM |
1047 | case RDIInfo_Log: |
1048 | *arg1 = (ARMword) rdi_log; | |
1049 | return RDIError_NoError; | |
1050 | ||
1051 | case RDIInfo_SetLog: | |
1052 | rdi_log = (int) *arg1; | |
1053 | return RDIError_NoError; | |
1054 | ||
1055 | case RDIInfo_CoPro: | |
1056 | return RDIError_NoError; | |
1057 | ||
1058 | case RDIPointStatus_Watch: | |
1059 | { | |
1060 | WatchNode *p, *handle = (WatchNode *) * arg1; | |
1061 | for (p = WatchList; p != NULL; p = p->next) | |
1062 | if (p == handle) | |
1063 | { | |
1064 | *arg1 = -1; | |
1065 | *arg2 = 1; | |
1066 | return RDIError_NoError; | |
1067 | } | |
1068 | return RDIError_NoSuchPoint; | |
c906108c | 1069 | } |
c906108c | 1070 | |
dfcd3bfb JM |
1071 | case RDIPointStatus_Break: |
1072 | { | |
1073 | BreakNode *p, *handle = (BreakNode *) * arg1; | |
1074 | for (p = BreakList; p != NULL; p = p->next) | |
1075 | if (p == handle) | |
1076 | { | |
1077 | *arg1 = -1; | |
1078 | *arg2 = 1; | |
1079 | return RDIError_NoError; | |
1080 | } | |
1081 | return RDIError_NoSuchPoint; | |
1082 | } | |
c906108c | 1083 | |
dfcd3bfb JM |
1084 | case RDISet_RDILevel: |
1085 | if (*arg1 < LOWEST_RDI_LEVEL || *arg1 > HIGHEST_RDI_LEVEL) | |
1086 | return RDIError_IncompatibleRDILevels; | |
1087 | MYrdi_level = *arg1; | |
1088 | return RDIError_NoError; | |
c906108c | 1089 | |
dfcd3bfb JM |
1090 | default: |
1091 | return RDIError_UnimplementedMessage; | |
c906108c | 1092 | |
c906108c | 1093 | } |
c906108c SS |
1094 | } |
1095 | ||
1096 | /***************************************************************************\ | |
1097 | * The emulator calls this routine at the beginning of every cycle when the * | |
1098 | * CallDebug flag is set. The second parameter passed is the address of the * | |
1099 | * currently executing instruction (i.e Program Counter - 8), the third * | |
1100 | * parameter is the instruction being executed. * | |
1101 | \***************************************************************************/ | |
1102 | ||
dfcd3bfb JM |
1103 | ARMword |
1104 | ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr) | |
c906108c SS |
1105 | { |
1106 | ||
dfcd3bfb JM |
1107 | if (state->EndCondition == RDIError_UserInterrupt) |
1108 | { | |
1109 | TracePrint ((state, "User interrupt at %.8lx\n", pc)); | |
1110 | state->CallDebug--; | |
c906108c | 1111 | state->Emulate = STOP; |
c906108c | 1112 | } |
dfcd3bfb JM |
1113 | else |
1114 | { | |
1115 | BreakNode *p = BreakList; | |
1116 | for (; p != NULL; p = p->next) | |
1117 | { | |
1118 | switch (p->type) | |
1119 | { | |
1120 | case RDIPoint_EQ: | |
1121 | if (pc == p->address) | |
1122 | break; | |
1123 | continue; | |
1124 | case RDIPoint_GT: | |
1125 | if (pc > p->address) | |
1126 | break; | |
1127 | continue; | |
1128 | case RDIPoint_GE: | |
1129 | if (pc >= p->address) | |
1130 | break; | |
1131 | continue; | |
1132 | case RDIPoint_LT: | |
1133 | if (pc < p->address) | |
1134 | break; | |
1135 | continue; | |
1136 | case RDIPoint_LE: | |
1137 | if (pc <= p->address) | |
1138 | break; | |
1139 | continue; | |
1140 | case RDIPoint_IN: | |
1141 | if (p->address <= pc && pc < p->address + p->bound) | |
1142 | break; | |
1143 | continue; | |
1144 | case RDIPoint_OUT: | |
1145 | if (p->address > pc || pc >= p->address + p->bound) | |
1146 | break; | |
1147 | continue; | |
1148 | case RDIPoint_MASK: | |
1149 | if ((pc & p->bound) == p->address) | |
1150 | break; | |
1151 | continue; | |
1152 | } | |
1153 | /* found a match */ | |
1154 | TracePrint ((state, "Breakpoint reached at %.8lx\n", pc)); | |
1155 | state->EndCondition = RDIError_BreakpointReached; | |
1156 | state->Emulate = STOP; | |
1157 | state->StopHandle = (ARMword) p; | |
1158 | break; | |
1159 | } | |
1160 | } | |
c906108c SS |
1161 | return instr; |
1162 | } | |
1163 | ||
dfcd3bfb JM |
1164 | void |
1165 | ARMul_CheckWatch (ARMul_State * state, ARMword addr, int access) | |
1166 | { | |
1167 | WatchNode *p; | |
c906108c | 1168 | for (p = WatchList; p != NULL; p = p->next) |
dfcd3bfb JM |
1169 | if (p->datatype & access) |
1170 | { | |
1171 | switch (p->type) | |
1172 | { | |
1173 | case RDIPoint_EQ: | |
1174 | if (addr == p->address) | |
1175 | break; | |
1176 | continue; | |
1177 | case RDIPoint_GT: | |
1178 | if (addr > p->address) | |
1179 | break; | |
1180 | continue; | |
1181 | case RDIPoint_GE: | |
1182 | if (addr >= p->address) | |
1183 | break; | |
1184 | continue; | |
1185 | case RDIPoint_LT: | |
1186 | if (addr < p->address) | |
1187 | break; | |
1188 | continue; | |
1189 | case RDIPoint_LE: | |
1190 | if (addr <= p->address) | |
1191 | break; | |
1192 | continue; | |
1193 | case RDIPoint_IN: | |
1194 | if (p->address <= addr && addr < p->address + p->bound) | |
1195 | break; | |
1196 | continue; | |
1197 | case RDIPoint_OUT: | |
1198 | if (p->address > addr || addr >= p->address + p->bound) | |
1199 | break; | |
1200 | continue; | |
1201 | case RDIPoint_MASK: | |
1202 | if ((addr & p->bound) == p->address) | |
1203 | break; | |
1204 | continue; | |
1205 | } | |
1206 | /* found a match */ | |
1207 | TracePrint ((state, "Watchpoint at %.8lx accessed\n", addr)); | |
1208 | state->EndCondition = RDIError_WatchpointAccessed; | |
1209 | state->Emulate = STOP; | |
1210 | state->StopHandle = (ARMword) p; | |
1211 | return; | |
c906108c | 1212 | } |
c906108c SS |
1213 | } |
1214 | ||
dfcd3bfb JM |
1215 | static RDI_NameList const * |
1216 | RDI_cpunames () | |
1217 | { | |
1218 | return (RDI_NameList const *) &processorconfig.count; | |
c906108c SS |
1219 | } |
1220 | ||
1221 | const struct RDIProcVec armul_rdi = { | |
dfcd3bfb JM |
1222 | "ARMUL", |
1223 | RDI_open, | |
1224 | RDI_close, | |
1225 | RDI_read, | |
1226 | RDI_write, | |
1227 | RDI_CPUread, | |
1228 | RDI_CPUwrite, | |
1229 | RDI_CPread, | |
1230 | RDI_CPwrite, | |
1231 | RDI_setbreak, | |
1232 | RDI_clearbreak, | |
1233 | RDI_setwatch, | |
1234 | RDI_clearwatch, | |
1235 | RDI_execute, | |
1236 | RDI_step, | |
1237 | RDI_info, | |
1238 | ||
1239 | 0, /*pointinq */ | |
1240 | 0, /*addconfig */ | |
1241 | 0, /*loadconfigdata */ | |
1242 | 0, /*selectconfig */ | |
1243 | 0, /*drivernames */ | |
1244 | ||
1245 | RDI_cpunames | |
c906108c | 1246 | }; |