Commit | Line | Data |
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c906108c | 1 | /* run front end support for arm |
8acc9f48 | 2 | Copyright (C) 1995-2013 Free Software Foundation, Inc. |
c906108c | 3 | |
86c735a5 | 4 | This file is part of ARM SIM. |
c906108c | 5 | |
4744ac1b JB |
6 | This program is free software; you can redistribute it and/or modify |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3 of the License, or | |
9 | (at your option) any later version. | |
c906108c | 10 | |
4744ac1b JB |
11 | This program is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
c906108c | 15 | |
4744ac1b JB |
16 | You should have received a copy of the GNU General Public License |
17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
c906108c | 18 | |
86c735a5 NC |
19 | /* This file provides the interface between the simulator and |
20 | run.c and gdb (when the simulator is linked with gdb). | |
c906108c SS |
21 | All simulator interaction should go through this file. */ |
22 | ||
a6ff997c | 23 | #include "config.h" |
c906108c SS |
24 | #include <stdio.h> |
25 | #include <stdarg.h> | |
6d358e86 | 26 | #include <string.h> |
c906108c SS |
27 | #include <bfd.h> |
28 | #include <signal.h> | |
3c25f8c7 AC |
29 | #include "gdb/callback.h" |
30 | #include "gdb/remote-sim.h" | |
c906108c SS |
31 | #include "armdefs.h" |
32 | #include "armemu.h" | |
33 | #include "dbg_rdi.h" | |
6d358e86 | 34 | #include "ansidecl.h" |
86c735a5 | 35 | #include "sim-utils.h" |
de4112fa | 36 | #include "run-sim.h" |
26216b98 | 37 | #include "gdb/sim-arm.h" |
aba6488e | 38 | #include "gdb/signals.h" |
9256caa6 | 39 | #include "libiberty.h" |
74ec5579 | 40 | |
c906108c SS |
41 | host_callback *sim_callback; |
42 | ||
43 | static struct ARMul_State *state; | |
44 | ||
45 | /* Who is using the simulator. */ | |
46 | static SIM_OPEN_KIND sim_kind; | |
47 | ||
48 | /* argv[0] */ | |
49 | static char *myname; | |
50 | ||
51 | /* Memory size in bytes. */ | |
058f270d | 52 | static int mem_size = (1 << 21); |
c906108c SS |
53 | |
54 | /* Non-zero to display start up banner, and maybe other things. */ | |
55 | static int verbosity; | |
56 | ||
57 | /* Non-zero to set big endian mode. */ | |
58 | static int big_endian; | |
59 | ||
7a292a7a SS |
60 | int stop_simulator; |
61 | ||
f603c8fe NC |
62 | /* Cirrus DSP registers. |
63 | ||
64 | We need to define these registers outside of maverick.c because | |
65 | maverick.c might not be linked in unless --target=arm9e-* in which | |
66 | case wrapper.c will not compile because it tries to access Cirrus | |
67 | registers. This should all go away once we get the Cirrus and ARM | |
68 | Coprocessor to coexist in armcopro.c-- aldyh. */ | |
69 | ||
70 | struct maverick_regs | |
71 | { | |
72 | union | |
73 | { | |
74 | int i; | |
75 | float f; | |
76 | } upper; | |
77 | ||
78 | union | |
79 | { | |
80 | int i; | |
81 | float f; | |
82 | } lower; | |
83 | }; | |
84 | ||
85 | union maverick_acc_regs | |
86 | { | |
87 | long double ld; /* Acc registers are 72-bits. */ | |
88 | }; | |
89 | ||
90 | struct maverick_regs DSPregs[16]; | |
91 | union maverick_acc_regs DSPacc[4]; | |
92 | ARMword DSPsc; | |
93 | ||
dfcd3bfb | 94 | static void |
c906108c SS |
95 | init () |
96 | { | |
97 | static int done; | |
98 | ||
99 | if (!done) | |
100 | { | |
dfcd3bfb | 101 | ARMul_EmulateInit (); |
c906108c SS |
102 | state = ARMul_NewState (); |
103 | state->bigendSig = (big_endian ? HIGH : LOW); | |
dfcd3bfb JM |
104 | ARMul_MemoryInit (state, mem_size); |
105 | ARMul_OSInit (state); | |
c906108c SS |
106 | state->verbose = verbosity; |
107 | done = 1; | |
108 | } | |
109 | } | |
110 | ||
111 | /* Set verbosity level of simulator. | |
112 | This is not intended to produce detailed tracing or debugging information. | |
113 | Just summaries. */ | |
114 | /* FIXME: common/run.c doesn't do this yet. */ | |
115 | ||
116 | void | |
117 | sim_set_verbose (v) | |
118 | int v; | |
119 | { | |
120 | verbosity = v; | |
121 | } | |
122 | ||
123 | /* Set the memory size to SIZE bytes. | |
dfcd3bfb | 124 | Must be called before initializing simulator. */ |
c906108c SS |
125 | /* FIXME: Rename to sim_set_mem_size. */ |
126 | ||
dfcd3bfb | 127 | void |
c906108c SS |
128 | sim_size (size) |
129 | int size; | |
130 | { | |
131 | mem_size = size; | |
132 | } | |
133 | ||
dfcd3bfb | 134 | void |
86c735a5 NC |
135 | ARMul_ConsolePrint VPARAMS ((ARMul_State * state, |
136 | const char * format, | |
137 | ...)) | |
c906108c SS |
138 | { |
139 | va_list ap; | |
140 | ||
141 | if (state->verbose) | |
142 | { | |
143 | va_start (ap, format); | |
144 | vprintf (format, ap); | |
145 | va_end (ap); | |
146 | } | |
147 | } | |
148 | ||
6d358e86 | 149 | ARMword |
86c735a5 NC |
150 | ARMul_Debug (state, pc, instr) |
151 | ARMul_State * state ATTRIBUTE_UNUSED; | |
152 | ARMword pc ATTRIBUTE_UNUSED; | |
153 | ARMword instr ATTRIBUTE_UNUSED; | |
c906108c | 154 | { |
6d358e86 | 155 | return 0; |
c906108c SS |
156 | } |
157 | ||
158 | int | |
159 | sim_write (sd, addr, buffer, size) | |
6d358e86 | 160 | SIM_DESC sd ATTRIBUTE_UNUSED; |
c906108c | 161 | SIM_ADDR addr; |
5558e7e6 | 162 | const unsigned char * buffer; |
c906108c SS |
163 | int size; |
164 | { | |
165 | int i; | |
3943c96b | 166 | |
c906108c | 167 | init (); |
3943c96b | 168 | |
c906108c | 169 | for (i = 0; i < size; i++) |
917bca4f | 170 | ARMul_SafeWriteByte (state, addr + i, buffer[i]); |
3943c96b | 171 | |
c906108c SS |
172 | return size; |
173 | } | |
174 | ||
175 | int | |
176 | sim_read (sd, addr, buffer, size) | |
6d358e86 | 177 | SIM_DESC sd ATTRIBUTE_UNUSED; |
c906108c | 178 | SIM_ADDR addr; |
86c735a5 | 179 | unsigned char * buffer; |
c906108c SS |
180 | int size; |
181 | { | |
182 | int i; | |
917bca4f | 183 | |
c906108c | 184 | init (); |
86c735a5 | 185 | |
c906108c | 186 | for (i = 0; i < size; i++) |
917bca4f NC |
187 | buffer[i] = ARMul_SafeReadByte (state, addr + i); |
188 | ||
c906108c SS |
189 | return size; |
190 | } | |
191 | ||
192 | int | |
193 | sim_trace (sd) | |
6d358e86 | 194 | SIM_DESC sd ATTRIBUTE_UNUSED; |
dfcd3bfb | 195 | { |
86c735a5 NC |
196 | (*sim_callback->printf_filtered) |
197 | (sim_callback, | |
198 | "This simulator does not support tracing\n"); | |
c906108c SS |
199 | return 1; |
200 | } | |
201 | ||
202 | int | |
203 | sim_stop (sd) | |
6d358e86 | 204 | SIM_DESC sd ATTRIBUTE_UNUSED; |
c906108c | 205 | { |
7a292a7a SS |
206 | state->Emulate = STOP; |
207 | stop_simulator = 1; | |
208 | return 1; | |
c906108c SS |
209 | } |
210 | ||
211 | void | |
212 | sim_resume (sd, step, siggnal) | |
6d358e86 NC |
213 | SIM_DESC sd ATTRIBUTE_UNUSED; |
214 | int step; | |
215 | int siggnal ATTRIBUTE_UNUSED; | |
c906108c SS |
216 | { |
217 | state->EndCondition = 0; | |
7a292a7a | 218 | stop_simulator = 0; |
c906108c SS |
219 | |
220 | if (step) | |
221 | { | |
222 | state->Reg[15] = ARMul_DoInstr (state); | |
223 | if (state->EndCondition == 0) | |
224 | state->EndCondition = RDIError_BreakpointReached; | |
225 | } | |
226 | else | |
227 | { | |
dfcd3bfb | 228 | state->NextInstr = RESUME; /* treat as PC change */ |
c906108c SS |
229 | state->Reg[15] = ARMul_DoProg (state); |
230 | } | |
231 | ||
232 | FLUSHPIPE; | |
233 | } | |
234 | ||
235 | SIM_RC | |
236 | sim_create_inferior (sd, abfd, argv, env) | |
6d358e86 | 237 | SIM_DESC sd ATTRIBUTE_UNUSED; |
6b4a8935 | 238 | struct bfd * abfd; |
86c735a5 NC |
239 | char ** argv; |
240 | char ** env; | |
c906108c | 241 | { |
dfcd3bfb | 242 | int argvlen = 0; |
1e6b544a | 243 | int mach; |
c906108c SS |
244 | char **arg; |
245 | ||
246 | if (abfd != NULL) | |
247 | ARMul_SetPC (state, bfd_get_start_address (abfd)); | |
248 | else | |
dfcd3bfb | 249 | ARMul_SetPC (state, 0); /* ??? */ |
c906108c | 250 | |
1e6b544a AO |
251 | mach = bfd_get_mach (abfd); |
252 | ||
3943c96b NC |
253 | switch (mach) |
254 | { | |
255 | default: | |
86c735a5 NC |
256 | (*sim_callback->printf_filtered) |
257 | (sim_callback, | |
10b57fcb NC |
258 | "Unknown machine type '%d'; please update sim_create_inferior.\n", |
259 | mach); | |
3943c96b NC |
260 | /* fall through */ |
261 | ||
f1129fb8 | 262 | case 0: |
3943c96b | 263 | /* We wouldn't set the machine type with earlier toolchains, so we |
f1129fb8 NC |
264 | explicitly select a processor capable of supporting all ARMs in |
265 | 32bit mode. */ | |
0f026fd0 NC |
266 | /* We choose the XScale rather than the iWMMXt, because the iWMMXt |
267 | removes the FPE emulator, since it conflicts with its coprocessors. | |
268 | For the most generic ARM support, we want the FPE emulator in place. */ | |
272fcdcd | 269 | case bfd_mach_arm_XScale: |
8207e0f2 | 270 | ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_v6_Prop); |
272fcdcd NC |
271 | break; |
272 | ||
b0f05691 | 273 | case bfd_mach_arm_iWMMXt2: |
0f026fd0 NC |
274 | case bfd_mach_arm_iWMMXt: |
275 | { | |
276 | extern int SWI_vector_installed; | |
277 | ARMword i; | |
278 | ||
279 | if (! SWI_vector_installed) | |
280 | { | |
281 | /* Intialise the hardware vectors to zero. */ | |
282 | if (! SWI_vector_installed) | |
283 | for (i = ARMul_ResetV; i <= ARMFIQV; i += 4) | |
284 | ARMul_WriteWord (state, i, 0); | |
285 | ||
286 | /* ARM_WriteWord will have detected the write to the SWI vector, | |
287 | but we want SWI_vector_installed to remain at 0 so that thumb | |
288 | mode breakpoints will work. */ | |
289 | SWI_vector_installed = 0; | |
290 | } | |
291 | } | |
292 | ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop); | |
293 | break; | |
294 | ||
f603c8fe NC |
295 | case bfd_mach_arm_ep9312: |
296 | ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop); | |
297 | break; | |
298 | ||
f1129fb8 | 299 | case bfd_mach_arm_5: |
c17aa318 NC |
300 | if (bfd_family_coff (abfd)) |
301 | { | |
302 | /* This is a special case in order to support COFF based ARM toolchains. | |
303 | The COFF header does not have enough room to store all the different | |
304 | kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default | |
305 | to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5 | |
306 | machine type here, we assume it could be any of the above architectures | |
307 | and so select the most feature-full. */ | |
308 | ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop); | |
309 | break; | |
310 | } | |
311 | /* Otherwise drop through. */ | |
25180f8a | 312 | |
f1129fb8 NC |
313 | case bfd_mach_arm_5T: |
314 | ARMul_SelectProcessor (state, ARM_v5_Prop); | |
315 | break; | |
3943c96b | 316 | |
f1129fb8 NC |
317 | case bfd_mach_arm_5TE: |
318 | ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop); | |
319 | break; | |
320 | ||
f1129fb8 NC |
321 | case bfd_mach_arm_4: |
322 | case bfd_mach_arm_4T: | |
323 | ARMul_SelectProcessor (state, ARM_v4_Prop); | |
324 | break; | |
325 | ||
326 | case bfd_mach_arm_3: | |
327 | case bfd_mach_arm_3M: | |
3943c96b NC |
328 | ARMul_SelectProcessor (state, ARM_Lock_Prop); |
329 | break; | |
330 | ||
f1129fb8 NC |
331 | case bfd_mach_arm_2: |
332 | case bfd_mach_arm_2a: | |
3943c96b NC |
333 | ARMul_SelectProcessor (state, ARM_Fix26_Prop); |
334 | break; | |
335 | } | |
336 | ||
5f7d0a33 NC |
337 | if ( mach != bfd_mach_arm_3 |
338 | && mach != bfd_mach_arm_3M | |
339 | && mach != bfd_mach_arm_2 | |
340 | && mach != bfd_mach_arm_2a) | |
f1129fb8 NC |
341 | { |
342 | /* Reset mode to ARM. A gdb user may rerun a program that had entered | |
343 | THUMB mode from the start and cause the ARM-mode startup code to be | |
5f7d0a33 NC |
344 | executed in THUMB mode. */ |
345 | ARMul_SetCPSR (state, SVC32MODE); | |
f1129fb8 NC |
346 | } |
347 | ||
c906108c SS |
348 | if (argv != NULL) |
349 | { | |
5f7d0a33 NC |
350 | /* Set up the command line by laboriously stringing together |
351 | the environment carefully picked apart by our caller. */ | |
352 | ||
353 | /* Free any old stuff. */ | |
c906108c SS |
354 | if (state->CommandLine != NULL) |
355 | { | |
dfcd3bfb | 356 | free (state->CommandLine); |
c906108c SS |
357 | state->CommandLine = NULL; |
358 | } | |
dfcd3bfb | 359 | |
5f7d0a33 | 360 | /* See how much we need. */ |
c906108c | 361 | for (arg = argv; *arg != NULL; arg++) |
dfcd3bfb JM |
362 | argvlen += strlen (*arg) + 1; |
363 | ||
5f7d0a33 | 364 | /* Allocate it. */ |
dfcd3bfb | 365 | state->CommandLine = malloc (argvlen + 1); |
c906108c SS |
366 | if (state->CommandLine != NULL) |
367 | { | |
368 | arg = argv; | |
dfcd3bfb | 369 | state->CommandLine[0] = '\0'; |
5f7d0a33 | 370 | |
c906108c SS |
371 | for (arg = argv; *arg != NULL; arg++) |
372 | { | |
dfcd3bfb JM |
373 | strcat (state->CommandLine, *arg); |
374 | strcat (state->CommandLine, " "); | |
c906108c SS |
375 | } |
376 | } | |
377 | } | |
378 | ||
379 | if (env != NULL) | |
380 | { | |
5f7d0a33 | 381 | /* Now see if there's a MEMSIZE spec in the environment. */ |
c906108c SS |
382 | while (*env) |
383 | { | |
dfcd3bfb | 384 | if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0) |
c906108c | 385 | { |
c906108c | 386 | char *end_of_num; |
dfcd3bfb | 387 | |
5f7d0a33 | 388 | /* Set up memory limit. */ |
dfcd3bfb JM |
389 | state->MemSize = |
390 | strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0); | |
c906108c SS |
391 | } |
392 | env++; | |
393 | } | |
394 | } | |
395 | ||
396 | return SIM_RC_OK; | |
397 | } | |
398 | ||
399 | void | |
400 | sim_info (sd, verbose) | |
6d358e86 NC |
401 | SIM_DESC sd ATTRIBUTE_UNUSED; |
402 | int verbose ATTRIBUTE_UNUSED; | |
c906108c SS |
403 | { |
404 | } | |
405 | ||
dfcd3bfb | 406 | static int |
c906108c SS |
407 | frommem (state, memory) |
408 | struct ARMul_State *state; | |
409 | unsigned char *memory; | |
410 | { | |
411 | if (state->bigendSig == HIGH) | |
86c735a5 NC |
412 | return (memory[0] << 24) | (memory[1] << 16) |
413 | | (memory[2] << 8) | (memory[3] << 0); | |
c906108c | 414 | else |
86c735a5 NC |
415 | return (memory[3] << 24) | (memory[2] << 16) |
416 | | (memory[1] << 8) | (memory[0] << 0); | |
c906108c SS |
417 | } |
418 | ||
c906108c | 419 | static void |
dfcd3bfb | 420 | tomem (state, memory, val) |
c906108c SS |
421 | struct ARMul_State *state; |
422 | unsigned char *memory; | |
423 | int val; | |
424 | { | |
425 | if (state->bigendSig == HIGH) | |
426 | { | |
427 | memory[0] = val >> 24; | |
428 | memory[1] = val >> 16; | |
429 | memory[2] = val >> 8; | |
430 | memory[3] = val >> 0; | |
431 | } | |
432 | else | |
433 | { | |
434 | memory[3] = val >> 24; | |
435 | memory[2] = val >> 16; | |
436 | memory[1] = val >> 8; | |
437 | memory[0] = val >> 0; | |
438 | } | |
439 | } | |
440 | ||
441 | int | |
442 | sim_store_register (sd, rn, memory, length) | |
6d358e86 | 443 | SIM_DESC sd ATTRIBUTE_UNUSED; |
c906108c SS |
444 | int rn; |
445 | unsigned char *memory; | |
9256caa6 | 446 | int length; |
c906108c SS |
447 | { |
448 | init (); | |
f1129fb8 | 449 | |
26216b98 | 450 | switch ((enum sim_arm_regs) rn) |
3463c3fb | 451 | { |
26216b98 AC |
452 | case SIM_ARM_R0_REGNUM: |
453 | case SIM_ARM_R1_REGNUM: | |
454 | case SIM_ARM_R2_REGNUM: | |
455 | case SIM_ARM_R3_REGNUM: | |
456 | case SIM_ARM_R4_REGNUM: | |
457 | case SIM_ARM_R5_REGNUM: | |
458 | case SIM_ARM_R6_REGNUM: | |
459 | case SIM_ARM_R7_REGNUM: | |
460 | case SIM_ARM_R8_REGNUM: | |
461 | case SIM_ARM_R9_REGNUM: | |
462 | case SIM_ARM_R10_REGNUM: | |
463 | case SIM_ARM_R11_REGNUM: | |
464 | case SIM_ARM_R12_REGNUM: | |
465 | case SIM_ARM_R13_REGNUM: | |
466 | case SIM_ARM_R14_REGNUM: | |
467 | case SIM_ARM_R15_REGNUM: /* PC */ | |
468 | case SIM_ARM_FP0_REGNUM: | |
469 | case SIM_ARM_FP1_REGNUM: | |
470 | case SIM_ARM_FP2_REGNUM: | |
471 | case SIM_ARM_FP3_REGNUM: | |
472 | case SIM_ARM_FP4_REGNUM: | |
473 | case SIM_ARM_FP5_REGNUM: | |
474 | case SIM_ARM_FP6_REGNUM: | |
475 | case SIM_ARM_FP7_REGNUM: | |
476 | case SIM_ARM_FPS_REGNUM: | |
477 | ARMul_SetReg (state, state->Mode, rn, frommem (state, memory)); | |
478 | break; | |
479 | ||
480 | case SIM_ARM_PS_REGNUM: | |
3463c3fb | 481 | state->Cpsr = frommem (state, memory); |
10b57fcb | 482 | ARMul_CPSRAltered (state); |
26216b98 AC |
483 | break; |
484 | ||
f603c8fe NC |
485 | case SIM_ARM_MAVERIC_COP0R0_REGNUM: |
486 | case SIM_ARM_MAVERIC_COP0R1_REGNUM: | |
487 | case SIM_ARM_MAVERIC_COP0R2_REGNUM: | |
488 | case SIM_ARM_MAVERIC_COP0R3_REGNUM: | |
489 | case SIM_ARM_MAVERIC_COP0R4_REGNUM: | |
490 | case SIM_ARM_MAVERIC_COP0R5_REGNUM: | |
491 | case SIM_ARM_MAVERIC_COP0R6_REGNUM: | |
492 | case SIM_ARM_MAVERIC_COP0R7_REGNUM: | |
493 | case SIM_ARM_MAVERIC_COP0R8_REGNUM: | |
494 | case SIM_ARM_MAVERIC_COP0R9_REGNUM: | |
495 | case SIM_ARM_MAVERIC_COP0R10_REGNUM: | |
496 | case SIM_ARM_MAVERIC_COP0R11_REGNUM: | |
497 | case SIM_ARM_MAVERIC_COP0R12_REGNUM: | |
498 | case SIM_ARM_MAVERIC_COP0R13_REGNUM: | |
499 | case SIM_ARM_MAVERIC_COP0R14_REGNUM: | |
500 | case SIM_ARM_MAVERIC_COP0R15_REGNUM: | |
501 | memcpy (& DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM], | |
502 | memory, sizeof (struct maverick_regs)); | |
503 | return sizeof (struct maverick_regs); | |
504 | ||
505 | case SIM_ARM_MAVERIC_DSPSC_REGNUM: | |
506 | memcpy (&DSPsc, memory, sizeof DSPsc); | |
507 | return sizeof DSPsc; | |
508 | ||
0f026fd0 NC |
509 | case SIM_ARM_IWMMXT_COP0R0_REGNUM: |
510 | case SIM_ARM_IWMMXT_COP0R1_REGNUM: | |
511 | case SIM_ARM_IWMMXT_COP0R2_REGNUM: | |
512 | case SIM_ARM_IWMMXT_COP0R3_REGNUM: | |
513 | case SIM_ARM_IWMMXT_COP0R4_REGNUM: | |
514 | case SIM_ARM_IWMMXT_COP0R5_REGNUM: | |
515 | case SIM_ARM_IWMMXT_COP0R6_REGNUM: | |
516 | case SIM_ARM_IWMMXT_COP0R7_REGNUM: | |
517 | case SIM_ARM_IWMMXT_COP0R8_REGNUM: | |
518 | case SIM_ARM_IWMMXT_COP0R9_REGNUM: | |
519 | case SIM_ARM_IWMMXT_COP0R10_REGNUM: | |
520 | case SIM_ARM_IWMMXT_COP0R11_REGNUM: | |
521 | case SIM_ARM_IWMMXT_COP0R12_REGNUM: | |
522 | case SIM_ARM_IWMMXT_COP0R13_REGNUM: | |
523 | case SIM_ARM_IWMMXT_COP0R14_REGNUM: | |
524 | case SIM_ARM_IWMMXT_COP0R15_REGNUM: | |
525 | case SIM_ARM_IWMMXT_COP1R0_REGNUM: | |
526 | case SIM_ARM_IWMMXT_COP1R1_REGNUM: | |
527 | case SIM_ARM_IWMMXT_COP1R2_REGNUM: | |
528 | case SIM_ARM_IWMMXT_COP1R3_REGNUM: | |
529 | case SIM_ARM_IWMMXT_COP1R4_REGNUM: | |
530 | case SIM_ARM_IWMMXT_COP1R5_REGNUM: | |
531 | case SIM_ARM_IWMMXT_COP1R6_REGNUM: | |
532 | case SIM_ARM_IWMMXT_COP1R7_REGNUM: | |
533 | case SIM_ARM_IWMMXT_COP1R8_REGNUM: | |
534 | case SIM_ARM_IWMMXT_COP1R9_REGNUM: | |
535 | case SIM_ARM_IWMMXT_COP1R10_REGNUM: | |
536 | case SIM_ARM_IWMMXT_COP1R11_REGNUM: | |
537 | case SIM_ARM_IWMMXT_COP1R12_REGNUM: | |
538 | case SIM_ARM_IWMMXT_COP1R13_REGNUM: | |
539 | case SIM_ARM_IWMMXT_COP1R14_REGNUM: | |
540 | case SIM_ARM_IWMMXT_COP1R15_REGNUM: | |
541 | return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory); | |
3a3d6f65 | 542 | |
26216b98 AC |
543 | default: |
544 | return 0; | |
3463c3fb | 545 | } |
26216b98 | 546 | |
9256caa6 | 547 | return length; |
c906108c SS |
548 | } |
549 | ||
550 | int | |
551 | sim_fetch_register (sd, rn, memory, length) | |
6d358e86 | 552 | SIM_DESC sd ATTRIBUTE_UNUSED; |
c906108c SS |
553 | int rn; |
554 | unsigned char *memory; | |
9256caa6 | 555 | int length; |
c906108c SS |
556 | { |
557 | ARMword regval; | |
9256caa6 | 558 | int len = length; |
c906108c SS |
559 | |
560 | init (); | |
f1129fb8 | 561 | |
26216b98 AC |
562 | switch ((enum sim_arm_regs) rn) |
563 | { | |
564 | case SIM_ARM_R0_REGNUM: | |
565 | case SIM_ARM_R1_REGNUM: | |
566 | case SIM_ARM_R2_REGNUM: | |
567 | case SIM_ARM_R3_REGNUM: | |
568 | case SIM_ARM_R4_REGNUM: | |
569 | case SIM_ARM_R5_REGNUM: | |
570 | case SIM_ARM_R6_REGNUM: | |
571 | case SIM_ARM_R7_REGNUM: | |
572 | case SIM_ARM_R8_REGNUM: | |
573 | case SIM_ARM_R9_REGNUM: | |
574 | case SIM_ARM_R10_REGNUM: | |
575 | case SIM_ARM_R11_REGNUM: | |
576 | case SIM_ARM_R12_REGNUM: | |
577 | case SIM_ARM_R13_REGNUM: | |
578 | case SIM_ARM_R14_REGNUM: | |
579 | case SIM_ARM_R15_REGNUM: /* PC */ | |
580 | regval = ARMul_GetReg (state, state->Mode, rn); | |
581 | break; | |
582 | ||
583 | case SIM_ARM_FP0_REGNUM: | |
584 | case SIM_ARM_FP1_REGNUM: | |
585 | case SIM_ARM_FP2_REGNUM: | |
586 | case SIM_ARM_FP3_REGNUM: | |
587 | case SIM_ARM_FP4_REGNUM: | |
588 | case SIM_ARM_FP5_REGNUM: | |
589 | case SIM_ARM_FP6_REGNUM: | |
590 | case SIM_ARM_FP7_REGNUM: | |
591 | case SIM_ARM_FPS_REGNUM: | |
592 | memset (memory, 0, length); | |
593 | return 0; | |
594 | ||
595 | case SIM_ARM_PS_REGNUM: | |
596 | regval = ARMul_GetCPSR (state); | |
597 | break; | |
598 | ||
f603c8fe NC |
599 | case SIM_ARM_MAVERIC_COP0R0_REGNUM: |
600 | case SIM_ARM_MAVERIC_COP0R1_REGNUM: | |
601 | case SIM_ARM_MAVERIC_COP0R2_REGNUM: | |
602 | case SIM_ARM_MAVERIC_COP0R3_REGNUM: | |
603 | case SIM_ARM_MAVERIC_COP0R4_REGNUM: | |
604 | case SIM_ARM_MAVERIC_COP0R5_REGNUM: | |
605 | case SIM_ARM_MAVERIC_COP0R6_REGNUM: | |
606 | case SIM_ARM_MAVERIC_COP0R7_REGNUM: | |
607 | case SIM_ARM_MAVERIC_COP0R8_REGNUM: | |
608 | case SIM_ARM_MAVERIC_COP0R9_REGNUM: | |
609 | case SIM_ARM_MAVERIC_COP0R10_REGNUM: | |
610 | case SIM_ARM_MAVERIC_COP0R11_REGNUM: | |
611 | case SIM_ARM_MAVERIC_COP0R12_REGNUM: | |
612 | case SIM_ARM_MAVERIC_COP0R13_REGNUM: | |
613 | case SIM_ARM_MAVERIC_COP0R14_REGNUM: | |
614 | case SIM_ARM_MAVERIC_COP0R15_REGNUM: | |
615 | memcpy (memory, & DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM], | |
616 | sizeof (struct maverick_regs)); | |
617 | return sizeof (struct maverick_regs); | |
618 | ||
619 | case SIM_ARM_MAVERIC_DSPSC_REGNUM: | |
620 | memcpy (memory, & DSPsc, sizeof DSPsc); | |
621 | return sizeof DSPsc; | |
622 | ||
0f026fd0 NC |
623 | case SIM_ARM_IWMMXT_COP0R0_REGNUM: |
624 | case SIM_ARM_IWMMXT_COP0R1_REGNUM: | |
625 | case SIM_ARM_IWMMXT_COP0R2_REGNUM: | |
626 | case SIM_ARM_IWMMXT_COP0R3_REGNUM: | |
627 | case SIM_ARM_IWMMXT_COP0R4_REGNUM: | |
628 | case SIM_ARM_IWMMXT_COP0R5_REGNUM: | |
629 | case SIM_ARM_IWMMXT_COP0R6_REGNUM: | |
630 | case SIM_ARM_IWMMXT_COP0R7_REGNUM: | |
631 | case SIM_ARM_IWMMXT_COP0R8_REGNUM: | |
632 | case SIM_ARM_IWMMXT_COP0R9_REGNUM: | |
633 | case SIM_ARM_IWMMXT_COP0R10_REGNUM: | |
634 | case SIM_ARM_IWMMXT_COP0R11_REGNUM: | |
635 | case SIM_ARM_IWMMXT_COP0R12_REGNUM: | |
636 | case SIM_ARM_IWMMXT_COP0R13_REGNUM: | |
637 | case SIM_ARM_IWMMXT_COP0R14_REGNUM: | |
638 | case SIM_ARM_IWMMXT_COP0R15_REGNUM: | |
639 | case SIM_ARM_IWMMXT_COP1R0_REGNUM: | |
640 | case SIM_ARM_IWMMXT_COP1R1_REGNUM: | |
641 | case SIM_ARM_IWMMXT_COP1R2_REGNUM: | |
642 | case SIM_ARM_IWMMXT_COP1R3_REGNUM: | |
643 | case SIM_ARM_IWMMXT_COP1R4_REGNUM: | |
644 | case SIM_ARM_IWMMXT_COP1R5_REGNUM: | |
645 | case SIM_ARM_IWMMXT_COP1R6_REGNUM: | |
646 | case SIM_ARM_IWMMXT_COP1R7_REGNUM: | |
647 | case SIM_ARM_IWMMXT_COP1R8_REGNUM: | |
648 | case SIM_ARM_IWMMXT_COP1R9_REGNUM: | |
649 | case SIM_ARM_IWMMXT_COP1R10_REGNUM: | |
650 | case SIM_ARM_IWMMXT_COP1R11_REGNUM: | |
651 | case SIM_ARM_IWMMXT_COP1R12_REGNUM: | |
652 | case SIM_ARM_IWMMXT_COP1R13_REGNUM: | |
653 | case SIM_ARM_IWMMXT_COP1R14_REGNUM: | |
654 | case SIM_ARM_IWMMXT_COP1R15_REGNUM: | |
655 | return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory); | |
3a3d6f65 | 656 | |
26216b98 AC |
657 | default: |
658 | return 0; | |
659 | } | |
272fcdcd | 660 | |
9256caa6 | 661 | while (len) |
272fcdcd NC |
662 | { |
663 | tomem (state, memory, regval); | |
664 | ||
9256caa6 | 665 | len -= 4; |
272fcdcd NC |
666 | memory += 4; |
667 | regval = 0; | |
668 | } | |
669 | ||
9256caa6 | 670 | return length; |
c906108c SS |
671 | } |
672 | ||
de4112fa NC |
673 | #ifdef SIM_TARGET_SWITCHES |
674 | ||
675 | static void sim_target_parse_arg_array PARAMS ((char **)); | |
676 | ||
677 | typedef struct | |
678 | { | |
679 | char * swi_option; | |
680 | unsigned int swi_mask; | |
681 | } swi_options; | |
682 | ||
683 | #define SWI_SWITCH "--swi-support" | |
684 | ||
685 | static swi_options options[] = | |
686 | { | |
687 | { "none", 0 }, | |
688 | { "demon", SWI_MASK_DEMON }, | |
689 | { "angel", SWI_MASK_ANGEL }, | |
690 | { "redboot", SWI_MASK_REDBOOT }, | |
691 | { "all", -1 }, | |
692 | { "NONE", 0 }, | |
693 | { "DEMON", SWI_MASK_DEMON }, | |
694 | { "ANGEL", SWI_MASK_ANGEL }, | |
695 | { "REDBOOT", SWI_MASK_REDBOOT }, | |
696 | { "ALL", -1 } | |
697 | }; | |
698 | ||
699 | ||
700 | int | |
701 | sim_target_parse_command_line (argc, argv) | |
702 | int argc; | |
703 | char ** argv; | |
704 | { | |
705 | int i; | |
706 | ||
707 | for (i = 1; i < argc; i++) | |
708 | { | |
709 | char * ptr = argv[i]; | |
710 | int arg; | |
711 | ||
712 | if ((ptr == NULL) || (* ptr != '-')) | |
713 | break; | |
714 | ||
715 | if (strncmp (ptr, SWI_SWITCH, sizeof SWI_SWITCH - 1) != 0) | |
716 | continue; | |
717 | ||
718 | if (ptr[sizeof SWI_SWITCH - 1] == 0) | |
719 | { | |
720 | /* Remove this option from the argv array. */ | |
721 | for (arg = i; arg < argc; arg ++) | |
722 | argv[arg] = argv[arg + 1]; | |
723 | argc --; | |
724 | ||
725 | ptr = argv[i]; | |
726 | } | |
727 | else | |
728 | ptr += sizeof SWI_SWITCH; | |
729 | ||
730 | swi_mask = 0; | |
731 | ||
732 | while (* ptr) | |
733 | { | |
734 | int i; | |
735 | ||
736 | for (i = sizeof options / sizeof options[0]; i--;) | |
737 | if (strncmp (ptr, options[i].swi_option, | |
738 | strlen (options[i].swi_option)) == 0) | |
739 | { | |
740 | swi_mask |= options[i].swi_mask; | |
741 | ptr += strlen (options[i].swi_option); | |
742 | ||
743 | if (* ptr == ',') | |
744 | ++ ptr; | |
745 | ||
746 | break; | |
747 | } | |
748 | ||
749 | if (i < 0) | |
750 | break; | |
751 | } | |
752 | ||
753 | if (* ptr != 0) | |
754 | fprintf (stderr, "Ignoring swi options: %s\n", ptr); | |
755 | ||
756 | /* Remove this option from the argv array. */ | |
757 | for (arg = i; arg < argc; arg ++) | |
758 | argv[arg] = argv[arg + 1]; | |
759 | argc --; | |
760 | i --; | |
761 | } | |
762 | return argc; | |
763 | } | |
764 | ||
765 | static void | |
766 | sim_target_parse_arg_array (argv) | |
767 | char ** argv; | |
768 | { | |
769 | int i; | |
770 | ||
771 | for (i = 0; argv[i]; i++) | |
772 | ; | |
773 | ||
8944021f | 774 | sim_target_parse_command_line (i, argv); |
de4112fa NC |
775 | } |
776 | ||
777 | void | |
6efef468 JM |
778 | sim_target_display_usage (help) |
779 | int help; | |
de4112fa | 780 | { |
6efef468 JM |
781 | FILE *stream = help ? stdout : stderr; |
782 | ||
783 | fprintf (stream, "%s=<list> Comma seperated list of SWI protocols to supoport.\n\ | |
de4112fa NC |
784 | This list can contain: NONE, DEMON, ANGEL, REDBOOT and/or ALL.\n", |
785 | SWI_SWITCH); | |
786 | } | |
787 | #endif | |
788 | ||
c906108c SS |
789 | SIM_DESC |
790 | sim_open (kind, ptr, abfd, argv) | |
791 | SIM_OPEN_KIND kind; | |
792 | host_callback *ptr; | |
6b4a8935 | 793 | struct bfd *abfd; |
c906108c SS |
794 | char **argv; |
795 | { | |
796 | sim_kind = kind; | |
6c9e0292 | 797 | if (myname) free (myname); |
c1a72ffd | 798 | myname = (char *) xstrdup (argv[0]); |
c906108c | 799 | sim_callback = ptr; |
dfcd3bfb | 800 | |
de4112fa NC |
801 | #ifdef SIM_TARGET_SWITCHES |
802 | sim_target_parse_arg_array (argv); | |
803 | #endif | |
804 | ||
c906108c SS |
805 | /* Decide upon the endian-ness of the processor. |
806 | If we can, get the information from the bfd itself. | |
807 | Otherwise look to see if we have been given a command | |
808 | line switch that tells us. Otherwise default to little endian. */ | |
809 | if (abfd != NULL) | |
810 | big_endian = bfd_big_endian (abfd); | |
811 | else if (argv[1] != NULL) | |
812 | { | |
813 | int i; | |
dfcd3bfb | 814 | |
058f270d | 815 | /* Scan for endian-ness and memory-size switches. */ |
c906108c | 816 | for (i = 0; (argv[i] != NULL) && (argv[i][0] != 0); i++) |
dfcd3bfb JM |
817 | if (argv[i][0] == '-' && argv[i][1] == 'E') |
818 | { | |
819 | char c; | |
820 | ||
821 | if ((c = argv[i][2]) == 0) | |
822 | { | |
823 | ++i; | |
824 | c = argv[i][0]; | |
825 | } | |
826 | ||
827 | switch (c) | |
828 | { | |
829 | case 0: | |
830 | sim_callback->printf_filtered | |
831 | (sim_callback, "No argument to -E option provided\n"); | |
832 | break; | |
833 | ||
834 | case 'b': | |
835 | case 'B': | |
836 | big_endian = 1; | |
837 | break; | |
838 | ||
839 | case 'l': | |
840 | case 'L': | |
841 | big_endian = 0; | |
842 | break; | |
843 | ||
844 | default: | |
845 | sim_callback->printf_filtered | |
846 | (sim_callback, "Unrecognised argument to -E option\n"); | |
847 | break; | |
848 | } | |
849 | } | |
058f270d AC |
850 | else if (argv[i][0] == '-' && argv[i][1] == 'm') |
851 | { | |
852 | if (argv[i][2] != '\0') | |
853 | sim_size (atoi (&argv[i][2])); | |
854 | else if (argv[i + 1] != NULL) | |
855 | { | |
856 | sim_size (atoi (argv[i + 1])); | |
857 | i++; | |
858 | } | |
859 | else | |
860 | { | |
861 | sim_callback->printf_filtered (sim_callback, | |
862 | "Missing argument to -m option\n"); | |
863 | return NULL; | |
864 | } | |
865 | ||
866 | } | |
c906108c SS |
867 | } |
868 | ||
869 | return (SIM_DESC) 1; | |
870 | } | |
871 | ||
872 | void | |
873 | sim_close (sd, quitting) | |
6d358e86 NC |
874 | SIM_DESC sd ATTRIBUTE_UNUSED; |
875 | int quitting ATTRIBUTE_UNUSED; | |
c906108c | 876 | { |
86c735a5 NC |
877 | if (myname) |
878 | free (myname); | |
6c9e0292 | 879 | myname = NULL; |
c906108c SS |
880 | } |
881 | ||
882 | SIM_RC | |
883 | sim_load (sd, prog, abfd, from_tty) | |
884 | SIM_DESC sd; | |
885 | char *prog; | |
886 | bfd *abfd; | |
6d358e86 | 887 | int from_tty ATTRIBUTE_UNUSED; |
c906108c | 888 | { |
c906108c SS |
889 | bfd *prog_bfd; |
890 | ||
891 | prog_bfd = sim_load_file (sd, myname, sim_callback, prog, abfd, | |
dfcd3bfb | 892 | sim_kind == SIM_OPEN_DEBUG, 0, sim_write); |
c906108c SS |
893 | if (prog_bfd == NULL) |
894 | return SIM_RC_FAIL; | |
895 | ARMul_SetPC (state, bfd_get_start_address (prog_bfd)); | |
896 | if (abfd == NULL) | |
897 | bfd_close (prog_bfd); | |
898 | return SIM_RC_OK; | |
899 | } | |
900 | ||
901 | void | |
902 | sim_stop_reason (sd, reason, sigrc) | |
6d358e86 | 903 | SIM_DESC sd ATTRIBUTE_UNUSED; |
c906108c SS |
904 | enum sim_stop *reason; |
905 | int *sigrc; | |
906 | { | |
7a292a7a SS |
907 | if (stop_simulator) |
908 | { | |
909 | *reason = sim_stopped; | |
a493e3e2 | 910 | *sigrc = GDB_SIGNAL_INT; |
7a292a7a SS |
911 | } |
912 | else if (state->EndCondition == 0) | |
c906108c SS |
913 | { |
914 | *reason = sim_exited; | |
915 | *sigrc = state->Reg[0] & 255; | |
916 | } | |
917 | else | |
918 | { | |
919 | *reason = sim_stopped; | |
920 | if (state->EndCondition == RDIError_BreakpointReached) | |
a493e3e2 | 921 | *sigrc = GDB_SIGNAL_TRAP; |
0f026fd0 NC |
922 | else if ( state->EndCondition == RDIError_DataAbort |
923 | || state->EndCondition == RDIError_AddressException) | |
a493e3e2 | 924 | *sigrc = GDB_SIGNAL_BUS; |
c906108c SS |
925 | else |
926 | *sigrc = 0; | |
927 | } | |
928 | } | |
929 | ||
930 | void | |
931 | sim_do_command (sd, cmd) | |
6d358e86 NC |
932 | SIM_DESC sd ATTRIBUTE_UNUSED; |
933 | char *cmd ATTRIBUTE_UNUSED; | |
dfcd3bfb | 934 | { |
86c735a5 NC |
935 | (*sim_callback->printf_filtered) |
936 | (sim_callback, | |
937 | "This simulator does not accept any commands.\n"); | |
c906108c SS |
938 | } |
939 | ||
c906108c SS |
940 | void |
941 | sim_set_callbacks (ptr) | |
942 | host_callback *ptr; | |
943 | { | |
944 | sim_callback = ptr; | |
945 | } | |
af9f7da7 MF |
946 | |
947 | char ** | |
3cb2ab1a | 948 | sim_complete_command (SIM_DESC sd, const char *text, const char *word) |
af9f7da7 MF |
949 | { |
950 | return NULL; | |
951 | } |