Commit | Line | Data |
---|---|---|
ef016f83 MF |
1 | /* Blackfin Ethernet Media Access Controller (EMAC) model. |
2 | ||
3 | Copyright (C) 2010-2011 Free Software Foundation, Inc. | |
4 | Contributed by Analog Devices, Inc. | |
5 | ||
6 | This file is part of simulators. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | ||
23 | #include <errno.h> | |
24 | #include <fcntl.h> | |
25 | #include <unistd.h> | |
26 | ||
27 | #ifdef HAVE_SYS_IOCTL_H | |
28 | #include <sys/ioctl.h> | |
29 | #endif | |
30 | #ifdef HAVE_NET_IF_H | |
31 | #include <net/if.h> | |
32 | #endif | |
33 | #ifdef HAVE_LINUX_IF_TUN_H | |
34 | #include <linux/if_tun.h> | |
35 | #endif | |
36 | ||
37 | #ifdef HAVE_LINUX_IF_TUN_H | |
38 | # define WITH_TUN 1 | |
39 | #else | |
40 | # define WITH_TUN 0 | |
41 | #endif | |
42 | ||
43 | #include "sim-main.h" | |
44 | #include "sim-hw.h" | |
45 | #include "devices.h" | |
46 | #include "dv-bfin_emac.h" | |
47 | ||
48 | /* XXX: This doesn't support partial DMA transfers. */ | |
49 | /* XXX: The TUN pieces should be pushed to the PHY so that we work with | |
50 | multiple "networks" and the PHY takes care of it. */ | |
51 | ||
52 | struct bfin_emac | |
53 | { | |
54 | /* This top portion matches common dv_bfin struct. */ | |
55 | bu32 base; | |
56 | struct hw *dma_master; | |
57 | bool acked; | |
58 | ||
59 | int tap; | |
60 | #if WITH_TUN | |
61 | struct ifreq ifr; | |
62 | #endif | |
63 | bu32 rx_crc; | |
64 | ||
65 | /* Order after here is important -- matches hardware MMR layout. */ | |
66 | bu32 opmode, addrlo, addrhi, hashlo, hashhi, staadd, stadat, flc, vlan1, vlan2; | |
67 | bu32 _pad0; | |
68 | bu32 wkup_ctl, wkup_ffmsk0, wkup_ffmsk1, wkup_ffmsk2, wkup_ffmsk3; | |
69 | bu32 wkup_ffcmd, wkup_ffoff, wkup_ffcrc0, wkup_ffcrc1; | |
70 | bu32 _pad1[4]; | |
71 | bu32 sysctl, systat, rx_stat, rx_stky, rx_irqe, tx_stat, tx_stky, tx_irqe; | |
72 | bu32 mmc_ctl, mmc_rirqs, mmc_rirqe, mmc_tirqs, mmc_tirqe; | |
73 | bu32 _pad2[3]; | |
74 | bu16 BFIN_MMR_16(ptp_ctl); | |
75 | bu16 BFIN_MMR_16(ptp_ie); | |
76 | bu16 BFIN_MMR_16(ptp_istat); | |
77 | bu32 ptp_foff, ptp_fv1, ptp_fv2, ptp_fv3, ptp_addend, ptp_accr, ptp_offset; | |
78 | bu32 ptp_timelo, ptp_timehi, ptp_rxsnaplo, ptp_rxsnaphi, ptp_txsnaplo; | |
79 | bu32 ptp_txsnaphi, ptp_alarmlo, ptp_alarmhi, ptp_id_off, ptp_id_snap; | |
80 | bu32 ptp_pps_startlo, ptp_pps_starthi, ptp_pps_period; | |
81 | bu32 _pad3[1]; | |
82 | bu32 rxc_ok, rxc_fcs, rxc_lign, rxc_octet, rxc_dmaovf, rxc_unicst, rxc_multi; | |
83 | bu32 rxc_broad, rxc_lnerri, rxc_lnerro, rxc_long, rxc_macctl, rxc_opcode; | |
84 | bu32 rxc_pause, rxc_allfrm, rxc_alloct, rxc_typed, rxc_short, rxc_eq64; | |
85 | bu32 rxc_lt128, rxc_lt256, rxc_lt512, rxc_lt1024, rxc_ge1024; | |
86 | bu32 _pad4[8]; | |
87 | bu32 txc_ok, txc_1col, txc_gt1col, txc_octet, txc_defer, txc_latecl; | |
88 | bu32 txc_xs_col, txc_dmaund, txc_crserr, txc_unicst, txc_multi, txc_broad; | |
89 | bu32 txc_xs_dfr, txc_macctl, txc_allfrm, txc_alloct, txc_eq64, txc_lt128; | |
90 | bu32 txc_lt256, txc_lt512, txc_lt1024, txc_ge1024, txc_abort; | |
91 | }; | |
92 | #define mmr_base() offsetof(struct bfin_emac, opmode) | |
93 | #define mmr_offset(mmr) (offsetof(struct bfin_emac, mmr) - mmr_base()) | |
94 | #define mmr_idx(mmr) (mmr_offset (mmr) / 4) | |
95 | ||
96 | static const char * const mmr_names[BFIN_MMR_EMAC_SIZE / 4] = { | |
97 | "EMAC_OPMODE", "EMAC_ADDRLO", "EMAC_ADDRHI", "EMAC_HASHLO", "EMAC_HASHHI", | |
98 | "EMAC_STAADD", "EMAC_STADAT", "EMAC_FLC", "EMAC_VLAN1", "EMAC_VLAN2", NULL, | |
99 | "EMAC_WKUP_CTL", "EMAC_WKUP_FFMSK0", "EMAC_WKUP_FFMSK1", "EMAC_WKUP_FFMSK2", | |
100 | "EMAC_WKUP_FFMSK3", "EMAC_WKUP_FFCMD", "EMAC_WKUP_FFOFF", "EMAC_WKUP_FFCRC0", | |
101 | "EMAC_WKUP_FFCRC1", [mmr_idx (sysctl)] = "EMAC_SYSCTL", "EMAC_SYSTAT", | |
102 | "EMAC_RX_STAT", "EMAC_RX_STKY", "EMAC_RX_IRQE", "EMAC_TX_STAT", | |
103 | "EMAC_TX_STKY", "EMAC_TX_IRQE", "EMAC_MMC_CTL", "EMAC_MMC_RIRQS", | |
104 | "EMAC_MMC_RIRQE", "EMAC_MMC_TIRQS", "EMAC_MMC_TIRQE", | |
105 | [mmr_idx (ptp_ctl)] = "EMAC_PTP_CTL", "EMAC_PTP_IE", "EMAC_PTP_ISTAT", | |
106 | "EMAC_PTP_FOFF", "EMAC_PTP_FV1", "EMAC_PTP_FV2", "EMAC_PTP_FV3", | |
107 | "EMAC_PTP_ADDEND", "EMAC_PTP_ACCR", "EMAC_PTP_OFFSET", "EMAC_PTP_TIMELO", | |
108 | "EMAC_PTP_TIMEHI", "EMAC_PTP_RXSNAPLO", "EMAC_PTP_RXSNAPHI", | |
109 | "EMAC_PTP_TXSNAPLO", "EMAC_PTP_TXSNAPHI", "EMAC_PTP_ALARMLO", | |
110 | "EMAC_PTP_ALARMHI", "EMAC_PTP_ID_OFF", "EMAC_PTP_ID_SNAP", | |
111 | "EMAC_PTP_PPS_STARTLO", "EMAC_PTP_PPS_STARTHI", "EMAC_PTP_PPS_PERIOD", | |
112 | [mmr_idx (rxc_ok)] = "EMAC_RXC_OK", "EMAC_RXC_FCS", "EMAC_RXC_LIGN", | |
113 | "EMAC_RXC_OCTET", "EMAC_RXC_DMAOVF", "EMAC_RXC_UNICST", "EMAC_RXC_MULTI", | |
114 | "EMAC_RXC_BROAD", "EMAC_RXC_LNERRI", "EMAC_RXC_LNERRO", "EMAC_RXC_LONG", | |
115 | "EMAC_RXC_MACCTL", "EMAC_RXC_OPCODE", "EMAC_RXC_PAUSE", "EMAC_RXC_ALLFRM", | |
116 | "EMAC_RXC_ALLOCT", "EMAC_RXC_TYPED", "EMAC_RXC_SHORT", "EMAC_RXC_EQ64", | |
117 | "EMAC_RXC_LT128", "EMAC_RXC_LT256", "EMAC_RXC_LT512", "EMAC_RXC_LT1024", | |
118 | "EMAC_RXC_GE1024", | |
119 | [mmr_idx (txc_ok)] = "EMAC_TXC_OK", "EMAC_TXC_1COL", "EMAC_TXC_GT1COL", | |
120 | "EMAC_TXC_OCTET", "EMAC_TXC_DEFER", "EMAC_TXC_LATECL", "EMAC_TXC_XS_COL", | |
121 | "EMAC_TXC_DMAUND", "EMAC_TXC_CRSERR", "EMAC_TXC_UNICST", "EMAC_TXC_MULTI", | |
122 | "EMAC_TXC_BROAD", "EMAC_TXC_XS_DFR", "EMAC_TXC_MACCTL", "EMAC_TXC_ALLFRM", | |
123 | "EMAC_TXC_ALLOCT", "EMAC_TXC_EQ64", "EMAC_TXC_LT128", "EMAC_TXC_LT256", | |
124 | "EMAC_TXC_LT512", "EMAC_TXC_LT1024", "EMAC_TXC_GE1024", "EMAC_TXC_ABORT", | |
125 | }; | |
126 | #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>") | |
127 | ||
128 | static struct hw * | |
129 | mii_find_phy (struct hw *me, bu8 addr) | |
130 | { | |
131 | struct hw *phy = hw_child (me); | |
132 | while (phy && --addr) | |
133 | phy = hw_sibling (phy); | |
134 | return phy; | |
135 | } | |
136 | ||
137 | static void | |
138 | mii_write (struct hw *me) | |
139 | { | |
140 | SIM_DESC sd = hw_system (me); | |
141 | struct bfin_emac *emac = hw_data (me); | |
142 | struct hw *phy; | |
143 | bu8 addr = PHYAD (emac->staadd); | |
144 | bu8 reg = REGAD (emac->staadd); | |
145 | bu16 data = emac->stadat; | |
146 | ||
147 | phy = mii_find_phy (me, addr); | |
148 | if (!phy) | |
149 | return; | |
150 | sim_hw_io_write_buffer (sd, phy, &data, 1, reg, 2); | |
151 | } | |
152 | ||
153 | static void | |
154 | mii_read (struct hw *me) | |
155 | { | |
156 | SIM_DESC sd = hw_system (me); | |
157 | struct bfin_emac *emac = hw_data (me); | |
158 | struct hw *phy; | |
159 | bu8 addr = PHYAD (emac->staadd); | |
160 | bu8 reg = REGAD (emac->staadd); | |
161 | bu16 data; | |
162 | ||
163 | phy = mii_find_phy (me, addr); | |
164 | if (!phy || sim_hw_io_read_buffer (sd, phy, &data, 1, reg, 2) != 2) | |
165 | data = 0xffff; | |
166 | ||
167 | emac->stadat = data; | |
168 | } | |
169 | ||
170 | static unsigned | |
171 | bfin_emac_io_write_buffer (struct hw *me, const void *source, | |
172 | int space, address_word addr, unsigned nr_bytes) | |
173 | { | |
174 | struct bfin_emac *emac = hw_data (me); | |
175 | bu32 mmr_off; | |
176 | bu32 value; | |
177 | bu32 *valuep; | |
178 | ||
179 | /* XXX: 16bit accesses are allowed ... */ | |
180 | dv_bfin_mmr_require_32 (me, addr, nr_bytes, true); | |
181 | value = dv_load_4 (source); | |
182 | ||
183 | mmr_off = addr - emac->base; | |
184 | valuep = (void *)((unsigned long)emac + mmr_base() + mmr_off); | |
185 | ||
186 | HW_TRACE_WRITE (); | |
187 | ||
188 | switch (mmr_off) | |
189 | { | |
190 | case mmr_offset(hashlo): | |
191 | case mmr_offset(hashhi): | |
192 | case mmr_offset(stadat): | |
193 | case mmr_offset(flc): | |
194 | case mmr_offset(vlan1): | |
195 | case mmr_offset(vlan2): | |
196 | case mmr_offset(wkup_ffmsk0): | |
197 | case mmr_offset(wkup_ffmsk1): | |
198 | case mmr_offset(wkup_ffmsk2): | |
199 | case mmr_offset(wkup_ffmsk3): | |
200 | case mmr_offset(wkup_ffcmd): | |
201 | case mmr_offset(wkup_ffoff): | |
202 | case mmr_offset(wkup_ffcrc0): | |
203 | case mmr_offset(wkup_ffcrc1): | |
204 | case mmr_offset(sysctl): | |
205 | case mmr_offset(rx_irqe): | |
206 | case mmr_offset(tx_irqe): | |
207 | case mmr_offset(mmc_rirqe): | |
208 | case mmr_offset(mmc_tirqe): | |
209 | *valuep = value; | |
210 | break; | |
211 | case mmr_offset(opmode): | |
212 | if (!(*valuep & RE) && (value & RE)) | |
213 | emac->rx_stat &= ~RX_COMP; | |
214 | if (!(*valuep & TE) && (value & TE)) | |
215 | emac->tx_stat &= ~TX_COMP; | |
216 | *valuep = value; | |
217 | break; | |
218 | case mmr_offset(addrlo): | |
219 | case mmr_offset(addrhi): | |
220 | *valuep = value; | |
221 | break; | |
222 | case mmr_offset(wkup_ctl): | |
223 | dv_w1c_4_partial (valuep, value, 0xf20); | |
224 | break; | |
225 | case mmr_offset(systat): | |
226 | dv_w1c_4 (valuep, value, 0x1e); | |
227 | break; | |
228 | case mmr_offset(staadd): | |
229 | *valuep = value | STABUSY; | |
230 | if (value & STAOP) | |
231 | mii_write (me); | |
232 | else | |
233 | mii_read (me); | |
234 | *valuep &= ~STABUSY; | |
235 | break; | |
236 | case mmr_offset(rx_stat): | |
237 | case mmr_offset(tx_stat): | |
238 | /* Discard writes to these. */ | |
239 | break; | |
240 | case mmr_offset(rx_stky): | |
241 | case mmr_offset(tx_stky): | |
242 | case mmr_offset(mmc_rirqs): | |
243 | case mmr_offset(mmc_tirqs): | |
244 | dv_w1c_4 (valuep, value, 0); | |
245 | break; | |
246 | case mmr_offset(mmc_ctl): | |
247 | /* Writing to bit 0 clears all counters. */ | |
248 | *valuep = value & ~1; | |
249 | if (value & 1) | |
250 | { | |
251 | memset (&emac->rxc_ok, 0, mmr_offset (rxc_ge1024) - mmr_offset (rxc_ok) + 4); | |
252 | memset (&emac->txc_ok, 0, mmr_offset (txc_abort) - mmr_offset (txc_ok) + 4); | |
253 | } | |
254 | break; | |
255 | case mmr_offset(rxc_ok) ... mmr_offset(rxc_ge1024): | |
256 | case mmr_offset(txc_ok) ... mmr_offset(txc_abort): | |
257 | /* XXX: Are these supposed to be read-only ? */ | |
258 | *valuep = value; | |
259 | break; | |
260 | case mmr_offset(ptp_ctl) ... mmr_offset(ptp_pps_period): | |
261 | /* XXX: Only on some models; ignore for now. */ | |
262 | break; | |
263 | default: | |
264 | dv_bfin_mmr_invalid (me, addr, nr_bytes, true); | |
265 | break; | |
266 | } | |
267 | ||
268 | return nr_bytes; | |
269 | } | |
270 | ||
271 | static unsigned | |
272 | bfin_emac_io_read_buffer (struct hw *me, void *dest, | |
273 | int space, address_word addr, unsigned nr_bytes) | |
274 | { | |
275 | struct bfin_emac *emac = hw_data (me); | |
276 | bu32 mmr_off; | |
277 | bu32 *valuep; | |
278 | ||
279 | /* XXX: 16bit accesses are allowed ... */ | |
280 | dv_bfin_mmr_require_32 (me, addr, nr_bytes, false); | |
281 | ||
282 | mmr_off = addr - emac->base; | |
283 | valuep = (void *)((unsigned long)emac + mmr_base() + mmr_off); | |
284 | ||
285 | HW_TRACE_READ (); | |
286 | ||
287 | switch (mmr_off) | |
288 | { | |
289 | case mmr_offset(opmode): | |
290 | case mmr_offset(addrlo): | |
291 | case mmr_offset(addrhi): | |
292 | case mmr_offset(hashlo): | |
293 | case mmr_offset(hashhi): | |
294 | case mmr_offset(staadd): | |
295 | case mmr_offset(stadat): | |
296 | case mmr_offset(flc): | |
297 | case mmr_offset(vlan1): | |
298 | case mmr_offset(vlan2): | |
299 | case mmr_offset(wkup_ctl): | |
300 | case mmr_offset(wkup_ffmsk0): | |
301 | case mmr_offset(wkup_ffmsk1): | |
302 | case mmr_offset(wkup_ffmsk2): | |
303 | case mmr_offset(wkup_ffmsk3): | |
304 | case mmr_offset(wkup_ffcmd): | |
305 | case mmr_offset(wkup_ffoff): | |
306 | case mmr_offset(wkup_ffcrc0): | |
307 | case mmr_offset(wkup_ffcrc1): | |
308 | case mmr_offset(sysctl): | |
309 | case mmr_offset(systat): | |
310 | case mmr_offset(rx_stat): | |
311 | case mmr_offset(rx_stky): | |
312 | case mmr_offset(rx_irqe): | |
313 | case mmr_offset(tx_stat): | |
314 | case mmr_offset(tx_stky): | |
315 | case mmr_offset(tx_irqe): | |
316 | case mmr_offset(mmc_rirqs): | |
317 | case mmr_offset(mmc_rirqe): | |
318 | case mmr_offset(mmc_tirqs): | |
319 | case mmr_offset(mmc_tirqe): | |
320 | case mmr_offset(mmc_ctl): | |
321 | case mmr_offset(rxc_ok) ... mmr_offset(rxc_ge1024): | |
322 | case mmr_offset(txc_ok) ... mmr_offset(txc_abort): | |
323 | dv_store_4 (dest, *valuep); | |
324 | break; | |
325 | case mmr_offset(ptp_ctl) ... mmr_offset(ptp_pps_period): | |
326 | /* XXX: Only on some models; ignore for now. */ | |
327 | break; | |
328 | default: | |
329 | dv_bfin_mmr_invalid (me, addr, nr_bytes, false); | |
330 | break; | |
331 | } | |
332 | ||
333 | return nr_bytes; | |
334 | } | |
335 | ||
336 | static void | |
337 | attach_bfin_emac_regs (struct hw *me, struct bfin_emac *emac) | |
338 | { | |
339 | address_word attach_address; | |
340 | int attach_space; | |
341 | unsigned attach_size; | |
342 | reg_property_spec reg; | |
343 | ||
344 | if (hw_find_property (me, "reg") == NULL) | |
345 | hw_abort (me, "Missing \"reg\" property"); | |
346 | ||
347 | if (!hw_find_reg_array_property (me, "reg", 0, ®)) | |
348 | hw_abort (me, "\"reg\" property must contain three addr/size entries"); | |
349 | ||
350 | hw_unit_address_to_attach_address (hw_parent (me), | |
351 | ®.address, | |
352 | &attach_space, &attach_address, me); | |
353 | hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); | |
354 | ||
355 | if (attach_size != BFIN_MMR_EMAC_SIZE) | |
356 | hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_EMAC_SIZE); | |
357 | ||
358 | hw_attach_address (hw_parent (me), | |
359 | 0, attach_space, attach_address, attach_size, me); | |
360 | ||
361 | emac->base = attach_address; | |
362 | } | |
363 | ||
364 | static struct dv_bfin *dma_tx; | |
365 | ||
366 | static unsigned | |
367 | bfin_emac_dma_read_buffer (struct hw *me, void *dest, int space, | |
368 | unsigned_word addr, unsigned nr_bytes) | |
369 | { | |
370 | struct bfin_emac *emac = hw_data (me); | |
371 | struct dv_bfin *dma = hw_data (emac->dma_master); | |
372 | unsigned char *data = dest; | |
373 | static bool flop; /* XXX: This sucks. */ | |
374 | bu16 len; | |
375 | ssize_t ret; | |
376 | ||
377 | HW_TRACE_DMA_READ (); | |
378 | ||
379 | if (dma_tx == dma) | |
380 | { | |
381 | /* Handle the TX turn around and write the status. */ | |
382 | emac->tx_stat |= TX_OK; | |
383 | emac->tx_stky |= TX_OK; | |
384 | ||
385 | memcpy (data, &emac->tx_stat, 4); | |
386 | ||
387 | dma->acked = true; | |
388 | return 4; | |
389 | } | |
390 | ||
391 | if (!(emac->opmode & RE)) | |
392 | return 0; | |
393 | ||
394 | if (!flop) | |
395 | { | |
396 | ssize_t pad_ret; | |
397 | /* Outgoing DMA buffer has 16bit len prepended to it. */ | |
398 | data += 2; | |
399 | ||
400 | /* This doesn't seem to work. | |
401 | if (emac->sysctl & RXDWA) | |
402 | { | |
403 | memset (data, 0, 2); | |
404 | data += 2; | |
405 | } */ | |
406 | ||
407 | ret = read (emac->tap, data, nr_bytes); | |
408 | if (ret < 0) | |
409 | return 0; | |
410 | ret += 4; /* include crc */ | |
411 | pad_ret = MAX (ret + 4, 64); | |
412 | len = pad_ret; | |
413 | memcpy (dest, &len, 2); | |
414 | ||
415 | pad_ret = (pad_ret + 3) & ~3; | |
416 | if (ret < pad_ret) | |
417 | memset (data + ret, 0, pad_ret - ret); | |
418 | pad_ret += 4; | |
419 | ||
420 | /* XXX: Need to check -- u-boot doesn't look at this. */ | |
421 | if (emac->sysctl & RXCKS) | |
422 | { | |
423 | pad_ret += 4; | |
424 | emac->rx_crc = 0; | |
425 | } | |
426 | ret = pad_ret; | |
427 | ||
428 | /* XXX: Don't support promiscuous yet. */ | |
429 | emac->rx_stat |= RX_ACCEPT; | |
430 | emac->rx_stat = (emac->rx_stat & ~RX_FRLEN) | len; | |
431 | ||
432 | emac->rx_stat |= RX_COMP; | |
433 | emac->rx_stky |= RX_COMP; | |
434 | } | |
435 | else | |
436 | { | |
437 | /* Write the RX status and crc info. */ | |
438 | emac->rx_stat |= RX_OK; | |
439 | emac->rx_stky |= RX_OK; | |
440 | ||
441 | ret = 4; | |
442 | if (emac->sysctl & RXCKS) | |
443 | { | |
444 | memcpy (data, &emac->rx_crc, 4); | |
445 | data += 4; | |
446 | ret += 4; | |
447 | } | |
448 | memcpy (data, &emac->rx_stat, 4); | |
449 | } | |
450 | ||
451 | flop = !flop; | |
452 | dma->acked = true; | |
453 | return ret; | |
454 | } | |
455 | ||
456 | static unsigned | |
457 | bfin_emac_dma_write_buffer (struct hw *me, const void *source, | |
458 | int space, unsigned_word addr, | |
459 | unsigned nr_bytes, | |
460 | int violate_read_only_section) | |
461 | { | |
462 | struct bfin_emac *emac = hw_data (me); | |
463 | struct dv_bfin *dma = hw_data (emac->dma_master); | |
464 | const unsigned char *data = source; | |
465 | bu16 len; | |
466 | ssize_t ret; | |
467 | ||
468 | HW_TRACE_DMA_WRITE (); | |
469 | ||
470 | if (!(emac->opmode & TE)) | |
471 | return 0; | |
472 | ||
473 | /* Incoming DMA buffer has 16bit len prepended to it. */ | |
474 | memcpy (&len, data, 2); | |
475 | if (!len) | |
476 | return 0; | |
477 | ||
478 | ret = write (emac->tap, data + 2, len); | |
479 | if (ret < 0) | |
480 | return 0; | |
481 | ret += 2; | |
482 | ||
483 | emac->tx_stat |= TX_COMP; | |
484 | emac->tx_stky |= TX_COMP; | |
485 | ||
486 | dma_tx = dma; | |
487 | dma->acked = true; | |
488 | return ret; | |
489 | } | |
490 | ||
491 | static const struct hw_port_descriptor bfin_emac_ports[] = { | |
492 | { "tx", DV_PORT_TX, 0, output_port, }, | |
493 | { "rx", DV_PORT_RX, 0, output_port, }, | |
494 | { "stat", DV_PORT_STAT, 0, output_port, }, | |
495 | { NULL, 0, 0, 0, }, | |
496 | }; | |
497 | ||
498 | static void | |
499 | bfin_emac_attach_address_callback (struct hw *me, | |
500 | int level, | |
501 | int space, | |
502 | address_word addr, | |
503 | address_word nr_bytes, | |
504 | struct hw *client) | |
505 | { | |
506 | const hw_unit *unit = hw_unit_address (client); | |
507 | HW_TRACE ((me, "attach - level=%d, space=%d, addr=0x%lx, nr_bytes=%lu, client=%s", | |
508 | level, space, (unsigned long) addr, (unsigned long) nr_bytes, hw_path (client))); | |
509 | /* NOTE: At preset the space is assumed to be zero. Perhaphs the | |
510 | space should be mapped onto something for instance: space0 - | |
511 | unified memory; space1 - IO memory; ... */ | |
512 | sim_core_attach (hw_system (me), | |
513 | NULL, /*cpu*/ | |
514 | level + 10 + unit->cells[unit->nr_cells - 1], | |
515 | access_read_write_exec, | |
516 | space, addr, | |
517 | nr_bytes, | |
518 | 0, /* modulo */ | |
519 | client, | |
520 | NULL); | |
521 | } | |
522 | ||
523 | static void | |
524 | bfin_emac_delete (struct hw *me) | |
525 | { | |
526 | struct bfin_emac *emac = hw_data (me); | |
527 | close (emac->tap); | |
528 | } | |
529 | ||
530 | static void | |
531 | bfin_emac_tap_init (struct hw *me) | |
532 | { | |
533 | #if WITH_TUN | |
534 | struct bfin_emac *emac = hw_data (me); | |
535 | const hw_unit *unit; | |
536 | int flags; | |
537 | ||
538 | unit = hw_unit_address (me); | |
539 | ||
540 | emac->tap = open ("/dev/net/tun", O_RDWR); | |
541 | if (emac->tap == -1) | |
542 | { | |
543 | HW_TRACE ((me, "unable to open /dev/net/tun: %s", strerror (errno))); | |
544 | return; | |
545 | } | |
546 | ||
547 | memset (&emac->ifr, 0, sizeof (emac->ifr)); | |
548 | emac->ifr.ifr_flags = IFF_TAP | IFF_NO_PI; | |
549 | strcpy (emac->ifr.ifr_name, "tap-gdb"); | |
550 | ||
551 | flags = 1 * 1024 * 1024; | |
552 | if (ioctl (emac->tap, TUNSETIFF, &emac->ifr) < 0 | |
553 | #ifdef TUNSETNOCSUM | |
554 | || ioctl (emac->tap, TUNSETNOCSUM) < 0 | |
555 | #endif | |
556 | #ifdef TUNSETSNDBUF | |
557 | || ioctl (emac->tap, TUNSETSNDBUF, &flags) < 0 | |
558 | #endif | |
559 | ) | |
560 | { | |
561 | HW_TRACE ((me, "tap ioctl setup failed: %s", strerror (errno))); | |
562 | close (emac->tap); | |
563 | return; | |
564 | } | |
565 | ||
566 | flags = fcntl (emac->tap, F_GETFL); | |
567 | fcntl (emac->tap, F_SETFL, flags | O_NONBLOCK); | |
568 | #endif | |
569 | } | |
570 | ||
571 | static void | |
572 | bfin_emac_finish (struct hw *me) | |
573 | { | |
574 | struct bfin_emac *emac; | |
575 | ||
576 | emac = HW_ZALLOC (me, struct bfin_emac); | |
577 | ||
578 | set_hw_data (me, emac); | |
579 | set_hw_io_read_buffer (me, bfin_emac_io_read_buffer); | |
580 | set_hw_io_write_buffer (me, bfin_emac_io_write_buffer); | |
581 | set_hw_dma_read_buffer (me, bfin_emac_dma_read_buffer); | |
582 | set_hw_dma_write_buffer (me, bfin_emac_dma_write_buffer); | |
583 | set_hw_ports (me, bfin_emac_ports); | |
584 | set_hw_attach_address (me, bfin_emac_attach_address_callback); | |
585 | set_hw_delete (me, bfin_emac_delete); | |
586 | ||
587 | attach_bfin_emac_regs (me, emac); | |
588 | ||
589 | /* Initialize the EMAC. */ | |
590 | emac->addrlo = 0xffffffff; | |
591 | emac->addrhi = 0x0000ffff; | |
592 | emac->vlan1 = 0x0000ffff; | |
593 | emac->vlan2 = 0x0000ffff; | |
594 | emac->sysctl = 0x00003f00; | |
595 | emac->mmc_ctl = 0x0000000a; | |
596 | ||
597 | bfin_emac_tap_init (me); | |
598 | } | |
599 | ||
600 | const struct hw_descriptor dv_bfin_emac_descriptor[] = { | |
601 | {"bfin_emac", bfin_emac_finish,}, | |
602 | {NULL, NULL}, | |
603 | }; |