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ef016f83 MF |
1 | /* Blackfin JTAG model. |
2 | ||
3 | Copyright (C) 2010-2011 Free Software Foundation, Inc. | |
4 | Contributed by Analog Devices, Inc. | |
5 | ||
6 | This file is part of simulators. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | ||
23 | #include "sim-main.h" | |
24 | #include "devices.h" | |
25 | #include "dv-bfin_jtag.h" | |
26 | ||
27 | /* XXX: This is mostly a stub. There are more registers, but they're only | |
28 | accessible via the JTAG scan chain and not the MMR interface. */ | |
29 | ||
30 | struct bfin_jtag | |
31 | { | |
32 | bu32 base; | |
33 | ||
34 | /* Order after here is important -- matches hardware MMR layout. */ | |
35 | bu32 dspid; | |
36 | bu32 _pad0; | |
37 | bu32 dbgstat; | |
38 | }; | |
39 | #define mmr_base() offsetof(struct bfin_jtag, dspid) | |
40 | #define mmr_offset(mmr) (offsetof(struct bfin_jtag, mmr) - mmr_base()) | |
41 | ||
990d19fd MF |
42 | static const char * const mmr_names[] = |
43 | { | |
ef016f83 MF |
44 | "DSPID", NULL, "DBGSTAT", |
45 | }; | |
46 | #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>") | |
47 | ||
48 | static unsigned | |
49 | bfin_jtag_io_write_buffer (struct hw *me, const void *source, int space, | |
50 | address_word addr, unsigned nr_bytes) | |
51 | { | |
52 | struct bfin_jtag *jtag = hw_data (me); | |
53 | bu32 mmr_off; | |
54 | bu32 value; | |
55 | bu32 *valuep; | |
56 | ||
57 | value = dv_load_4 (source); | |
58 | mmr_off = addr - jtag->base; | |
59 | valuep = (void *)((unsigned long)jtag + mmr_base() + mmr_off); | |
60 | ||
61 | HW_TRACE_WRITE (); | |
62 | ||
63 | switch (mmr_off) | |
64 | { | |
65 | case mmr_offset(dbgstat): | |
9922f803 | 66 | dv_w1c_4 (valuep, value, 0xc); |
ef016f83 MF |
67 | break; |
68 | case mmr_offset(dspid): | |
69 | /* Discard writes to these. */ | |
70 | break; | |
71 | default: | |
72 | dv_bfin_mmr_invalid (me, addr, nr_bytes, true); | |
73 | break; | |
74 | } | |
75 | ||
76 | return nr_bytes; | |
77 | } | |
78 | ||
79 | static unsigned | |
80 | bfin_jtag_io_read_buffer (struct hw *me, void *dest, int space, | |
81 | address_word addr, unsigned nr_bytes) | |
82 | { | |
83 | struct bfin_jtag *jtag = hw_data (me); | |
84 | bu32 mmr_off; | |
85 | bu32 value; | |
86 | bu32 *valuep; | |
87 | ||
88 | mmr_off = addr - jtag->base; | |
89 | valuep = (void *)((unsigned long)jtag + mmr_base() + mmr_off); | |
90 | ||
91 | HW_TRACE_READ (); | |
92 | ||
93 | switch (mmr_off) | |
94 | { | |
95 | case mmr_offset(dbgstat): | |
96 | case mmr_offset(dspid): | |
97 | value = *valuep; | |
98 | break; | |
99 | default: | |
100 | while (1) /* Core MMRs -> exception -> doesn't return. */ | |
101 | dv_bfin_mmr_invalid (me, addr, nr_bytes, false); | |
102 | break; | |
103 | } | |
104 | ||
105 | dv_store_4 (dest, value); | |
106 | ||
107 | return nr_bytes; | |
108 | } | |
109 | ||
110 | static void | |
111 | attach_bfin_jtag_regs (struct hw *me, struct bfin_jtag *jtag) | |
112 | { | |
113 | address_word attach_address; | |
114 | int attach_space; | |
115 | unsigned attach_size; | |
116 | reg_property_spec reg; | |
117 | ||
118 | if (hw_find_property (me, "reg") == NULL) | |
119 | hw_abort (me, "Missing \"reg\" property"); | |
120 | ||
121 | if (!hw_find_reg_array_property (me, "reg", 0, ®)) | |
122 | hw_abort (me, "\"reg\" property must contain three addr/size entries"); | |
123 | ||
124 | hw_unit_address_to_attach_address (hw_parent (me), | |
125 | ®.address, | |
126 | &attach_space, &attach_address, me); | |
127 | hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); | |
128 | ||
129 | if (attach_size != BFIN_COREMMR_JTAG_SIZE) | |
130 | hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_JTAG_SIZE); | |
131 | ||
132 | hw_attach_address (hw_parent (me), | |
133 | 0, attach_space, attach_address, attach_size, me); | |
134 | ||
135 | jtag->base = attach_address; | |
136 | } | |
137 | ||
138 | static void | |
139 | bfin_jtag_finish (struct hw *me) | |
140 | { | |
141 | struct bfin_jtag *jtag; | |
142 | ||
143 | jtag = HW_ZALLOC (me, struct bfin_jtag); | |
144 | ||
145 | set_hw_data (me, jtag); | |
146 | set_hw_io_read_buffer (me, bfin_jtag_io_read_buffer); | |
147 | set_hw_io_write_buffer (me, bfin_jtag_io_write_buffer); | |
148 | ||
149 | attach_bfin_jtag_regs (me, jtag); | |
150 | ||
151 | /* Initialize the JTAG state. */ | |
152 | jtag->dspid = bfin_model_get_dspid (hw_system (me)); | |
153 | } | |
154 | ||
81d126c3 MF |
155 | const struct hw_descriptor dv_bfin_jtag_descriptor[] = |
156 | { | |
ef016f83 MF |
157 | {"bfin_jtag", bfin_jtag_finish,}, |
158 | {NULL, NULL}, | |
159 | }; |