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ef016f83 MF |
1 | /* Blackfin Trace (TBUF) model. |
2 | ||
3 | Copyright (C) 2010-2011 Free Software Foundation, Inc. | |
4 | Contributed by Analog Devices, Inc. | |
5 | ||
6 | This file is part of simulators. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | ||
23 | #include "sim-main.h" | |
24 | #include "devices.h" | |
25 | #include "dv-bfin_cec.h" | |
26 | #include "dv-bfin_trace.h" | |
27 | ||
28 | /* Note: The circular buffering here might look a little buggy wrt mid-reads | |
29 | and consuming the top entry, but this is simulating hardware behavior. | |
30 | The hardware is simple, dumb, and fast. Don't write dumb Blackfin | |
31 | software and you won't have a problem. */ | |
32 | ||
33 | /* The hardware is limited to 16 entries and defines TBUFCTL. Let's extend it ;). */ | |
34 | #ifndef SIM_BFIN_TRACE_DEPTH | |
35 | #define SIM_BFIN_TRACE_DEPTH 6 | |
36 | #endif | |
37 | #define SIM_BFIN_TRACE_LEN (1 << SIM_BFIN_TRACE_DEPTH) | |
38 | #define SIM_BFIN_TRACE_LEN_MASK (SIM_BFIN_TRACE_LEN - 1) | |
39 | ||
40 | struct bfin_trace_entry | |
41 | { | |
42 | bu32 src, dst; | |
43 | }; | |
44 | struct bfin_trace | |
45 | { | |
46 | bu32 base; | |
47 | struct bfin_trace_entry buffer[SIM_BFIN_TRACE_LEN]; | |
48 | int top, bottom; | |
49 | bool mid; | |
50 | ||
51 | /* Order after here is important -- matches hardware MMR layout. */ | |
52 | bu32 tbufctl, tbufstat; | |
53 | char _pad[0x100 - 0x8]; | |
54 | bu32 tbuf; | |
55 | }; | |
56 | #define mmr_base() offsetof(struct bfin_trace, tbufctl) | |
57 | #define mmr_offset(mmr) (offsetof(struct bfin_trace, mmr) - mmr_base()) | |
58 | ||
59 | static const char * const mmr_names[] = { | |
60 | "TBUFCTL", "TBUFSTAT", [mmr_offset (tbuf) / 4] = "TBUF", | |
61 | }; | |
62 | #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>") | |
63 | ||
64 | /* Ugh, circular buffers. */ | |
65 | #define TBUF_LEN(t) ((t)->top - (t)->bottom) | |
66 | #define TBUF_IDX(i) ((i) & SIM_BFIN_TRACE_LEN_MASK) | |
67 | /* TOP is the next slot to fill. */ | |
68 | #define TBUF_TOP(t) (&(t)->buffer[TBUF_IDX ((t)->top)]) | |
69 | /* LAST is the latest valid slot. */ | |
70 | #define TBUF_LAST(t) (&(t)->buffer[TBUF_IDX ((t)->top - 1)]) | |
71 | /* LAST_LAST is the second-to-last valid slot. */ | |
72 | #define TBUF_LAST_LAST(t) (&(t)->buffer[TBUF_IDX ((t)->top - 2)]) | |
73 | ||
74 | static unsigned | |
75 | bfin_trace_io_write_buffer (struct hw *me, const void *source, | |
76 | int space, address_word addr, unsigned nr_bytes) | |
77 | { | |
78 | struct bfin_trace *trace = hw_data (me); | |
79 | bu32 mmr_off; | |
80 | bu32 value; | |
81 | ||
82 | value = dv_load_4 (source); | |
83 | mmr_off = addr - trace->base; | |
84 | ||
85 | HW_TRACE_WRITE (); | |
86 | ||
87 | switch (mmr_off) | |
88 | { | |
89 | case mmr_offset(tbufctl): | |
90 | trace->tbufctl = value; | |
91 | break; | |
92 | case mmr_offset(tbufstat): | |
93 | case mmr_offset(tbuf): | |
94 | /* Discard writes to these. */ | |
95 | break; | |
96 | default: | |
97 | dv_bfin_mmr_invalid (me, addr, nr_bytes, true); | |
98 | break; | |
99 | } | |
100 | ||
101 | return nr_bytes; | |
102 | } | |
103 | ||
104 | static unsigned | |
105 | bfin_trace_io_read_buffer (struct hw *me, void *dest, | |
106 | int space, address_word addr, unsigned nr_bytes) | |
107 | { | |
108 | struct bfin_trace *trace = hw_data (me); | |
109 | bu32 mmr_off; | |
110 | bu32 value; | |
111 | ||
112 | mmr_off = addr - trace->base; | |
113 | ||
114 | HW_TRACE_READ (); | |
115 | ||
116 | switch (mmr_off) | |
117 | { | |
118 | case mmr_offset(tbufctl): | |
119 | value = trace->tbufctl; | |
120 | break; | |
121 | case mmr_offset(tbufstat): | |
122 | /* Hardware is limited to 16 entries, so to stay compatible with | |
123 | software, limit the value to 16. For software algorithms that | |
124 | keep reading while (TBUFSTAT != 0), they'll get all of it. */ | |
125 | value = MIN (TBUF_LEN (trace), 16); | |
126 | break; | |
127 | case mmr_offset(tbuf): | |
128 | { | |
129 | struct bfin_trace_entry *e; | |
130 | ||
131 | if (TBUF_LEN (trace) == 0) | |
132 | { | |
133 | value = 0; | |
134 | break; | |
135 | } | |
136 | ||
137 | e = TBUF_LAST (trace); | |
138 | if (trace->mid) | |
139 | { | |
140 | value = e->src; | |
141 | --trace->top; | |
142 | } | |
143 | else | |
144 | value = e->dst; | |
145 | trace->mid = !trace->mid; | |
146 | ||
147 | break; | |
148 | } | |
149 | default: | |
150 | while (1) /* Core MMRs -> exception -> doesn't return. */ | |
151 | dv_bfin_mmr_invalid (me, addr, nr_bytes, false); | |
152 | break; | |
153 | } | |
154 | ||
155 | dv_store_4 (dest, value); | |
156 | ||
157 | return nr_bytes; | |
158 | } | |
159 | ||
160 | static void | |
161 | attach_bfin_trace_regs (struct hw *me, struct bfin_trace *trace) | |
162 | { | |
163 | address_word attach_address; | |
164 | int attach_space; | |
165 | unsigned attach_size; | |
166 | reg_property_spec reg; | |
167 | ||
168 | if (hw_find_property (me, "reg") == NULL) | |
169 | hw_abort (me, "Missing \"reg\" property"); | |
170 | ||
171 | if (!hw_find_reg_array_property (me, "reg", 0, ®)) | |
172 | hw_abort (me, "\"reg\" property must contain three addr/size entries"); | |
173 | ||
174 | hw_unit_address_to_attach_address (hw_parent (me), | |
175 | ®.address, | |
176 | &attach_space, &attach_address, me); | |
177 | hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); | |
178 | ||
179 | if (attach_size != BFIN_COREMMR_TRACE_SIZE) | |
180 | hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_TRACE_SIZE); | |
181 | ||
182 | hw_attach_address (hw_parent (me), | |
183 | 0, attach_space, attach_address, attach_size, me); | |
184 | ||
185 | trace->base = attach_address; | |
186 | } | |
187 | ||
188 | static void | |
189 | bfin_trace_finish (struct hw *me) | |
190 | { | |
191 | struct bfin_trace *trace; | |
192 | ||
193 | trace = HW_ZALLOC (me, struct bfin_trace); | |
194 | ||
195 | set_hw_data (me, trace); | |
196 | set_hw_io_read_buffer (me, bfin_trace_io_read_buffer); | |
197 | set_hw_io_write_buffer (me, bfin_trace_io_write_buffer); | |
198 | ||
199 | attach_bfin_trace_regs (me, trace); | |
200 | } | |
201 | ||
202 | const struct hw_descriptor dv_bfin_trace_descriptor[] = { | |
203 | {"bfin_trace", bfin_trace_finish,}, | |
204 | {NULL, NULL}, | |
205 | }; | |
206 | ||
207 | #define TRACE_STATE(cpu) DV_STATE_CACHED (cpu, trace) | |
208 | ||
209 | /* This is not re-entrant, but neither is the cpu state, so this shouldn't | |
210 | be a big deal ... */ | |
211 | void bfin_trace_queue (SIM_CPU *cpu, bu32 src_pc, bu32 dst_pc, int hwloop) | |
212 | { | |
213 | struct bfin_trace *trace = TRACE_STATE (cpu); | |
214 | struct bfin_trace_entry *e; | |
215 | int len, ivg; | |
216 | ||
217 | /* Only queue if powered. */ | |
218 | if (!(trace->tbufctl & TBUFPWR)) | |
219 | return; | |
220 | ||
221 | /* Only queue if enabled. */ | |
222 | if (!(trace->tbufctl & TBUFEN)) | |
223 | return; | |
224 | ||
225 | /* Ignore hardware loops. | |
226 | XXX: This is what the hardware does, but an option to ignore | |
227 | could be useful for debugging ... */ | |
228 | if (hwloop >= 0) | |
229 | return; | |
230 | ||
231 | /* Only queue if at right level. */ | |
232 | ivg = cec_get_ivg (cpu); | |
233 | if (ivg == IVG_RST) | |
234 | /* XXX: This is what the hardware does, but an option to ignore | |
235 | could be useful for debugging ... */ | |
236 | return; | |
237 | if (ivg <= IVG_EVX && (trace->tbufctl & TBUFOVF)) | |
238 | /* XXX: This is what the hardware does, but an option to ignore | |
239 | could be useful for debugging ... just don't throw an | |
240 | exception when full and in EVT{0..3}. */ | |
241 | return; | |
242 | ||
243 | /* Are we full ? */ | |
244 | len = TBUF_LEN (trace); | |
245 | if (len == SIM_BFIN_TRACE_LEN) | |
246 | { | |
247 | if (trace->tbufctl & TBUFOVF) | |
248 | { | |
249 | cec_exception (cpu, VEC_OVFLOW); | |
250 | return; | |
251 | } | |
252 | ||
253 | /* Overwrite next entry. */ | |
254 | ++trace->bottom; | |
255 | } | |
256 | ||
257 | /* One level compression. */ | |
258 | if (len >= 1 && (trace->tbufctl & TBUFCMPLP)) | |
259 | { | |
260 | e = TBUF_LAST (trace); | |
261 | if (src_pc == (e->src & ~1) && dst_pc == (e->dst & ~1)) | |
262 | { | |
263 | /* Hardware sets LSB when level is compressed. */ | |
264 | e->dst |= 1; | |
265 | return; | |
266 | } | |
267 | } | |
268 | ||
269 | /* Two level compression. */ | |
270 | if (len >= 2 && (trace->tbufctl & TBUFCMPLP_DOUBLE)) | |
271 | { | |
272 | e = TBUF_LAST_LAST (trace); | |
273 | if (src_pc == (e->src & ~1) && dst_pc == (e->dst & ~1)) | |
274 | { | |
275 | /* Hardware sets LSB when level is compressed. */ | |
276 | e->src |= 1; | |
277 | return; | |
278 | } | |
279 | } | |
280 | ||
281 | e = TBUF_TOP (trace); | |
282 | e->dst = dst_pc; | |
283 | e->src = src_pc; | |
284 | ++trace->top; | |
285 | } |