[deliverable/binutils-gdb.git] / sim / bfin / dv-bfin_uart2.c

/* Blackfin Universal Asynchronous Receiver/Transmitter (UART) model.
   For "new style" UARTs on BF50x/BF54x parts.

   Copyright (C) 2010-2011 Free Software Foundation, Inc.
   Contributed by Analog Devices, Inc.

   This file is part of simulators.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#include "config.h"

#include "sim-main.h"
#include "devices.h"
#include "dv-bfin_uart2.h"

/* XXX: Should we bother emulating the TX/RX FIFOs ?  */

/* Internal state needs to be the same as bfin_uart.  */
struct bfin_uart
{
  /* This top portion matches common dv_bfin struct.  */
  bu32 base;
  struct hw *dma_master;
  bool acked;

  struct hw_event *handler;
  char saved_byte;
  int saved_count;

  /* Accessed indirectly by ier_{set,clear}.  */
  bu16 ier;

  /* Order after here is important -- matches hardware MMR layout.  */
  bu16 BFIN_MMR_16(dll);
  bu16 BFIN_MMR_16(dlh);
  bu16 BFIN_MMR_16(gctl);
  bu16 BFIN_MMR_16(lcr);
  bu16 BFIN_MMR_16(mcr);
  bu16 BFIN_MMR_16(lsr);
  bu16 BFIN_MMR_16(msr);
  bu16 BFIN_MMR_16(scr);
  bu16 BFIN_MMR_16(ier_set);
  bu16 BFIN_MMR_16(ier_clear);
  bu16 BFIN_MMR_16(thr);
  bu16 BFIN_MMR_16(rbr);
};
#define mmr_base()      offsetof(struct bfin_uart, dll)
#define mmr_offset(mmr) (offsetof(struct bfin_uart, mmr) - mmr_base())

static const char * const mmr_names[] =
{
  "UART_DLL", "UART_DLH", "UART_GCTL", "UART_LCR", "UART_MCR", "UART_LSR",
  "UART_MSR", "UART_SCR", "UART_IER_SET", "UART_IER_CLEAR", "UART_THR",
  "UART_RBR",
};
#define mmr_name(off) mmr_names[(off) / 4]

static unsigned
bfin_uart_io_write_buffer (struct hw *me, const void *source,
			   int space, address_word addr, unsigned nr_bytes)
{
  struct bfin_uart *uart = hw_data (me);
  bu32 mmr_off;
  bu32 value;
  bu16 *valuep;

  value = dv_load_2 (source);
  mmr_off = addr - uart->base;
  valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off);

  HW_TRACE_WRITE ();

  dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);

  /* XXX: All MMRs are "8bit" ... what happens to high 8bits ?  */

  switch (mmr_off)
    {
    case mmr_offset(thr):
      uart->thr = bfin_uart_write_byte (me, value);
      if (uart->ier & ETBEI)
	hw_port_event (me, DV_PORT_TX, 1);
      break;
    case mmr_offset(ier_set):
      uart->ier |= value;
      break;
    case mmr_offset(ier_clear):
      dv_w1c_2 (&uart->ier, value, -1);
      break;
    case mmr_offset(lsr):
      dv_w1c_2 (valuep, value, TFI | BI | FE | PE | OE);
      break;
    case mmr_offset(rbr):
      /* XXX: Writes are ignored ?  */
      break;
    case mmr_offset(msr):
      dv_w1c_2 (valuep, value, SCTS);
      break;
    case mmr_offset(dll):
    case mmr_offset(dlh):
    case mmr_offset(gctl):
    case mmr_offset(lcr):
    case mmr_offset(mcr):
    case mmr_offset(scr):
      *valuep = value;
      break;
    default:
      dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
      break;
    }

  return nr_bytes;
}

static unsigned
bfin_uart_io_read_buffer (struct hw *me, void *dest,
			  int space, address_word addr, unsigned nr_bytes)
{
  struct bfin_uart *uart = hw_data (me);
  bu32 mmr_off;
  bu16 *valuep;

  mmr_off = addr - uart->base;
  valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off);

  HW_TRACE_READ ();

  dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);

  switch (mmr_off)
    {
    case mmr_offset(rbr):
      uart->rbr = bfin_uart_get_next_byte (me, uart->rbr, NULL);
      dv_store_2 (dest, uart->rbr);
      break;
    case mmr_offset(ier_set):
    case mmr_offset(ier_clear):
      dv_store_2 (dest, uart->ier);
      bfin_uart_reschedule (me);
      break;
    case mmr_offset(lsr):
      uart->lsr &= ~(DR | THRE | TEMT);
      uart->lsr |= bfin_uart_get_status (me);
    case mmr_offset(thr):
    case mmr_offset(msr):
    case mmr_offset(dll):
    case mmr_offset(dlh):
    case mmr_offset(gctl):
    case mmr_offset(lcr):
    case mmr_offset(mcr):
    case mmr_offset(scr):
      dv_store_2 (dest, *valuep);
      break;
    default:
      dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
      break;
    }

  return nr_bytes;
}

static unsigned
bfin_uart_dma_read_buffer (struct hw *me, void *dest, int space,
			   unsigned_word addr, unsigned nr_bytes)
{
  HW_TRACE_DMA_READ ();
  return bfin_uart_read_buffer (me, dest, nr_bytes);
}

static unsigned
bfin_uart_dma_write_buffer (struct hw *me, const void *source,
			    int space, unsigned_word addr,
			    unsigned nr_bytes,
			    int violate_read_only_section)
{
  struct bfin_uart *uart = hw_data (me);
  unsigned ret;

  HW_TRACE_DMA_WRITE ();

  ret = bfin_uart_write_buffer (me, source, nr_bytes);

  if (ret == nr_bytes && (uart->ier & ETBEI))
    hw_port_event (me, DV_PORT_TX, 1);

  return ret;
}

static const struct hw_port_descriptor bfin_uart_ports[] =
{
  { "tx",   DV_PORT_TX,   0, output_port, },
  { "rx",   DV_PORT_RX,   0, output_port, },
  { "stat", DV_PORT_STAT, 0, output_port, },
  { NULL, 0, 0, 0, },
};

static void
attach_bfin_uart_regs (struct hw *me, struct bfin_uart *uart)
{
  address_word attach_address;
  int attach_space;
  unsigned attach_size;
  reg_property_spec reg;

  if (hw_find_property (me, "reg") == NULL)
    hw_abort (me, "Missing \"reg\" property");

  if (!hw_find_reg_array_property (me, "reg", 0, &reg))
    hw_abort (me, "\"reg\" property must contain three addr/size entries");

  hw_unit_address_to_attach_address (hw_parent (me),
				     &reg.address,
				     &attach_space, &attach_address, me);
  hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);

  if (attach_size != BFIN_MMR_UART2_SIZE)
    hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_UART2_SIZE);

  hw_attach_address (hw_parent (me),
		     0, attach_space, attach_address, attach_size, me);

  uart->base = attach_address;
}

static void
bfin_uart_finish (struct hw *me)
{
  struct bfin_uart *uart;

  uart = HW_ZALLOC (me, struct bfin_uart);

  set_hw_data (me, uart);
  set_hw_io_read_buffer (me, bfin_uart_io_read_buffer);
  set_hw_io_write_buffer (me, bfin_uart_io_write_buffer);
  set_hw_dma_read_buffer (me, bfin_uart_dma_read_buffer);
  set_hw_dma_write_buffer (me, bfin_uart_dma_write_buffer);
  set_hw_ports (me, bfin_uart_ports);

  attach_bfin_uart_regs (me, uart);

  /* Initialize the UART.  */
  uart->dll = 0x0001;
  uart->lsr = 0x0060;
}

const struct hw_descriptor dv_bfin_uart2_descriptor[] =
{
  {"bfin_uart2", bfin_uart_finish,},
  {NULL, NULL},
};
Commit	Line	Data
ef016f83 MF	1	/* Blackfin Universal Asynchronous Receiver/Transmitter (UART) model.
	2	For "new style" UARTs on BF50x/BF54x parts.
	3
	4	Copyright (C) 2010-2011 Free Software Foundation, Inc.
	5	Contributed by Analog Devices, Inc.
	6
	7	This file is part of simulators.
	8
	9	This program is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation; either version 3 of the License, or
	12	(at your option) any later version.
	13
	14	This program is distributed in the hope that it will be useful,
	15	but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License
	20	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	21
	22	#include "config.h"
	23
	24	#include "sim-main.h"
	25	#include "devices.h"
	26	#include "dv-bfin_uart2.h"
	27
	28	/* XXX: Should we bother emulating the TX/RX FIFOs ? */
	29
	30	/* Internal state needs to be the same as bfin_uart. */
	31	struct bfin_uart
	32	{
	33	/* This top portion matches common dv_bfin struct. */
	34	bu32 base;
	35	struct hw *dma_master;
	36	bool acked;
	37
	38	struct hw_event *handler;
	39	char saved_byte;
	40	int saved_count;
	41
	42	/* Accessed indirectly by ier_{set,clear}. */
	43	bu16 ier;
	44
	45	/* Order after here is important -- matches hardware MMR layout. */
	46	bu16 BFIN_MMR_16(dll);
	47	bu16 BFIN_MMR_16(dlh);
	48	bu16 BFIN_MMR_16(gctl);
	49	bu16 BFIN_MMR_16(lcr);
	50	bu16 BFIN_MMR_16(mcr);
	51	bu16 BFIN_MMR_16(lsr);
	52	bu16 BFIN_MMR_16(msr);
	53	bu16 BFIN_MMR_16(scr);
	54	bu16 BFIN_MMR_16(ier_set);
	55	bu16 BFIN_MMR_16(ier_clear);
	56	bu16 BFIN_MMR_16(thr);
	57	bu16 BFIN_MMR_16(rbr);
	58	};
	59	#define mmr_base() offsetof(struct bfin_uart, dll)
	60	#define mmr_offset(mmr) (offsetof(struct bfin_uart, mmr) - mmr_base())
	61
990d19fd MF	62	static const char * const mmr_names[] =
990d19fd MF	63	{
ef016f83 MF	64	"UART_DLL", "UART_DLH", "UART_GCTL", "UART_LCR", "UART_MCR", "UART_LSR",
	65	"UART_MSR", "UART_SCR", "UART_IER_SET", "UART_IER_CLEAR", "UART_THR",
	66	"UART_RBR",
	67	};
	68	#define mmr_name(off) mmr_names[(off) / 4]
	69
	70	static unsigned
	71	bfin_uart_io_write_buffer (struct hw me, const void source,
	72	int space, address_word addr, unsigned nr_bytes)
	73	{
	74	struct bfin_uart *uart = hw_data (me);
	75	bu32 mmr_off;
	76	bu32 value;
	77	bu16 *valuep;
	78
	79	value = dv_load_2 (source);
	80	mmr_off = addr - uart->base;
	81	valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off);
	82
	83	HW_TRACE_WRITE ();
	84
	85	dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
	86
	87	/* XXX: All MMRs are "8bit" ... what happens to high 8bits ? */
	88
	89	switch (mmr_off)
	90	{
	91	case mmr_offset(thr):
	92	uart->thr = bfin_uart_write_byte (me, value);
	93	if (uart->ier & ETBEI)
	94	hw_port_event (me, DV_PORT_TX, 1);
	95	break;
	96	case mmr_offset(ier_set):
	97	uart->ier \|= value;
	98	break;
	99	case mmr_offset(ier_clear):
9922f803	100	dv_w1c_2 (&uart->ier, value, -1);
ef016f83 MF	101	break;
ef016f83 MF	102	case mmr_offset(lsr):
9922f803	103	dv_w1c_2 (valuep, value, TFI \| BI \| FE \| PE \| OE);
ef016f83 MF	104	break;
	105	case mmr_offset(rbr):
	106	/* XXX: Writes are ignored ? */
	107	break;
	108	case mmr_offset(msr):
	109	dv_w1c_2 (valuep, value, SCTS);
	110	break;
	111	case mmr_offset(dll):
	112	case mmr_offset(dlh):
	113	case mmr_offset(gctl):
	114	case mmr_offset(lcr):
	115	case mmr_offset(mcr):
	116	case mmr_offset(scr):
	117	*valuep = value;
	118	break;
	119	default:
	120	dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
	121	break;
	122	}
	123
	124	return nr_bytes;
	125	}
	126
	127	static unsigned
	128	bfin_uart_io_read_buffer (struct hw me, void dest,
	129	int space, address_word addr, unsigned nr_bytes)
	130	{
	131	struct bfin_uart *uart = hw_data (me);
	132	bu32 mmr_off;
	133	bu16 *valuep;
	134
	135	mmr_off = addr - uart->base;
	136	valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off);
	137
	138	HW_TRACE_READ ();
	139
	140	dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
	141
	142	switch (mmr_off)
	143	{
	144	case mmr_offset(rbr):
	145	uart->rbr = bfin_uart_get_next_byte (me, uart->rbr, NULL);
	146	dv_store_2 (dest, uart->rbr);
	147	break;
	148	case mmr_offset(ier_set):
	149	case mmr_offset(ier_clear):
	150	dv_store_2 (dest, uart->ier);
	151	bfin_uart_reschedule (me);
	152	break;
	153	case mmr_offset(lsr):
b44f3f63	154	uart->lsr &= ~(DR \| THRE \| TEMT);
ef016f83 MF	155	uart->lsr \|= bfin_uart_get_status (me);
	156	case mmr_offset(thr):
	157	case mmr_offset(msr):
	158	case mmr_offset(dll):
	159	case mmr_offset(dlh):
	160	case mmr_offset(gctl):
	161	case mmr_offset(lcr):
	162	case mmr_offset(mcr):
	163	case mmr_offset(scr):
	164	dv_store_2 (dest, *valuep);
	165	break;
	166	default:
	167	dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
	168	break;
	169	}
	170
	171	return nr_bytes;
	172	}
	173
	174	static unsigned
	175	bfin_uart_dma_read_buffer (struct hw me, void dest, int space,
	176	unsigned_word addr, unsigned nr_bytes)
	177	{
	178	HW_TRACE_DMA_READ ();
	179	return bfin_uart_read_buffer (me, dest, nr_bytes);
	180	}
	181
	182	static unsigned
	183	bfin_uart_dma_write_buffer (struct hw me, const void source,
	184	int space, unsigned_word addr,
	185	unsigned nr_bytes,
	186	int violate_read_only_section)
	187	{
	188	struct bfin_uart *uart = hw_data (me);
	189	unsigned ret;
	190
	191	HW_TRACE_DMA_WRITE ();
	192
	193	ret = bfin_uart_write_buffer (me, source, nr_bytes);
	194
	195	if (ret == nr_bytes && (uart->ier & ETBEI))
	196	hw_port_event (me, DV_PORT_TX, 1);
	197
	198	return ret;
	199	}
	200
990d19fd MF	201	static const struct hw_port_descriptor bfin_uart_ports[] =
990d19fd MF	202	{
ef016f83 MF	203	{ "tx", DV_PORT_TX, 0, output_port, },
	204	{ "rx", DV_PORT_RX, 0, output_port, },
	205	{ "stat", DV_PORT_STAT, 0, output_port, },
	206	{ NULL, 0, 0, 0, },
	207	};
	208
	209	static void
	210	attach_bfin_uart_regs (struct hw me, struct bfin_uart uart)
	211	{
	212	address_word attach_address;
	213	int attach_space;
	214	unsigned attach_size;
	215	reg_property_spec reg;
	216
	217	if (hw_find_property (me, "reg") == NULL)
	218	hw_abort (me, "Missing \"reg\" property");
	219
	220	if (!hw_find_reg_array_property (me, "reg", 0, &reg))
	221	hw_abort (me, "\"reg\" property must contain three addr/size entries");
	222
	223	hw_unit_address_to_attach_address (hw_parent (me),
	224	&reg.address,
	225	&attach_space, &attach_address, me);
	226	hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
	227
	228	if (attach_size != BFIN_MMR_UART2_SIZE)
	229	hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_UART2_SIZE);
	230
	231	hw_attach_address (hw_parent (me),
	232	0, attach_space, attach_address, attach_size, me);
	233
	234	uart->base = attach_address;
	235	}
	236
	237	static void
	238	bfin_uart_finish (struct hw *me)
	239	{
	240	struct bfin_uart *uart;
	241
	242	uart = HW_ZALLOC (me, struct bfin_uart);
	243
	244	set_hw_data (me, uart);
	245	set_hw_io_read_buffer (me, bfin_uart_io_read_buffer);
	246	set_hw_io_write_buffer (me, bfin_uart_io_write_buffer);
	247	set_hw_dma_read_buffer (me, bfin_uart_dma_read_buffer);
	248	set_hw_dma_write_buffer (me, bfin_uart_dma_write_buffer);
	249	set_hw_ports (me, bfin_uart_ports);
	250
	251	attach_bfin_uart_regs (me, uart);
	252
	253	/* Initialize the UART. */
	254	uart->dll = 0x0001;
	255	uart->lsr = 0x0060;
	256	}
	257
81d126c3 MF	258	const struct hw_descriptor dv_bfin_uart2_descriptor[] =
81d126c3 MF	259	{
ef016f83 MF	260	{"bfin_uart2", bfin_uart_finish,},
	261	{NULL, NULL},
	262	};