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ef016f83 MF |
1 | /* Blackfin Watchpoint (WP) model. |
2 | ||
618f726f | 3 | Copyright (C) 2010-2016 Free Software Foundation, Inc. |
ef016f83 MF |
4 | Contributed by Analog Devices, Inc. |
5 | ||
6 | This file is part of simulators. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "config.h" | |
22 | ||
23 | #include "sim-main.h" | |
24 | #include "devices.h" | |
25 | #include "dv-bfin_wp.h" | |
26 | ||
27 | /* XXX: This is mostly a stub. */ | |
28 | ||
29 | #define WPI_NUM 6 /* 6 instruction watchpoints. */ | |
30 | #define WPD_NUM 2 /* 2 data watchpoints. */ | |
31 | ||
32 | struct bfin_wp | |
33 | { | |
34 | bu32 base; | |
35 | ||
36 | /* Order after here is important -- matches hardware MMR layout. */ | |
37 | bu32 iactl; | |
38 | bu32 _pad0[15]; | |
39 | bu32 ia[WPI_NUM]; | |
40 | bu32 _pad1[16 - WPI_NUM]; | |
41 | bu32 iacnt[WPI_NUM]; | |
42 | bu32 _pad2[32 - WPI_NUM]; | |
43 | ||
44 | bu32 dactl; | |
45 | bu32 _pad3[15]; | |
46 | bu32 da[WPD_NUM]; | |
47 | bu32 _pad4[16 - WPD_NUM]; | |
48 | bu32 dacnt[WPD_NUM]; | |
49 | bu32 _pad5[32 - WPD_NUM]; | |
50 | ||
51 | bu32 stat; | |
52 | }; | |
53 | #define mmr_base() offsetof(struct bfin_wp, iactl) | |
54 | #define mmr_offset(mmr) (offsetof(struct bfin_wp, mmr) - mmr_base()) | |
55 | #define mmr_idx(mmr) (mmr_offset (mmr) / 4) | |
56 | ||
990d19fd MF |
57 | static const char * const mmr_names[] = |
58 | { | |
ef016f83 MF |
59 | [mmr_idx (iactl)] = "WPIACTL", |
60 | [mmr_idx (ia)] = "WPIA0", "WPIA1", "WPIA2", "WPIA3", "WPIA4", "WPIA5", | |
61 | [mmr_idx (iacnt)] = "WPIACNT0", "WPIACNT1", "WPIACNT2", | |
62 | "WPIACNT3", "WPIACNT4", "WPIACNT5", | |
63 | [mmr_idx (dactl)] = "WPDACTL", | |
64 | [mmr_idx (da)] = "WPDA0", "WPDA1", "WPDA2", "WPDA3", "WPDA4", "WPDA5", | |
65 | [mmr_idx (dacnt)] = "WPDACNT0", "WPDACNT1", "WPDACNT2", | |
66 | "WPDACNT3", "WPDACNT4", "WPDACNT5", | |
67 | [mmr_idx (stat)] = "WPSTAT", | |
68 | }; | |
69 | #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>") | |
70 | ||
71 | static unsigned | |
72 | bfin_wp_io_write_buffer (struct hw *me, const void *source, int space, | |
73 | address_word addr, unsigned nr_bytes) | |
74 | { | |
75 | struct bfin_wp *wp = hw_data (me); | |
76 | bu32 mmr_off; | |
77 | bu32 value; | |
78 | bu32 *valuep; | |
79 | ||
466b619e MF |
80 | /* Invalid access mode is higher priority than missing register. */ |
81 | if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true)) | |
82 | return 0; | |
83 | ||
ef016f83 MF |
84 | value = dv_load_4 (source); |
85 | mmr_off = addr - wp->base; | |
86 | valuep = (void *)((unsigned long)wp + mmr_base() + mmr_off); | |
87 | ||
88 | HW_TRACE_WRITE (); | |
89 | ||
90 | switch (mmr_off) | |
91 | { | |
92 | case mmr_offset(iactl): | |
93 | case mmr_offset(ia[0]) ... mmr_offset(ia[WPI_NUM - 1]): | |
94 | case mmr_offset(iacnt[0]) ... mmr_offset(iacnt[WPI_NUM - 1]): | |
95 | case mmr_offset(dactl): | |
96 | case mmr_offset(da[0]) ... mmr_offset(da[WPD_NUM - 1]): | |
97 | case mmr_offset(dacnt[0]) ... mmr_offset(dacnt[WPD_NUM - 1]): | |
98 | *valuep = value; | |
99 | break; | |
100 | case mmr_offset(stat): | |
101 | /* Yes, the hardware is this dumb -- clear all bits on any write. */ | |
102 | *valuep = 0; | |
103 | break; | |
104 | default: | |
105 | dv_bfin_mmr_invalid (me, addr, nr_bytes, true); | |
466b619e | 106 | return 0; |
ef016f83 MF |
107 | } |
108 | ||
109 | return nr_bytes; | |
110 | } | |
111 | ||
112 | static unsigned | |
113 | bfin_wp_io_read_buffer (struct hw *me, void *dest, int space, | |
114 | address_word addr, unsigned nr_bytes) | |
115 | { | |
116 | struct bfin_wp *wp = hw_data (me); | |
117 | bu32 mmr_off; | |
118 | bu32 value; | |
119 | bu32 *valuep; | |
120 | ||
466b619e MF |
121 | /* Invalid access mode is higher priority than missing register. */ |
122 | if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false)) | |
123 | return 0; | |
124 | ||
ef016f83 MF |
125 | mmr_off = addr - wp->base; |
126 | valuep = (void *)((unsigned long)wp + mmr_base() + mmr_off); | |
127 | ||
128 | HW_TRACE_READ (); | |
129 | ||
130 | switch (mmr_off) | |
131 | { | |
132 | case mmr_offset(iactl): | |
133 | case mmr_offset(ia[0]) ... mmr_offset(ia[WPI_NUM - 1]): | |
134 | case mmr_offset(iacnt[0]) ... mmr_offset(iacnt[WPI_NUM - 1]): | |
135 | case mmr_offset(dactl): | |
136 | case mmr_offset(da[0]) ... mmr_offset(da[WPD_NUM - 1]): | |
137 | case mmr_offset(dacnt[0]) ... mmr_offset(dacnt[WPD_NUM - 1]): | |
138 | case mmr_offset(stat): | |
139 | value = *valuep; | |
140 | break; | |
141 | default: | |
466b619e MF |
142 | dv_bfin_mmr_invalid (me, addr, nr_bytes, false); |
143 | return 0; | |
ef016f83 MF |
144 | } |
145 | ||
146 | dv_store_4 (dest, value); | |
147 | ||
148 | return nr_bytes; | |
149 | } | |
150 | ||
151 | static void | |
152 | attach_bfin_wp_regs (struct hw *me, struct bfin_wp *wp) | |
153 | { | |
154 | address_word attach_address; | |
155 | int attach_space; | |
156 | unsigned attach_size; | |
157 | reg_property_spec reg; | |
158 | ||
159 | if (hw_find_property (me, "reg") == NULL) | |
160 | hw_abort (me, "Missing \"reg\" property"); | |
161 | ||
162 | if (!hw_find_reg_array_property (me, "reg", 0, ®)) | |
163 | hw_abort (me, "\"reg\" property must contain three addr/size entries"); | |
164 | ||
165 | hw_unit_address_to_attach_address (hw_parent (me), | |
166 | ®.address, | |
167 | &attach_space, &attach_address, me); | |
168 | hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); | |
169 | ||
170 | if (attach_size != BFIN_COREMMR_WP_SIZE) | |
171 | hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_WP_SIZE); | |
172 | ||
173 | hw_attach_address (hw_parent (me), | |
174 | 0, attach_space, attach_address, attach_size, me); | |
175 | ||
176 | wp->base = attach_address; | |
177 | } | |
178 | ||
179 | static void | |
180 | bfin_wp_finish (struct hw *me) | |
181 | { | |
182 | struct bfin_wp *wp; | |
183 | ||
184 | wp = HW_ZALLOC (me, struct bfin_wp); | |
185 | ||
186 | set_hw_data (me, wp); | |
187 | set_hw_io_read_buffer (me, bfin_wp_io_read_buffer); | |
188 | set_hw_io_write_buffer (me, bfin_wp_io_write_buffer); | |
189 | ||
190 | attach_bfin_wp_regs (me, wp); | |
191 | } | |
192 | ||
81d126c3 MF |
193 | const struct hw_descriptor dv_bfin_wp_descriptor[] = |
194 | { | |
ef016f83 MF |
195 | {"bfin_wp", bfin_wp_finish,}, |
196 | {NULL, NULL}, | |
197 | }; |