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sim: bfin: handle AZ updates with 16bit adds/subs
[deliverable/binutils-gdb.git] / sim / bfin / machs.c
CommitLineData
ef016f83
MF		 1/* Simulator for Analog Devices Blackfin processors.
2
3 Copyright (C) 2005-2011 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
5
6 This file is part of simulators.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "config.h"
22
23#include "sim-main.h"
24#include "gdb/sim-bfin.h"
25#include "bfd.h"
26
27#include "sim-hw.h"
28#include "devices.h"
29#include "dv-bfin_cec.h"
30#include "dv-bfin_ctimer.h"
31#include "dv-bfin_dma.h"
32#include "dv-bfin_dmac.h"
33#include "dv-bfin_ebiu_amc.h"
34#include "dv-bfin_ebiu_ddrc.h"
35#include "dv-bfin_ebiu_sdc.h"
36#include "dv-bfin_emac.h"
37#include "dv-bfin_eppi.h"
38#include "dv-bfin_evt.h"
39#include "dv-bfin_gptimer.h"
40#include "dv-bfin_jtag.h"
41#include "dv-bfin_mmu.h"
42#include "dv-bfin_nfc.h"
43#include "dv-bfin_otp.h"
44#include "dv-bfin_ppi.h"
45#include "dv-bfin_pll.h"
46#include "dv-bfin_rtc.h"
47#include "dv-bfin_sic.h"
48#include "dv-bfin_spi.h"
49#include "dv-bfin_trace.h"
50#include "dv-bfin_twi.h"
51#include "dv-bfin_uart.h"
52#include "dv-bfin_uart2.h"
53#include "dv-bfin_wdog.h"
54#include "dv-bfin_wp.h"
55
56static const MACH bfin_mach;
57
58struct bfin_memory_layout {
59 address_word addr, len;
60 unsigned mask; /* see mapmask in sim_core_attach() */
61};
62struct bfin_dev_layout {
63 address_word base, len;
64 unsigned int dmac;
65 const char *dev;
66};
67struct bfin_dmac_layout {
68 address_word base;
69 unsigned int dma_count;
70};
71struct bfin_model_data {
72 bu32 chipid;
73 int model_num;
74 const struct bfin_memory_layout *mem;
75 size_t mem_count;
76 const struct bfin_dev_layout *dev;
77 size_t dev_count;
78 const struct bfin_dmac_layout *dmac;
79 size_t dmac_count;
80};
81
82#define LAYOUT(_addr, _len, _mask) { .addr = _addr, .len = _len, .mask = access_##_mask, }
83#define _DEVICE(_base, _len, _dev, _dmac) { .base = _base, .len = _len, .dev = _dev, .dmac = _dmac, }
84#define DEVICE(_base, _len, _dev) _DEVICE(_base, _len, _dev, 0)
85
86/* [1] Common sim code can't model exec-only memory.
87 http://sourceware.org/ml/gdb/2010-02/msg00047.html */
88
89#define bf000_chipid 0
90static const struct bfin_memory_layout bf000_mem[] = {};
91static const struct bfin_dev_layout bf000_dev[] = {};
92static const struct bfin_dmac_layout bf000_dmac[] = {};
93
94#define bf50x_chipid 0x2800
95#define bf504_chipid bf50x_chipid
96#define bf506_chipid bf50x_chipid
97static const struct bfin_memory_layout bf50x_mem[] = {
98 LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
99 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
100 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
101 LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */
102 LAYOUT (0xFFC01700, 0x50, read_write), /* PORTH stub */
103 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
104 LAYOUT (0xFFC03800, 0x100, read_write), /* RSI stub */
105 LAYOUT (0xFFC0328C, 0xC, read_write), /* Flash stub */
106 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
107 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
108 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
109 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst Cache [1] */
110};
111#define bf504_mem bf50x_mem
112#define bf506_mem bf50x_mem
113static const struct bfin_dev_layout bf50x_dev[] = {
114 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
115 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
116 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
117 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
118 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
119 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
120 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
121 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
122 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
123 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
124 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
125 DEVICE (0xFFC00A00, BF50X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
126 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
127 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
128 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
129 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
130};
131#define bf504_dev bf50x_dev
132#define bf506_dev bf50x_dev
133static const struct bfin_dmac_layout bf50x_dmac[] = {
134 { BFIN_MMR_DMAC0_BASE, 12, },
135};
136#define bf504_dmac bf50x_dmac
137#define bf506_dmac bf50x_dmac
138
139#define bf51x_chipid 0x27e8
140#define bf512_chipid bf51x_chipid
141#define bf514_chipid bf51x_chipid
142#define bf516_chipid bf51x_chipid
143#define bf518_chipid bf51x_chipid
144static const struct bfin_memory_layout bf51x_mem[] = {
145 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
146 LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
147 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
148 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
149 LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */
150 LAYOUT (0xFFC01700, 0x50, read_write), /* PORTH stub */
151 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
152 LAYOUT (0xFFC03800, 0xD0, read_write), /* RSI stub */
153 LAYOUT (0xFFC03FE0, 0x20, read_write), /* RSI peripheral stub */
154 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
155 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
156 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
157 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
158 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
159 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
160};
161#define bf512_mem bf51x_mem
162#define bf514_mem bf51x_mem
163#define bf516_mem bf51x_mem
164#define bf518_mem bf51x_mem
165static const struct bfin_dev_layout bf512_dev[] = {
166 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
167 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
168 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
169 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
170 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
171 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
172 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
173 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
174 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
175 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
176 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
177 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
178 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
179 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
180 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
181 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
182 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
183 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
184 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
185};
186#define bf514_dev bf512_dev
187static const struct bfin_dev_layout bf516_dev[] = {
188 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
189 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
190 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
191 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
192 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
193 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
194 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
195 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
196 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
197 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
198 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
199 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
200 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
201 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
202 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
203 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
204 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
205 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
206 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
207 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
208 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
209};
210#define bf518_dev bf516_dev
211#define bf512_dmac bf50x_dmac
212#define bf514_dmac bf50x_dmac
213#define bf516_dmac bf50x_dmac
214#define bf518_dmac bf50x_dmac
215
216#define bf522_chipid 0x27e4
217#define bf523_chipid 0x27e0
218#define bf524_chipid bf522_chipid
219#define bf525_chipid bf523_chipid
220#define bf526_chipid bf522_chipid
221#define bf527_chipid bf523_chipid
222static const struct bfin_memory_layout bf52x_mem[] = {
223 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
224 LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
225 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
226 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
227 LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */
228 LAYOUT (0xFFC01700, 0x50, read_write), /* PORTH stub */
229 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
230 LAYOUT (0xFFC03800, 0x500, read_write), /* MUSB stub */
231 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
232 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
233 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
234 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
235 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
236 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
237 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
238};
239#define bf522_mem bf52x_mem
240#define bf523_mem bf52x_mem
241#define bf524_mem bf52x_mem
242#define bf525_mem bf52x_mem
243#define bf526_mem bf52x_mem
244#define bf527_mem bf52x_mem
245static const struct bfin_dev_layout bf522_dev[] = {
246 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
247 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
248 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
249 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
250 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
251 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
252 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
253 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
254 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
255 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
256 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
257 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
258 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
259 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
260 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
261 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
262 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
263 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
264 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
265};
266#define bf523_dev bf522_dev
267#define bf524_dev bf522_dev
268#define bf525_dev bf522_dev
269static const struct bfin_dev_layout bf526_dev[] = {
270 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
271 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
272 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
273 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
274 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
275 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
276 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
277 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
278 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
279 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
280 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
281 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
282 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
283 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
284 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
285 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
286 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
287 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
288 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
289 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
290 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
291};
292#define bf527_dev bf526_dev
293#define bf522_dmac bf50x_dmac
294#define bf523_dmac bf50x_dmac
295#define bf524_dmac bf50x_dmac
296#define bf525_dmac bf50x_dmac
297#define bf526_dmac bf50x_dmac
298#define bf527_dmac bf50x_dmac
299
300#define bf531_chipid 0x27a5
301#define bf532_chipid bf531_chipid
302#define bf533_chipid bf531_chipid
303static const struct bfin_memory_layout bf531_mem[] = {
304 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
305 LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO stub */
306 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
307 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
308 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
309 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
310 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
311};
312static const struct bfin_memory_layout bf532_mem[] = {
313 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
314 LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO stub */
315 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
316 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
317 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
318 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
319 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
320 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
321 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
322};
323static const struct bfin_memory_layout bf533_mem[] = {
324 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
325 LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO stub */
326 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
327 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
328 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
329 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
330 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
331 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
332 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
333 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
334 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
335 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
336};
337static const struct bfin_dev_layout bf533_dev[] = {
338 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
339 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
340 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
341 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
342 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
343 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
344 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
345 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
346 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
347 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
348};
349#define bf531_dev bf533_dev
350#define bf532_dev bf533_dev
351static const struct bfin_dmac_layout bf533_dmac[] = {
352 { BFIN_MMR_DMAC0_BASE, 8, },
353};
354#define bf531_dmac bf533_dmac
355#define bf532_dmac bf533_dmac
356
357#define bf534_chipid 0x27c6
358#define bf536_chipid 0x27c8
359#define bf537_chipid bf536_chipid
360static const struct bfin_memory_layout bf534_mem[] = {
361 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
362 LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
363 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
364 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
365 LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */
366 LAYOUT (0xFFC01700, 0x50, read_write), /* PORTH stub */
367 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
368 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
369 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
370 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
371 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
372 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
373 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
374 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
375};
376static const struct bfin_memory_layout bf536_mem[] = {
377 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
378 LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
379 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
380 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
381 LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */
382 LAYOUT (0xFFC01700, 0x50, read_write), /* PORTG stub */
383 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
384 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
385 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
386 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
387 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
388 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
389};
390static const struct bfin_memory_layout bf537_mem[] = {
391 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
392 LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
393 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
394 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
395 LAYOUT (0xFFC01500, 0x50, read_write), /* PORTG stub */
396 LAYOUT (0xFFC01700, 0x50, read_write), /* PORTG stub */
397 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
398 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
399 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
400 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
401 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
402 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
403 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
404 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
405};
406static const struct bfin_dev_layout bf534_dev[] = {
407 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
408 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
409 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
410 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
411 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
412 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
413 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
414 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
415 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
416 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
417 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
418 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
419 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
420 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
421 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
422 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
423 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
424};
425static const struct bfin_dev_layout bf537_dev[] = {
426 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
427 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
428 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
429 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
430 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
431 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
432 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
433 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
434 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
435 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
436 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
437 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
438 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
439 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
440 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
441 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
442 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
443 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
444 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
445};
446#define bf536_dev bf537_dev
447#define bf534_dmac bf50x_dmac
448#define bf536_dmac bf50x_dmac
449#define bf537_dmac bf50x_dmac
450
451#define bf538_chipid 0x27c4
452#define bf539_chipid bf538_chipid
453static const struct bfin_memory_layout bf538_mem[] = {
454 LAYOUT (0xFFC00700, 0x50, read_write), /* PORTF stub */
455 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
456 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
457 LAYOUT (0xFFC01500, 0x70, read_write), /* PORTC/D/E stub */
458 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
459 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
460 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
461 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
462 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
463 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
464 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
465 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
466 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
467 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
468};
469#define bf539_mem bf538_mem
470static const struct bfin_dev_layout bf538_dev[] = {
471 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
472 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
473 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
474 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
475 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
476 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
477 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
478 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
479 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
480 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
481 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
482 _DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1", 1),
483 _DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart@2", 1),
484 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
485 _DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1", 1),
486 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1),
487};
488#define bf539_dev bf538_dev
489static const struct bfin_dmac_layout bf538_dmac[] = {
490 { BFIN_MMR_DMAC0_BASE, 8, },
491 { BFIN_MMR_DMAC1_BASE, 12, },
492};
493#define bf539_dmac bf538_dmac
494
495#define bf54x_chipid 0x27de
496#define bf542_chipid bf54x_chipid
497#define bf544_chipid bf54x_chipid
498#define bf547_chipid bf54x_chipid
499#define bf548_chipid bf54x_chipid
500#define bf549_chipid bf54x_chipid
501static const struct bfin_memory_layout bf54x_mem[] = {
502 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub XXX: not on BF542/4 */
503 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
504 LAYOUT (0xFFC01400, 0x200, read_write), /* PORT/GPIO stub */
505 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
506 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
507 LAYOUT (0xFFC03800, 0x70, read_write), /* ATAPI stub */
508 LAYOUT (0xFFC03900, 0x100, read_write), /* RSI stub */
509 LAYOUT (0xFFC03C00, 0x500, read_write), /* MUSB stub */
510 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
511 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
512 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
513 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
514 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
515 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
516 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
517 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
518};
519#define bf542_mem bf54x_mem
520#define bf544_mem bf54x_mem
521#define bf547_mem bf54x_mem
522#define bf548_mem bf54x_mem
523#define bf549_mem bf54x_mem
524static const struct bfin_dev_layout bf542_dev[] = {
525 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
526 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
527 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
528 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
529 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
530 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
531 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
532 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
533 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
534 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
535 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
536 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
537 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
538 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
539 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
540 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
541 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
542 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
543 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
544 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
545 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
546 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
547 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"),
548};
549static const struct bfin_dev_layout bf544_dev[] = {
550 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
551 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
552 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
553 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
554 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
555 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
556 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
557 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
558 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
559 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
560 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
561 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
562 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
563 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
564 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
565 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
566 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
567 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
568 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
569 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
570 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
571 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
572 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
573 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
574 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
575 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
576 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
577 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"),
578};
579static const struct bfin_dev_layout bf547_dev[] = {
580 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
581 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
582 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
583 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
584 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
585 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
586 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
587 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
588 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
589 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
590 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
591 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
592 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
593 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
594 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
595 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
596 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
597 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
598 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
599 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
600 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
601 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
602 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
603 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
604 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1),
605 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
606 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
607 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
608};
609#define bf548_dev bf547_dev
610#define bf549_dev bf547_dev
611static const struct bfin_dmac_layout bf54x_dmac[] = {
612 { BFIN_MMR_DMAC0_BASE, 12, },
613 { BFIN_MMR_DMAC1_BASE, 12, },
614};
615#define bf542_dmac bf54x_dmac
616#define bf544_dmac bf54x_dmac
617#define bf547_dmac bf54x_dmac
618#define bf548_dmac bf54x_dmac
619#define bf549_dmac bf54x_dmac
620
621/* This is only Core A of course ... */
622#define bf561_chipid 0x27bb
623static const struct bfin_memory_layout bf561_mem[] = {
624 LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO0 stub */
625 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
626 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
627 LAYOUT (0xFFC01500, 0x50, read_write), /* GPIO1 stub */
628 LAYOUT (0xFFC01700, 0x50, read_write), /* GPIO2 stub */
629 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
630 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
631 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
632 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
633 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
634 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
635 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
636};
637static const struct bfin_dev_layout bf561_dev[] = {
638 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
639 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
640 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
641 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
642 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
643 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
644 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
645 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
646 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
647 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
648 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
649 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
650 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
651 _DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0", 1),
652 DEVICE (0xFFC01200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@1"),
653 _DEVICE (0xFFC01300, BFIN_MMR_PPI_SIZE, "bfin_ppi@1", 1),
654 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
655 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
656 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
657 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@11"),
658};
659static const struct bfin_dmac_layout bf561_dmac[] = {
660 { BFIN_MMR_DMAC0_BASE, 12, },
661 { BFIN_MMR_DMAC1_BASE, 12, },
662 /* XXX: IMDMA: { 0xFFC01800, 4, }, */
663};
664
665#define bf592_chipid 0x20cb
666static const struct bfin_memory_layout bf592_mem[] = {
667 LAYOUT (0xFFC00700, 0x50, read_write), /* GPIO0 stub */
668 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
669 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
670 LAYOUT (0xFFC01500, 0x50, read_write), /* GPIO1 stub */
671 LAYOUT (0xFF800000, 0x8000, read_write), /* Data A */
672 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
673 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst B [1] */
674};
675static const struct bfin_dev_layout bf592_dev[] = {
676 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
677 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
678 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
679 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
680 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
681 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
682 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
683 DEVICE (0xFFC01300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
684 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
685};
686static const struct bfin_dmac_layout bf592_dmac[] = {
687 /* XXX: there are only 9 channels, but mdma code below assumes that they
688 start right after the dma channels ... */
689 { BFIN_MMR_DMAC0_BASE, 12, },
690};
691
692static const struct bfin_model_data bfin_model_data[] =
693{
694#define P(n) \
695 [MODEL_BF##n] = { \
696 bf##n##_chipid, n, \
697 bf##n##_mem , ARRAY_SIZE (bf##n##_mem ), \
698 bf##n##_dev , ARRAY_SIZE (bf##n##_dev ), \
699 bf##n##_dmac, ARRAY_SIZE (bf##n##_dmac), \
700 },
701#include "proc_list.def"
702#undef P
703};
704
705#define CORE_DEVICE(dev, DEV) \
706 DEVICE (BFIN_COREMMR_##DEV##_BASE, BFIN_COREMMR_##DEV##_SIZE, "bfin_"#dev)
707static const struct bfin_dev_layout bfin_core_dev[] = {
708 CORE_DEVICE (cec, CEC),
709 CORE_DEVICE (ctimer, CTIMER),
710 CORE_DEVICE (evt, EVT),
711 CORE_DEVICE (jtag, JTAG),
712 CORE_DEVICE (mmu, MMU),
713 CORE_DEVICE (trace, TRACE),
714 CORE_DEVICE (wp, WP),
715};
716
717#define dv_bfin_hw_parse(sd, dv, DV) \
718 do { \
719 bu32 base = BFIN_MMR_##DV##_BASE; \
720 bu32 size = BFIN_MMR_##DV##_SIZE; \
721 sim_hw_parse (sd, "/core/bfin_"#dv"/reg %#x %i", base, size); \
722 sim_hw_parse (sd, "/core/bfin_"#dv"/type %i", mdata->model_num); \
723 } while (0)
724
725static void
726bfin_model_hw_tree_init (SIM_DESC sd, SIM_CPU *cpu)
727{
728 const MODEL *model = CPU_MODEL (cpu);
729 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
730 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
731 int mnum = MODEL_NUM (model);
732 unsigned i, j, dma_chan;
733
734 /* Map the core devices. */
735 for (i = 0; i < ARRAY_SIZE (bfin_core_dev); ++i)
736 {
737 const struct bfin_dev_layout *dev = &bfin_core_dev[i];
738 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
739 }
740 sim_hw_parse (sd, "/core/bfin_ctimer > ivtmr ivtmr /core/bfin_cec");
741
742 if (mnum == MODEL_BF000)
743 goto done;
744
745 /* Map the system devices. */
746 dv_bfin_hw_parse (sd, sic, SIC);
747 sim_hw_parse (sd, "/core/bfin_sic/type %i", mdata->model_num);
748 for (i = 7; i < 16; ++i)
749 sim_hw_parse (sd, "/core/bfin_sic > ivg%i ivg%i /core/bfin_cec", i, i);
750
751 dv_bfin_hw_parse (sd, pll, PLL);
752 sim_hw_parse (sd, "/core/bfin_pll > pll pll /core/bfin_sic");
753
754 dma_chan = 0;
755 for (i = 0; i < mdata->dmac_count; ++i)
756 {
757 const struct bfin_dmac_layout *dmac = &mdata->dmac[i];
758
759 sim_hw_parse (sd, "/core/bfin_dmac@%u/type %i", i, mdata->model_num);
760
761 /* Hook up the non-mdma channels. */
762 for (j = 0; j < dmac->dma_count; ++j)
763 {
764 sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u/reg %#x %i", i,
765 dma_chan, dmac->base + j * BFIN_MMR_DMA_SIZE,
766 BFIN_MMR_DMA_SIZE);
767
768 /* Could route these into the bfin_dmac and let that
769 forward it to the SIC, but not much value. */
770 sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u > di dma@%u /core/bfin_sic",
771 i, dma_chan, dma_chan);
772
773 ++dma_chan;
774 }
775
776 /* Hook up the mdma channels -- assume every DMAC has 4. */
777 for (j = 0; j < 4; ++j)
778 {
779 sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u/reg %#x %i",
780 i, j + BFIN_DMAC_MDMA_BASE,
781 dmac->base + (j + dmac->dma_count) * BFIN_MMR_DMA_SIZE,
782 BFIN_MMR_DMA_SIZE);
783 sim_hw_parse (sd, "/core/bfin_dmac@%u/bfin_dma@%u > di mdma@%u /core/bfin_sic",
784 i, j + BFIN_DMAC_MDMA_BASE, (2 * i) + (j / 2));
785 }
786 }
787
788 for (i = 0; i < mdata->dev_count; ++i)
789 {
790 const struct bfin_dev_layout *dev = &mdata->dev[i];
791 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
792 sim_hw_parse (sd, "/core/%s/type %i", dev->dev, mdata->model_num);
793 if (strchr (dev->dev, '/'))
794 continue;
795 if (!strncmp (dev->dev, "bfin_uart", 9)
796 || !strncmp (dev->dev, "bfin_emac", 9)
797 || !strncmp (dev->dev, "bfin_sport", 10))
798 {
799 const char *sint = dev->dev + 5;
800 sim_hw_parse (sd, "/core/%s > tx %s_tx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
801 sim_hw_parse (sd, "/core/%s > rx %s_rx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
802 sim_hw_parse (sd, "/core/%s > stat %s_stat /core/bfin_sic", dev->dev, sint);
803 }
804 else if (!strncmp (dev->dev, "bfin_gptimer", 12)
805 || !strncmp (dev->dev, "bfin_ppi", 8)
806 || !strncmp (dev->dev, "bfin_spi", 8)
807 || !strncmp (dev->dev, "bfin_twi", 8))
808 {
809 const char *sint = dev->dev + 5;
810 sim_hw_parse (sd, "/core/%s > stat %s /core/bfin_sic", dev->dev, sint);
811 }
812 else if (!strncmp (dev->dev, "bfin_rtc", 8))
813 {
814 const char *sint = dev->dev + 5;
815 sim_hw_parse (sd, "/core/%s > %s %s /core/bfin_sic", dev->dev, sint, sint);
816 }
817 else if (!strncmp (dev->dev, "bfin_wdog", 9))
818 {
819 sim_hw_parse (sd, "/core/%s > reset rst /core/bfin_cec", dev->dev);
820 sim_hw_parse (sd, "/core/%s > nmi nmi /core/bfin_cec", dev->dev);
821 sim_hw_parse (sd, "/core/%s > gpi wdog /core/bfin_sic", dev->dev);
822 }
823 }
824
825 done:
826 /* Add any additional user board content. */
827 if (board->hw_file)
828 sim_do_commandf (sd, "hw-file %s", board->hw_file);
829
830 /* Trigger all the new devices' finish func. */
831 hw_tree_finish (dv_get_device (cpu, "/"));
832}
833
834#include "bfroms/all.h"
835
836struct bfrom {
837 bu32 addr, len, alias_len;
838 int sirev;
839 const char *buf;
840};
841
842#define BFROMA(addr, rom, sirev, alias_len) \
843 { addr, sizeof (bfrom_bf##rom##_0_##sirev), alias_len, \
844 sirev, bfrom_bf##rom##_0_##sirev, }
845#define BFROM(rom, sirev, alias_len) BFROMA (0xef000000, rom, sirev, alias_len)
846#define BFROM_STUB { 0, 0, 0, 0, NULL, }
847static const struct bfrom bf50x_roms[] = {
848 BFROM (50x, 0, 0x1000000),
849 BFROM_STUB,
850};
851static const struct bfrom bf51x_roms[] = {
852 BFROM (51x, 2, 0x1000000),
853 BFROM (51x, 1, 0x1000000),
854 BFROM (51x, 0, 0x1000000),
855 BFROM_STUB,
856};
857static const struct bfrom bf526_roms[] = {
858 BFROM (526, 1, 0x1000000),
859 BFROM (526, 0, 0x1000000),
860 BFROM_STUB,
861};
862static const struct bfrom bf527_roms[] = {
863 BFROM (527, 2, 0x1000000),
864 BFROM (527, 1, 0x1000000),
865 BFROM (527, 0, 0x1000000),
866 BFROM_STUB,
867};
868static const struct bfrom bf533_roms[] = {
869 BFROM (533, 6, 0x1000000),
870 BFROM (533, 5, 0x1000000),
871 BFROM (533, 4, 0x1000000),
872 BFROM (533, 3, 0x1000000),
873 BFROM (533, 2, 0x1000000),
874 BFROM (533, 1, 0x1000000),
875 BFROM_STUB,
876};
877static const struct bfrom bf537_roms[] = {
878 BFROM (537, 3, 0x100000),
879 BFROM (537, 2, 0x100000),
880 BFROM (537, 1, 0x100000),
881 BFROM (537, 0, 0x100000),
882 BFROM_STUB,
883};
884static const struct bfrom bf538_roms[] = {
885 BFROM (538, 5, 0x1000000),
886 BFROM (538, 4, 0x1000000),
887 BFROM (538, 3, 0x1000000),
888 BFROM (538, 2, 0x1000000),
889 BFROM (538, 1, 0x1000000),
890 BFROM (538, 0, 0x1000000),
891 BFROM_STUB,
892};
893static const struct bfrom bf54x_roms[] = {
894 BFROM (54x, 2, 0),
895 BFROM (54x, 1, 0),
896 BFROM (54x, 0, 0),
897 BFROMA (0xffa14000, 54x_l1, 2, 0),
898 BFROMA (0xffa14000, 54x_l1, 1, 0),
899 BFROMA (0xffa14000, 54x_l1, 0, 0),
900 BFROM_STUB,
901};
902static const struct bfrom bf561_roms[] = {
903 /* XXX: No idea what the actual wrap limit is here. */
904 BFROM (561, 5, 0),
905 BFROM_STUB,
906};
907static const struct bfrom bf59x_roms[] = {
908 BFROM (59x, 1, 0x1000000),
909 BFROM (59x, 0, 0x1000000),
910 BFROMA (0xffa10000, 59x_l1, 1, 0),
911 BFROM_STUB,
912};
913
914static void
915bfin_model_map_bfrom (SIM_DESC sd, SIM_CPU *cpu)
916{
917 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
918 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
919 int mnum = mdata->model_num;
920 const struct bfrom *bfrom;
921 unsigned int sirev;
922
923 if (mnum >= 500 && mnum <= 509)
924 bfrom = bf50x_roms;
925 else if (mnum >= 510 && mnum <= 519)
926 bfrom = bf51x_roms;
927 else if (mnum >= 520 && mnum <= 529)
928 bfrom = (mnum & 1) ? bf527_roms : bf526_roms;
929 else if (mnum >= 531 && mnum <= 533)
930 bfrom = bf533_roms;
931 else if (mnum == 535)
932 /* Stub. */;
933 else if (mnum >= 534 && mnum <= 537)
934 bfrom = bf537_roms;
935 else if (mnum >= 538 && mnum <= 539)
936 bfrom = bf538_roms;
937 else if (mnum >= 540 && mnum <= 549)
938 bfrom = bf54x_roms;
939 else if (mnum == 561)
940 bfrom = bf561_roms;
941 else if (mnum >= 590 && mnum <= 599)
942 bfrom = bf59x_roms;
943 else
944 return;
945
946 if (board->sirev_valid)
947 sirev = board->sirev;
948 else
949 sirev = bfrom->sirev;
950 while (bfrom->buf)
951 {
952 /* Map all the ranges for this model/sirev. */
953 if (bfrom->sirev == sirev)
954 sim_core_attach (sd, NULL, 0, access_read_exec, 0, bfrom->addr,
955 bfrom->alias_len ? : bfrom->len, bfrom->len, NULL,
956 (char *)bfrom->buf);
957 ++bfrom;
958 }
959}
960
961void
962bfin_model_cpu_init (SIM_DESC sd, SIM_CPU *cpu)
963{
964 const MODEL *model = CPU_MODEL (cpu);
965 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
966 int mnum = MODEL_NUM (model);
967 size_t idx;
968
969 /* These memory maps are supposed to be cpu-specific, but the common sim
970 code does not yet allow that (2nd arg is "cpu" rather than "NULL". */
971 sim_core_attach (sd, NULL, 0, access_read_write, 0, BFIN_L1_SRAM_SCRATCH,
972 BFIN_L1_SRAM_SCRATCH_SIZE, 0, NULL, NULL);
973
974 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
975 return;
976
977 if (mnum == MODEL_BF000)
978 goto core_only;
979
980 /* Map in the on-chip memories (SRAMs). */
981 mdata = &bfin_model_data[MODEL_NUM (model)];
982 for (idx = 0; idx < mdata->mem_count; ++idx)
983 {
984 const struct bfin_memory_layout *mem = &mdata->mem[idx];
985 sim_core_attach (sd, NULL, 0, mem->mask, 0, mem->addr,
986 mem->len, 0, NULL, NULL);
987 }
988
989 /* Map the on-chip ROMs. */
990 bfin_model_map_bfrom (sd, cpu);
991
992 core_only:
993 /* Finally, build up the tree for this cpu model. */
994 bfin_model_hw_tree_init (sd, cpu);
995}
996
997bu32
998bfin_model_get_chipid (SIM_DESC sd)
999{
1000 SIM_CPU *cpu = STATE_CPU (sd, 0);
1001 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1002 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1003 return
1004 (board->sirev << 28) |
1005 (mdata->chipid << 12) |
1006 (((0xE5 << 1) | 1) & 0xFF);
1007}
1008
1009bu32
1010bfin_model_get_dspid (SIM_DESC sd)
1011{
1012 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1013 return
1014 (0xE5 << 24) |
1015 (0x04 << 16) |
1016 (board->sirev);
1017}
1018
1019static void
1020bfin_model_init (SIM_CPU *cpu)
1021{
1022 CPU_MODEL_DATA (cpu) = (void *) &bfin_model_data[MODEL_NUM (CPU_MODEL (cpu))];
1023}
1024
1025static bu32
1026bfin_extract_unsigned_integer (unsigned char *addr, int len)
1027{
1028 bu32 retval;
1029 unsigned char * p;
1030 unsigned char * startaddr = (unsigned char *)addr;
1031 unsigned char * endaddr = startaddr + len;
1032
1033 retval = 0;
1034
1035 for (p = endaddr; p > startaddr;)
1036 retval = (retval << 8) | *--p;
1037
1038 return retval;
1039}
1040
1041static void
1042bfin_store_unsigned_integer (unsigned char *addr, int len, bu32 val)
1043{
1044 unsigned char *p;
1045 unsigned char *startaddr = addr;
1046 unsigned char *endaddr = startaddr + len;
1047
1048 for (p = startaddr; p < endaddr;)
1049 {
1050 *p++ = val & 0xff;
1051 val >>= 8;
1052 }
1053}
1054
1055static bu32 *
1056bfin_get_reg (SIM_CPU *cpu, int rn)
1057{
1058 switch (rn)
1059 {
1060 case SIM_BFIN_R0_REGNUM: return &DREG (0);
1061 case SIM_BFIN_R1_REGNUM: return &DREG (1);
1062 case SIM_BFIN_R2_REGNUM: return &DREG (2);
1063 case SIM_BFIN_R3_REGNUM: return &DREG (3);
1064 case SIM_BFIN_R4_REGNUM: return &DREG (4);
1065 case SIM_BFIN_R5_REGNUM: return &DREG (5);
1066 case SIM_BFIN_R6_REGNUM: return &DREG (6);
1067 case SIM_BFIN_R7_REGNUM: return &DREG (7);
1068 case SIM_BFIN_P0_REGNUM: return &PREG (0);
1069 case SIM_BFIN_P1_REGNUM: return &PREG (1);
1070 case SIM_BFIN_P2_REGNUM: return &PREG (2);
1071 case SIM_BFIN_P3_REGNUM: return &PREG (3);
1072 case SIM_BFIN_P4_REGNUM: return &PREG (4);
1073 case SIM_BFIN_P5_REGNUM: return &PREG (5);
1074 case SIM_BFIN_SP_REGNUM: return &SPREG;
1075 case SIM_BFIN_FP_REGNUM: return &FPREG;
1076 case SIM_BFIN_I0_REGNUM: return &IREG (0);
1077 case SIM_BFIN_I1_REGNUM: return &IREG (1);
1078 case SIM_BFIN_I2_REGNUM: return &IREG (2);
1079 case SIM_BFIN_I3_REGNUM: return &IREG (3);
1080 case SIM_BFIN_M0_REGNUM: return &MREG (0);
1081 case SIM_BFIN_M1_REGNUM: return &MREG (1);
1082 case SIM_BFIN_M2_REGNUM: return &MREG (2);
1083 case SIM_BFIN_M3_REGNUM: return &MREG (3);
1084 case SIM_BFIN_B0_REGNUM: return &BREG (0);
1085 case SIM_BFIN_B1_REGNUM: return &BREG (1);
1086 case SIM_BFIN_B2_REGNUM: return &BREG (2);
1087 case SIM_BFIN_B3_REGNUM: return &BREG (3);
1088 case SIM_BFIN_L0_REGNUM: return &LREG (0);
1089 case SIM_BFIN_L1_REGNUM: return &LREG (1);
1090 case SIM_BFIN_L2_REGNUM: return &LREG (2);
1091 case SIM_BFIN_L3_REGNUM: return &LREG (3);
1092 case SIM_BFIN_RETS_REGNUM: return &RETSREG;
1093 case SIM_BFIN_A0_DOT_X_REGNUM: return &AXREG (0);
1094 case SIM_BFIN_A0_DOT_W_REGNUM: return &AWREG (0);
1095 case SIM_BFIN_A1_DOT_X_REGNUM: return &AXREG (1);
1096 case SIM_BFIN_A1_DOT_W_REGNUM: return &AWREG (1);
1097 case SIM_BFIN_LC0_REGNUM: return &LCREG (0);
1098 case SIM_BFIN_LT0_REGNUM: return &LTREG (0);
1099 case SIM_BFIN_LB0_REGNUM: return &LBREG (0);
1100 case SIM_BFIN_LC1_REGNUM: return &LCREG (1);
1101 case SIM_BFIN_LT1_REGNUM: return &LTREG (1);
1102 case SIM_BFIN_LB1_REGNUM: return &LBREG (1);
1103 case SIM_BFIN_CYCLES_REGNUM: return &CYCLESREG;
1104 case SIM_BFIN_CYCLES2_REGNUM: return &CYCLES2REG;
1105 case SIM_BFIN_USP_REGNUM: return &USPREG;
1106 case SIM_BFIN_SEQSTAT_REGNUM: return &SEQSTATREG;
1107 case SIM_BFIN_SYSCFG_REGNUM: return &SYSCFGREG;
1108 case SIM_BFIN_RETI_REGNUM: return &RETIREG;
1109 case SIM_BFIN_RETX_REGNUM: return &RETXREG;
1110 case SIM_BFIN_RETN_REGNUM: return &RETNREG;
1111 case SIM_BFIN_RETE_REGNUM: return &RETEREG;
1112 case SIM_BFIN_PC_REGNUM: return &PCREG;
1113 default: return NULL;
1114 }
1115}
1116
1117static int
1118bfin_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
1119{
1120 bu32 value, *reg;
1121
1122 reg = bfin_get_reg (cpu, rn);
1123 if (reg)
1124 value = *reg;
1125 else if (rn == SIM_BFIN_ASTAT_REGNUM)
1126 value = ASTAT;
1127 else if (rn == SIM_BFIN_CC_REGNUM)
1128 value = CCREG;
1129 else
1130 return 0; // will be an error in gdb
1131
1132 /* Handle our KSP/USP shadowing in SP. While in supervisor mode, we
1133 have the normal SP/USP behavior. User mode is tricky though. */
1134 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) == OPERATING_ENVIRONMENT
1135 && cec_is_user_mode (cpu))
1136 {
1137 if (rn == SIM_BFIN_SP_REGNUM)
1138 value = KSPREG;
1139 else if (rn == SIM_BFIN_USP_REGNUM)
1140 value = SPREG;
1141 }
1142
1143 bfin_store_unsigned_integer (buf, 4, value);
1144
1145 return -1; // disables size checking in gdb
1146}
1147
1148static int
1149bfin_reg_store (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
1150{
1151 bu32 value, *reg;
1152
1153 value = bfin_extract_unsigned_integer (buf, 4);
1154 reg = bfin_get_reg (cpu, rn);
1155
1156 if (reg)
1157 /* XXX: Need register trace ? */
1158 *reg = value;
1159 else if (rn == SIM_BFIN_ASTAT_REGNUM)
1160 SET_ASTAT (value);
1161 else if (rn == SIM_BFIN_CC_REGNUM)
1162 SET_CCREG (value);
1163 else
1164 return 0; // will be an error in gdb
1165
1166 return -1; // disables size checking in gdb
1167}
1168
1169static sim_cia
1170bfin_pc_get (SIM_CPU *cpu)
1171{
1172 return PCREG;
1173}
1174
1175static void
1176bfin_pc_set (SIM_CPU *cpu, sim_cia newpc)
1177{
1178 SET_PCREG (newpc);
1179}
1180
1181static const char *
1182bfin_insn_name (SIM_CPU *cpu, int i)
1183{
1184 static const char * const insn_name[] = {
1185#define I(insn) #insn,
1186#include "insn_list.def"
1187#undef I
1188 };
1189 return insn_name[i];
1190}
1191
1192static void
1193bfin_init_cpu (SIM_CPU *cpu)
1194{
1195 CPU_REG_FETCH (cpu) = bfin_reg_fetch;
1196 CPU_REG_STORE (cpu) = bfin_reg_store;
1197 CPU_PC_FETCH (cpu) = bfin_pc_get;
1198 CPU_PC_STORE (cpu) = bfin_pc_set;
1199 CPU_MAX_INSNS (cpu) = BFIN_INSN_MAX;
1200 CPU_INSN_NAME (cpu) = bfin_insn_name;
1201}
1202
1203static void
1204bfin_prepare_run (SIM_CPU *cpu)
1205{
1206}
1207
1208static const MODEL bfin_models[] =
1209{
1210#define P(n) { "bf"#n, & bfin_mach, MODEL_BF##n, NULL, bfin_model_init },
1211#include "proc_list.def"
1212#undef P
1213 { 0, NULL, 0, NULL, NULL, }
1214};
1215
1216static const MACH_IMP_PROPERTIES bfin_imp_properties =
1217{
1218 sizeof (SIM_CPU),
1219 0,
1220};
1221
1222static const MACH bfin_mach =
1223{
1224 "bfin", "bfin", MACH_BFIN,
1225 32, 32, & bfin_models[0], & bfin_imp_properties,
1226 bfin_init_cpu,
1227 bfin_prepare_run
1228};
1229
1230const MACH *sim_machs[] =
1231{
1232 & bfin_mach,
1233 NULL
1234};
1235\f
1236/* Device option parsing. */
1237
1238static DECLARE_OPTION_HANDLER (bfin_mach_option_handler);
1239
1240enum {
1241 OPTION_MACH_SIREV = OPTION_START,
1242 OPTION_MACH_HW_BOARD_FILE,
1243};
1244
1245const OPTION bfin_mach_options[] =
1246{
1247 { {"sirev", required_argument, NULL, OPTION_MACH_SIREV },
1248 '\0', "NUMBER", "Set CPU silicon revision",
1249 bfin_mach_option_handler, NULL },
1250
1251 { {"hw-board-file", required_argument, NULL, OPTION_MACH_HW_BOARD_FILE },
1252 '\0', "FILE", "Add the supplemental devices listed in the file",
1253 bfin_mach_option_handler, NULL },
1254
1255 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL }
1256};
1257
1258static SIM_RC
1259bfin_mach_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt,
1260 char *arg, int is_command)
1261{
1262 struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1263
1264 switch (opt)
1265 {
1266 case OPTION_MACH_SIREV:
1267 board->sirev_valid = 1;
1268 /* Accept (and throw away) a leading "0." in the version. */
1269 if (!strncmp (arg, "0.", 2))
1270 arg += 2;
1271 board->sirev = atoi (arg);
1272 if (board->sirev > 0xf)
1273 {
1274 sim_io_eprintf (sd, "sirev '%s' needs to fit into 4 bits\n", arg);
1275 return SIM_RC_FAIL;
1276 }
1277 return SIM_RC_OK;
1278
1279 case OPTION_MACH_HW_BOARD_FILE:
1280 board->hw_file = xstrdup (arg);
1281 return SIM_RC_OK;
1282
1283 default:
1284 sim_io_eprintf (sd, "Unknown Blackfin option %d\n", opt);
1285 return SIM_RC_FAIL;
1286 }
1287}
GDB Binutils - Deliverables
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