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c906108c | 1 | /* Simulator header for cgen cpus. |
e2882c85 | 2 | Copyright (C) 1998-2018 Free Software Foundation, Inc. |
c906108c SS |
3 | Contributed by Cygnus Support. |
4 | ||
5 | This file is part of GDB, the GNU debugger. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
9 | the Free Software Foundation; either version 3 of the License, or |
10 | (at your option) any later version. | |
c906108c SS |
11 | |
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
4744ac1b JB |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
c906108c SS |
19 | |
20 | #ifndef CGEN_CPU_H | |
21 | #define CGEN_CPU_H | |
22 | ||
23 | /* Type of function that is ultimately called by sim_resume. */ | |
24 | typedef void (ENGINE_FN) (SIM_CPU *); | |
25 | ||
26 | /* Type of function to do disassembly. */ | |
27 | typedef void (CGEN_DISASSEMBLER) (SIM_CPU *, const CGEN_INSN *, | |
28 | const ARGBUF *, IADDR pc_, char *buf_); | |
29 | ||
30 | /* Additional non-machine generated per-cpu data to go in SIM_CPU. | |
31 | The member's name must be `cgen_cpu'. */ | |
32 | ||
33 | typedef struct { | |
34 | /* Non-zero while cpu simulation is running. */ | |
35 | int running_p; | |
36 | #define CPU_RUNNING_P(cpu) ((cpu)->cgen_cpu.running_p) | |
37 | ||
38 | /* Instruction count. This is maintained even in fast mode to keep track | |
39 | of simulator speed. */ | |
40 | unsigned long insn_count; | |
41 | #define CPU_INSN_COUNT(cpu) ((cpu)->cgen_cpu.insn_count) | |
42 | ||
43 | /* sim_resume handlers */ | |
44 | ENGINE_FN *fast_engine_fn; | |
45 | #define CPU_FAST_ENGINE_FN(cpu) ((cpu)->cgen_cpu.fast_engine_fn) | |
46 | ENGINE_FN *full_engine_fn; | |
47 | #define CPU_FULL_ENGINE_FN(cpu) ((cpu)->cgen_cpu.full_engine_fn) | |
48 | ||
49 | /* Maximum number of instructions per time slice. | |
50 | When single stepping this is 1. If using the pbb model, this can be | |
51 | more than 1. 0 means "as long as you want". */ | |
52 | unsigned int max_slice_insns; | |
53 | #define CPU_MAX_SLICE_INSNS(cpu) ((cpu)->cgen_cpu.max_slice_insns) | |
54 | ||
55 | /* Simulator's execution cache. | |
56 | Allocate space for this even if not used as some simulators may have | |
57 | one machine variant that uses the scache and another that doesn't and | |
58 | we don't want members in this struct to move about. */ | |
59 | CPU_SCACHE scache; | |
60 | ||
61 | /* Instruction descriptor table. */ | |
62 | IDESC *idesc; | |
63 | #define CPU_IDESC(cpu) ((cpu)->cgen_cpu.idesc) | |
64 | ||
96baa820 JM |
65 | /* Whether the read,write,semantic entries (function pointers or computed |
66 | goto labels) have been initialized or not. */ | |
c906108c SS |
67 | int idesc_read_init_p; |
68 | #define CPU_IDESC_READ_INIT_P(cpu) ((cpu)->cgen_cpu.idesc_read_init_p) | |
69 | int idesc_write_init_p; | |
70 | #define CPU_IDESC_WRITE_INIT_P(cpu) ((cpu)->cgen_cpu.idesc_write_init_p) | |
71 | int idesc_sem_init_p; | |
72 | #define CPU_IDESC_SEM_INIT_P(cpu) ((cpu)->cgen_cpu.idesc_sem_init_p) | |
73 | ||
74 | /* Cpu descriptor table. | |
75 | This is a CGEN created entity that contains the description file | |
76 | turned into C code and tables for our use. */ | |
77 | CGEN_CPU_DESC cpu_desc; | |
78 | #define CPU_CPU_DESC(cpu) ((cpu)->cgen_cpu.cpu_desc) | |
79 | ||
80 | /* Function to fetch the insn data entry in the IDESC. */ | |
81 | const CGEN_INSN * (*get_idata) (SIM_CPU *, int); | |
82 | #define CPU_GET_IDATA(cpu) ((cpu)->cgen_cpu.get_idata) | |
83 | ||
43ff13b4 JM |
84 | /* Floating point support. */ |
85 | CGEN_FPU fpu; | |
86 | #define CGEN_CPU_FPU(cpu) (& (cpu)->cgen_cpu.fpu) | |
87 | ||
c906108c SS |
88 | /* Disassembler. */ |
89 | CGEN_DISASSEMBLER *disassembler; | |
90 | #define CPU_DISASSEMBLER(cpu) ((cpu)->cgen_cpu.disassembler) | |
91 | ||
d4f3574e SS |
92 | /* Queued writes for parallel write-after support. */ |
93 | CGEN_WRITE_QUEUE write_queue; | |
94 | #define CPU_WRITE_QUEUE(cpu) (& (cpu)->cgen_cpu.write_queue) | |
95 | ||
c906108c SS |
96 | /* Allow slop in size calcs for case where multiple cpu types are supported |
97 | and space for the specified cpu is malloc'd at run time. */ | |
98 | double slop; | |
99 | } CGEN_CPU; | |
100 | ||
101 | /* Shorthand macro for fetching registers. | |
102 | CPU_CGEN_HW is defined in cpu.h. */ | |
103 | #define CPU(x) (CPU_CGEN_HW (current_cpu)->x) | |
104 | ||
105 | #endif /* CGEN_CPU_H */ |