import gdb-1999-10-11 snapshot
[deliverable/binutils-gdb.git] / sim / common / cgen-par.h
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1/* Simulator header for cgen parallel support.
2 Copyright (C) 1999 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
4
5This file is part of the GNU instruction set simulator.
6
7This program is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
12This program is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License along
18with this program; if not, write to the Free Software Foundation, Inc.,
1959 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21#ifndef CGEN_PAR_H
22#define CGEN_PAR_H
23
24/* Kinds of writes stored on the write queue. */
25enum cgen_write_queue_kind {
c2c6d25f 26 CGEN_BI_WRITE, CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE,
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27 CGEN_PC_WRITE,
28 CGEN_FN_SI_WRITE, CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE,
29 CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE,
30 CGEN_NUM_WRITE_KINDS
31};
32
33/* Element of the write queue. */
34typedef struct {
35 enum cgen_write_queue_kind kind; /* Used to select union member below. */
36 union {
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37 struct {
38 BI *target;
39 BI value;
40 } bi_write;
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41 struct {
42 UQI *target;
43 QI value;
44 } qi_write;
45 struct {
46 SI *target;
47 SI value;
48 } si_write;
49 struct {
50 SI *target;
51 SF value;
52 } sf_write;
53 struct {
54 USI value;
55 } pc_write;
56 struct {
57 UINT regno;
58 SI value;
59 void (*function)(SIM_CPU *, UINT, USI);
60 } fn_si_write;
61 struct {
62 UINT regno;
63 DI value;
64 void (*function)(SIM_CPU *, UINT, DI);
65 } fn_di_write;
66 struct {
67 UINT regno;
68 DI value;
69 void (*function)(SIM_CPU *, UINT, DI);
70 } fn_df_write;
71 struct {
72 SI address;
73 QI value;
74 } mem_qi_write;
75 struct {
76 SI address;
77 HI value;
78 } mem_hi_write;
79 struct {
80 SI address;
81 SI value;
82 } mem_si_write;
83 } kinds;
84} CGEN_WRITE_QUEUE_ELEMENT;
85
86#define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind)
87
88extern void cgen_write_queue_element_execute (
89 SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *
90);
91
92/* Instance of the queue for parallel write-after support. */
93/* FIXME: Should be dynamic? */
94#define CGEN_WRITE_QUEUE_SIZE (4 * 4) /* 4 writes x 4 insns -- for now. */
95
96typedef struct {
97 int index;
98 CGEN_WRITE_QUEUE_ELEMENT q[CGEN_WRITE_QUEUE_SIZE];
99} CGEN_WRITE_QUEUE;
100
101#define CGEN_WRITE_QUEUE_CLEAR(queue) ((queue)->index = 0)
102#define CGEN_WRITE_QUEUE_INDEX(queue) ((queue)->index)
103#define CGEN_WRITE_QUEUE_ELEMENT(queue, ix) (&(queue)->q[(ix)])
104
105#define CGEN_WRITE_QUEUE_NEXT(queue) ( \
106 (queue)->index < CGEN_WRITE_QUEUE_SIZE \
107 ? &(queue)->q[(queue)->index++] \
108 : cgen_write_queue_overflow (queue) \
109)
110
111extern CGEN_WRITE_QUEUE_ELEMENT *cgen_write_queue_overflow (CGEN_WRITE_QUEUE *);
112
113/* Functions for queuing writes. Used by semantic code. */
c2c6d25f 114extern void sim_queue_bi_write (SIM_CPU *, BI *, BI);
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115extern void sim_queue_qi_write (SIM_CPU *, UQI *, UQI);
116extern void sim_queue_si_write (SIM_CPU *, SI *, SI);
117extern void sim_queue_sf_write (SIM_CPU *, SI *, SF);
118
119extern void sim_queue_pc_write (SIM_CPU *, USI);
120
121extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, SI);
122extern void sim_queue_fn_di_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DI);
123extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DF);
124
125extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI);
126extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI);
127extern void sim_queue_mem_si_write (SIM_CPU *, SI, SI);
128
129#endif /* CGEN_PAR_H */
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