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c906108c SS |
1 | /* Simulator header for cgen scache support. |
2 | Copyright (C) 1998 Free Software Foundation, Inc. | |
3 | Contributed by Cygnus Solutions. | |
4 | ||
5 | This file is part of GDB, the GNU debugger. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License along | |
18 | with this program; if not, write to the Free Software Foundation, Inc., | |
19 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #ifndef CGEN_SCACHE_H | |
22 | #define CGEN_SCACHE_H | |
23 | ||
24 | #ifndef WITH_SCACHE | |
25 | #define WITH_SCACHE 0 | |
26 | #endif | |
27 | ||
28 | /* When caching bb's, instructions are extracted into "chains". | |
29 | SCACHE_MAP is a hash table into these chains. */ | |
30 | ||
31 | typedef struct { | |
32 | IADDR pc; | |
33 | SCACHE *sc; | |
34 | } SCACHE_MAP; | |
35 | ||
36 | typedef struct cpu_scache { | |
37 | /* Simulator cache size. Must be a power of 2. | |
38 | This is the number of elements in the `cache' member. */ | |
39 | unsigned int size; | |
40 | #define CPU_SCACHE_SIZE(cpu) ((cpu) -> cgen_cpu.scache.size) | |
41 | /* The cache. */ | |
42 | SCACHE *cache; | |
43 | #define CPU_SCACHE_CACHE(cpu) ((cpu) -> cgen_cpu.scache.cache) | |
44 | ||
45 | #if WITH_SCACHE_PBB | |
46 | /* Number of hash chains. Must be a power of 2. */ | |
47 | unsigned int num_hash_chains; | |
48 | #define CPU_SCACHE_NUM_HASH_CHAINS(cpu) ((cpu) -> cgen_cpu.scache.num_hash_chains) | |
49 | /* Number of entries in each hash chain. | |
50 | The hash table is a statically allocated NxM array where | |
51 | N = num_hash_chains | |
52 | M = num_hash_chain_entries. */ | |
53 | unsigned int num_hash_chain_entries; | |
54 | #define CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES(cpu) ((cpu) -> cgen_cpu.scache.num_hash_chain_entries) | |
55 | /* Maximum number of instructions in a chain. | |
56 | ??? This just let's us set a static size of chain_lengths table. | |
57 | In a simulation that handles more than just the cpu, this might also be | |
58 | used to keep too many instructions from being executed before checking | |
59 | for events (or some such). */ | |
60 | unsigned int max_chain_length; | |
61 | #define CPU_SCACHE_MAX_CHAIN_LENGTH(cpu) ((cpu) -> cgen_cpu.scache.max_chain_length) | |
62 | /* Special scache entry for (re)starting bb extraction. */ | |
63 | SCACHE *pbb_begin; | |
64 | #define CPU_SCACHE_PBB_BEGIN(cpu) ((cpu) -> cgen_cpu.scache.pbb_begin) | |
65 | /* Hash table into cached chains. */ | |
66 | SCACHE_MAP *hash_table; | |
67 | #define CPU_SCACHE_HASH_TABLE(cpu) ((cpu) -> cgen_cpu.scache.hash_table) | |
68 | /* Next free entry in cache. */ | |
69 | SCACHE *next_free; | |
70 | #define CPU_SCACHE_NEXT_FREE(cpu) ((cpu) -> cgen_cpu.scache.next_free) | |
71 | ||
96baa820 JM |
72 | /* Kind of branch being taken. |
73 | Only used by functional semantics, not switch form. */ | |
74 | SEM_BRANCH_TYPE pbb_br_type; | |
75 | #define CPU_PBB_BR_TYPE(cpu) ((cpu) -> cgen_cpu.scache.pbb_br_type) | |
c906108c SS |
76 | /* Target's branch address. */ |
77 | IADDR pbb_br_npc; | |
78 | #define CPU_PBB_BR_NPC(cpu) ((cpu) -> cgen_cpu.scache.pbb_br_npc) | |
79 | #endif /* WITH_SCACHE_PBB */ | |
80 | ||
81 | #if WITH_PROFILE_SCACHE_P | |
82 | /* Cache hits, misses. */ | |
83 | unsigned long hits, misses; | |
84 | #define CPU_SCACHE_HITS(cpu) ((cpu) -> cgen_cpu.scache.hits) | |
85 | #define CPU_SCACHE_MISSES(cpu) ((cpu) -> cgen_cpu.scache.misses) | |
86 | ||
87 | #if WITH_SCACHE_PBB | |
88 | /* Chain length counts. | |
89 | Each element is a count of the number of chains created with that | |
90 | length. */ | |
91 | unsigned long *chain_lengths; | |
92 | #define CPU_SCACHE_CHAIN_LENGTHS(cpu) ((cpu) -> cgen_cpu.scache.chain_lengths) | |
93 | /* Number of times cache was flushed due to its being full. */ | |
94 | unsigned long full_flushes; | |
95 | #define CPU_SCACHE_FULL_FLUSHES(cpu) ((cpu) -> cgen_cpu.scache.full_flushes) | |
96 | #endif | |
97 | #endif | |
98 | } CPU_SCACHE; | |
99 | ||
100 | /* Hash a PC value. | |
101 | This is split into two parts to help with moving as much of the | |
102 | computation out of the main loop. */ | |
103 | #define CPU_SCACHE_HASH_MASK(cpu) (CPU_SCACHE_SIZE (cpu) - 1) | |
104 | #define SCACHE_HASH_PC(pc, mask) \ | |
105 | ((CGEN_MIN_INSN_SIZE == 2 ? ((pc) >> 1) \ | |
106 | : CGEN_MIN_INSN_SIZE == 4 ? ((pc) >> 2) \ | |
107 | : (pc)) \ | |
108 | & (mask)) | |
109 | ||
110 | /* Non-zero if cache is in use. */ | |
111 | #define USING_SCACHE_P(sd) (STATE_SCACHE_SIZE (sd) > 0) | |
112 | ||
113 | /* Install the simulator cache into the simulator. */ | |
114 | MODULE_INSTALL_FN scache_install; | |
115 | ||
116 | /* Lookup a PC value in the scache [compilation only]. */ | |
117 | extern SCACHE * scache_lookup (SIM_CPU *, IADDR); | |
118 | /* Return a pointer to at least N buffers. */ | |
119 | extern SCACHE *scache_lookup_or_alloc (SIM_CPU *, IADDR, int, SCACHE **); | |
120 | /* Flush all cpu's scaches. */ | |
121 | extern void scache_flush (SIM_DESC); | |
122 | /* Flush a cpu's scache. */ | |
123 | extern void scache_flush_cpu (SIM_CPU *); | |
124 | \f | |
125 | /* Scache profiling support. */ | |
126 | ||
127 | /* Print summary scache usage information. */ | |
128 | extern void scache_print_profile (SIM_CPU *cpu, int verbose); | |
129 | ||
130 | #if WITH_PROFILE_SCACHE_P | |
131 | ||
132 | #define PROFILE_COUNT_SCACHE_HIT(cpu) \ | |
133 | do { \ | |
134 | if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \ | |
135 | ++ CPU_SCACHE_HITS (cpu); \ | |
136 | } while (0) | |
137 | #define PROFILE_COUNT_SCACHE_MISS(cpu) \ | |
138 | do { \ | |
139 | if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \ | |
140 | ++ CPU_SCACHE_MISSES (cpu); \ | |
141 | } while (0) | |
142 | #define PROFILE_COUNT_SCACHE_CHAIN_LENGTH(cpu,length) \ | |
143 | do { \ | |
144 | if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \ | |
145 | ++ CPU_SCACHE_CHAIN_LENGTHS (cpu) [length]; \ | |
146 | } while (0) | |
147 | #define PROFILE_COUNT_SCACHE_FULL_FLUSH(cpu) \ | |
148 | do { \ | |
149 | if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \ | |
150 | ++ CPU_SCACHE_FULL_FLUSHES (cpu); \ | |
151 | } while (0) | |
152 | ||
153 | #else | |
154 | ||
155 | #define PROFILE_COUNT_SCACHE_HIT(cpu) | |
156 | #define PROFILE_COUNT_SCACHE_MISS(cpu) | |
157 | #define PROFILE_COUNT_SCACHE_CHAIN_LENGTH(cpu,length) | |
158 | #define PROFILE_COUNT_SCACHE_FULL_FLUSH(cpu) | |
159 | ||
160 | #endif | |
161 | ||
162 | #endif /* CGEN_SCACHE_H */ |