Commit | Line | Data |
---|---|---|
b9c8cd10 | 1 | /* Simulator header for Cpu tools GENerated simulators. |
61b62559 | 2 | Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. |
b9c8cd10 DE |
3 | Contributed by Cygnus Support. |
4 | ||
5 | This file is part of GDB, the GNU debugger. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License along | |
18 | with this program; if not, write to the Free Software Foundation, Inc., | |
19 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #ifndef CGEN_SIM_H | |
22 | #define CGEN_SIM_H | |
23 | ||
61b62559 DE |
24 | #include "sim-xcat.h" |
25 | ||
26 | #define PC CPU (h_pc) | |
b9c8cd10 | 27 | \f |
2c8f0de6 DE |
28 | /* Instruction field support macros. */ |
29 | ||
30 | #define EXTRACT_SIGNED(val, total, start, length) \ | |
31 | (((((val) >> ((total) - ((start) + (length)))) & ((1 << (length)) - 1)) \ | |
32 | ^ (1 << ((length) - 1))) \ | |
33 | - (1 << ((length) - 1))) | |
34 | ||
35 | #define EXTRACT_UNSIGNED(val, total, start, length) \ | |
36 | (((val) >> ((total) - ((start) + (length)))) & ((1 << (length)) - 1)) | |
37 | ||
38 | /* Compute number of longs required to hold N bits. */ | |
39 | #define HOST_LONGS_FOR_BITS(n) \ | |
40 | (((n) + sizeof (long) * 8 - 1) / sizeof (long) * 8) | |
41 | \f | |
61b62559 DE |
42 | /* Execution support. */ |
43 | ||
44 | /* Forward decls. Defined in the machine generated arch.h and cpu.h files. */ | |
45 | typedef struct argbuf ARGBUF; | |
46 | typedef struct scache SCACHE; | |
47 | typedef struct parallel_exec PARALLEL_EXEC; | |
b9c8cd10 | 48 | |
61b62559 DE |
49 | /* Types of the machine generated extract and semantic fns. */ |
50 | typedef void (EXTRACT_FN) (SIM_CPU *, PCADDR, insn_t, ARGBUF *); | |
e61871ce | 51 | /* ??? READ_FN isn't currently used anywhere, we always use a switch. */ |
61b62559 DE |
52 | typedef void (READ_FN) (SIM_CPU *, PCADDR, insn_t, PARALLEL_EXEC *); |
53 | /*typedef CIA (SEMANTIC_FN) (SEM_ARG);*/ | |
54 | typedef PCADDR (SEMANTIC_FN) (SIM_CPU *, ARGBUF *); | |
b9c8cd10 | 55 | #if 0 /* wip */ |
61b62559 | 56 | typedef void (EXTRACT_CACHE_FN) (SIM_CPU *, PCADDR, insn_t, ARGBUF *); |
b9c8cd10 | 57 | #endif |
61b62559 | 58 | typedef PCADDR (SEMANTIC_CACHE_FN) (SIM_CPU *, SCACHE *); |
b9c8cd10 DE |
59 | |
60 | typedef struct { | |
61 | /* Using cgen_insn_type requires <cpu>-opc.h. */ | |
62 | int /*enum cgen_insn_type*/ insn_type; | |
63 | const struct cgen_insn *opcode; | |
b9c8cd10 | 64 | EXTRACT_FN *extract; |
61b62559 | 65 | #ifdef HAVE_PARALLEL_EXEC |
61b62559 DE |
66 | #ifdef __GNUC__ |
67 | void *read; | |
68 | #else | |
69 | int read; | |
70 | #endif | |
61b62559 | 71 | #endif |
b9c8cd10 | 72 | SEMANTIC_FN *semantic; |
b9c8cd10 | 73 | SEMANTIC_CACHE_FN *semantic_fast; |
61b62559 DE |
74 | #if WITH_SEM_SWITCH_FULL && defined (__GNUC__) |
75 | /* Set at runtime. */ | |
76 | void *sem_full_lab; | |
77 | #endif | |
78 | #if WITH_SEM_SWITCH_FAST && defined (__GNUC__) | |
79 | /* Set at runtime. */ | |
80 | void *semantic_lab; /* FIXME: Rename to sem_fast_lab. */ | |
b9c8cd10 DE |
81 | #endif |
82 | } DECODE; | |
83 | ||
61b62559 DE |
84 | /* Execution support. |
85 | ||
86 | Semantic functions come in two versions. | |
87 | One that uses the cache, and one that doesn't. | |
88 | ??? The one that doesn't may eventually be thrown away or replaced with | |
89 | something else. */ | |
90 | ||
91 | #ifdef SCACHE_P | |
92 | ||
93 | /* instruction address */ | |
94 | typedef PCADDR IADDR; | |
95 | /* current instruction address */ | |
96 | typedef PCADDR CIA; | |
97 | /* argument to semantic functions */ | |
98 | typedef SCACHE *SEM_ARG; | |
99 | ||
100 | #else /* ! SCACHE_P */ | |
101 | ||
102 | /* instruction address */ | |
103 | typedef PCADDR IADDR; | |
104 | /* current instruction address */ | |
105 | typedef PCADDR CIA; | |
106 | /* argument to semantic functions */ | |
107 | typedef ARGBUF *SEM_ARG; | |
108 | ||
109 | #endif /* ! SCACHE_P */ | |
110 | ||
111 | /* Scache data for each cpu. */ | |
112 | ||
113 | typedef struct cpu_scache { | |
114 | /* Simulator cache size. */ | |
115 | int size; | |
116 | #define CPU_SCACHE_SIZE(cpu) ((cpu) -> cgen_cpu.scache.size) | |
117 | /* Cache. */ | |
118 | SCACHE *cache; | |
119 | #define CPU_SCACHE_CACHE(cpu) ((cpu) -> cgen_cpu.scache.cache) | |
120 | #if 0 /* FIXME: wip */ | |
121 | /* Free list. */ | |
122 | SCACHE *free; | |
123 | #define CPU_SCACHE_FREE(cpu) ((cpu) -> cgen_cpu.scache.free) | |
124 | /* Hash table. */ | |
125 | SCACHE **hash_table; | |
126 | #define CPU_SCACHE_HASH_TABLE(cpu) ((cpu) -> cgen_cpu.scache.hash_table) | |
127 | #endif | |
128 | ||
129 | #if WITH_PROFILE_SCACHE_P | |
130 | /* Cache hits, misses. */ | |
131 | unsigned long hits, misses; | |
132 | #define CPU_SCACHE_HITS(cpu) ((cpu) -> cgen_cpu.scache.hits) | |
133 | #define CPU_SCACHE_MISSES(cpu) ((cpu) -> cgen_cpu.scache.misses) | |
134 | #endif | |
135 | } CPU_SCACHE; | |
136 | ||
137 | /* Default number of cached blocks. */ | |
138 | #ifdef CONFIG_SIM_CACHE_SIZE | |
139 | #define SCACHE_DEFAULT_CACHE_SIZE CONFIG_SIM_CACHE_SIZE | |
140 | #else | |
141 | #define SCACHE_DEFAULT_CACHE_SIZE 1024 | |
142 | #endif | |
143 | ||
144 | /* Hash a PC value. */ | |
145 | /* FIXME: cpu specific */ | |
146 | #define SCACHE_HASH_PC(state, pc) \ | |
147 | (((pc) >> 1) & (STATE_SCACHE_SIZE (sd) - 1)) | |
148 | ||
149 | /* Non-zero if cache is in use. */ | |
150 | #define USING_SCACHE_P(sd) (STATE_SCACHE_SIZE (sd) > 0) | |
151 | ||
152 | /* Install the simulator cache into the simulator. */ | |
153 | MODULE_INSTALL_FN scache_install; | |
154 | ||
155 | /* Flush all cpu's caches. */ | |
156 | void scache_flush (SIM_DESC); | |
b9c8cd10 | 157 | \f |
61b62559 | 158 | /* Scache profiling support. */ |
b9c8cd10 | 159 | |
61b62559 DE |
160 | /* Print summary scache usage information. */ |
161 | void scache_print_profile (SIM_CPU *cpu, int verbose); | |
162 | ||
163 | #if WITH_PROFILE_SCACHE_P | |
164 | #define PROFILE_COUNT_SCACHE_HIT(cpu) \ | |
165 | do { \ | |
166 | if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \ | |
167 | ++ CPU_SCACHE_HITS (cpu); \ | |
168 | } while (0) | |
169 | #define PROFILE_COUNT_SCACHE_MISS(cpu) \ | |
170 | do { \ | |
171 | if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \ | |
172 | ++ CPU_SCACHE_MISSES (cpu); \ | |
173 | } while (0) | |
174 | #else | |
175 | #define PROFILE_COUNT_SCACHE_HIT(cpu) | |
176 | #define PROFILE_COUNT_SCACHE_MISS(cpu) | |
177 | #endif | |
178 | \f | |
179 | /* Engine support. */ | |
180 | ||
181 | /* Values to denote parallel/sequential execution. */ | |
182 | #define EXEC_SEQUENCE 0 | |
183 | #define EXEC_PARALLEL 1 | |
184 | ||
185 | #ifdef SCACHE_P | |
186 | ||
187 | #define CIA_ADDR(cia) (cia) | |
188 | ||
189 | /* These are used so that we can compile two copies of the semantic code, | |
190 | one with scache support and one without. */ | |
191 | /* FIXME: Do we want _ex_ or _exc_? */ | |
192 | /*#define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_exc_,fn)*/ | |
193 | #define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_ex_,fn) | |
194 | #define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semc_,fn) | |
195 | ||
196 | /* extract.c support */ | |
197 | /* scache_unset is a cache entry that is never used. | |
198 | It's raison d'etre is so BRANCH_VIA_CACHE doesn't have to test for | |
199 | newval.cache == NULL. */ | |
200 | extern struct scache scache_unset; | |
201 | #define RECORD_IADDR(fld, val) \ | |
202 | do { (fld) = (val); } while (0) | |
203 | ||
204 | /* semantics.c support */ | |
205 | #define SEM_ARGBUF(sem_arg) (&(sem_arg) -> argbuf) | |
206 | #define SEM_INSN(sem_arg) shouldnt_be_used | |
207 | #define SEM_NEXT_PC(sc) ((sc) -> next) | |
208 | #define SEM_BRANCH_VIA_CACHE(sc, newval) (newval) | |
209 | #define SEM_BRANCH_VIA_ADDR(sc, newval) (newval) | |
210 | /* Return address a branch insn will branch to. | |
211 | This is only used during tracing. */ | |
212 | #define SEM_NEW_PC_ADDR(new_pc) (new_pc) | |
213 | ||
214 | #else /* ! SCACHE_P */ | |
215 | ||
216 | #define CIA_ADDR(cia) (cia) | |
217 | ||
218 | /* These are used so that we can compile two copies of the semantic code, | |
219 | one with scache support and one without. */ | |
220 | #define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_ex_,fn) | |
221 | #define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn) | |
222 | ||
223 | /* extract.c support */ | |
224 | #define RECORD_IADDR(fld, val) \ | |
225 | do { (fld) = (val); } while (0) | |
226 | ||
227 | /* semantics.c support */ | |
228 | #define SEM_ARGBUF(sem_arg) (sem_arg) | |
229 | #define SEM_INSN(sem_arg) (SEM_ARGBUF (sem_arg) -> insn) | |
230 | #define SEM_NEXT_PC(abuf) (abuf -> addr + abuf -> length) | |
231 | #define SEM_BRANCH_VIA_CACHE(abuf, newval) (newval) | |
232 | #define SEM_BRANCH_VIA_ADDR(abuf, newval) (newval) | |
233 | #define SEM_NEW_PC_ADDR(new_pc) (new_pc) | |
234 | ||
235 | #endif /* ! SCACHE_P */ | |
236 | ||
237 | /* GNU C's "computed goto" facility is used to speed things up where | |
238 | possible. These macros provide a portable way to use them. | |
239 | Nesting of these switch statements is done by providing an extra argument | |
240 | that distinguishes them. `N' can be a number or symbol. | |
241 | Variable `labels_##N' must be initialized with the labels of each case. */ | |
242 | #ifdef __GNUC__ | |
243 | #define SWITCH(N, X) goto *X; | |
244 | #define CASE(N, X) case_##N##_##X | |
245 | #define BREAK(N) goto end_switch_##N | |
246 | #define DEFAULT(N) default_##N | |
247 | #define ENDSWITCH(N) end_switch_##N: | |
248 | #else | |
249 | #define SWITCH(N, X) switch (X) | |
250 | #define CASE(N, X) case X /* FIXME: old sem-switch had (@arch@_,X) here */ | |
251 | #define BREAK(N) break | |
252 | #define DEFAULT(N) default | |
253 | #define ENDSWITCH(N) | |
b9c8cd10 DE |
254 | #endif |
255 | ||
61b62559 DE |
256 | /* Engine control (FIXME). */ |
257 | int engine_stop (SIM_DESC); | |
258 | void engine_run (SIM_DESC, int, int); | |
259 | /*void engine_resume (SIM_DESC, int, int);*/ | |
260 | \f | |
261 | /* Simulator state. */ | |
b9c8cd10 | 262 | |
61b62559 DE |
263 | /* Records simulator descriptor so utilities like @cpu@_dump_regs can be |
264 | called from gdb. */ | |
265 | extern SIM_DESC current_state; | |
b9c8cd10 DE |
266 | |
267 | /* Simulator state. */ | |
268 | ||
61b62559 | 269 | /* CGEN_STATE contains additional state information not present in |
b9c8cd10 DE |
270 | sim_state_base. */ |
271 | ||
272 | typedef struct cgen_state { | |
61b62559 | 273 | /* FIXME: Moved to sim_state_base. */ |
b9c8cd10 DE |
274 | /* argv, env */ |
275 | char **argv; | |
61b62559 DE |
276 | #define STATE_ARGV(s) ((s) -> cgen_state.argv) |
277 | /* FIXME: Move to sim_state_base. */ | |
b9c8cd10 | 278 | char **envp; |
61b62559 DE |
279 | #define STATE_ENVP(s) ((s) -> cgen_state.envp) |
280 | ||
281 | /* Non-zero if no tracing or profiling is selected. */ | |
282 | int run_fast_p; | |
283 | #define STATE_RUN_FAST_P(sd) ((sd) -> cgen_state.run_fast_p) | |
b9c8cd10 DE |
284 | } CGEN_STATE; |
285 | ||
61b62559 DE |
286 | /* Additional non-machine generated per-cpu data to go in SIM_CPU. |
287 | The member's name must be `cgen_cpu'. */ | |
b9c8cd10 DE |
288 | |
289 | typedef struct { | |
290 | /* Simulator's execution cache. */ | |
291 | #if WITH_SCACHE | |
292 | CPU_SCACHE scache; | |
293 | #endif /* WITH_SCACHE */ | |
294 | ||
61b62559 DE |
295 | /* Allow slop in size calcs for case where multiple cpu types are supported |
296 | and space for the specified cpu is malloc'd at run time. */ | |
297 | double slop; | |
b9c8cd10 DE |
298 | } CGEN_CPU; |
299 | \f | |
300 | /* Various utilities. */ | |
301 | ||
61b62559 DE |
302 | /* Called after sim_post_argv_init to do any cgen initialization. */ |
303 | void cgen_init (SIM_DESC); | |
b9c8cd10 DE |
304 | |
305 | void | |
61b62559 DE |
306 | sim_disassemble_insn (SIM_CPU *, const struct cgen_insn *, |
307 | const struct argbuf *, PCADDR, char *); | |
b9c8cd10 DE |
308 | |
309 | #endif /* CGEN_SIM_H */ |