[deliverable/binutils-gdb.git] / sim / common / cgen-sim.h

/* Simulator header for Cpu tools GENerated simulators.
   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   Contributed by Cygnus Support.

This file is part of GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#ifndef CGEN_SIM_H
#define CGEN_SIM_H

#include "sim-xcat.h"

#define PC CPU (h_pc)
\f
/* Instruction field support macros.  */

#define EXTRACT_SIGNED(val, total, start, length) \
(((((val) >> ((total) - ((start) + (length)))) & ((1 << (length)) - 1)) \
  ^ (1 << ((length) - 1))) \
 - (1 << ((length) - 1)))

#define EXTRACT_UNSIGNED(val, total, start, length) \
(((val) >> ((total) - ((start) + (length)))) & ((1 << (length)) - 1))

/* Compute number of longs required to hold N bits.  */
#define HOST_LONGS_FOR_BITS(n) \
  (((n) + sizeof (long) * 8 - 1) / sizeof (long) * 8)
\f
/* Execution support.  */

/* Forward decls.  Defined in the machine generated arch.h and cpu.h files.  */
typedef struct argbuf ARGBUF;
typedef struct scache SCACHE;
typedef struct parallel_exec PARALLEL_EXEC;

/* Types of the machine generated extract and semantic fns.  */
typedef void (EXTRACT_FN) (SIM_CPU *, PCADDR, insn_t, ARGBUF *);
typedef void (READ_FN) (SIM_CPU *, PCADDR, insn_t, PARALLEL_EXEC *);
/*typedef CIA (SEMANTIC_FN) (SEM_ARG);*/
typedef PCADDR (SEMANTIC_FN) (SIM_CPU *, ARGBUF *);
#if 0 /* wip */
typedef void (EXTRACT_CACHE_FN) (SIM_CPU *, PCADDR, insn_t, ARGBUF *);
#endif
typedef PCADDR (SEMANTIC_CACHE_FN) (SIM_CPU *, SCACHE *);

typedef struct {
  /* Using cgen_insn_type requires <cpu>-opc.h.  */
  int /*enum cgen_insn_type*/ insn_type;
  const struct cgen_insn *opcode;
  EXTRACT_FN *extract;
#ifdef HAVE_PARALLEL_EXEC
#ifdef USE_READ_SWITCH
#ifdef __GNUC__
  void *read;
#else
  int read;
#endif
#else
  READ_FN *read;
#endif
#endif
  SEMANTIC_FN *semantic;
#if 0 /* wip */
  EXTRACT_CACHE_FN *extract_fast;
#endif
  SEMANTIC_CACHE_FN *semantic_fast;
#if WITH_SEM_SWITCH_FULL && defined (__GNUC__)
  /* Set at runtime.  */
  void *sem_full_lab;
#endif
#if WITH_SEM_SWITCH_FAST && defined (__GNUC__)
  /* Set at runtime.  */
  void *semantic_lab; /* FIXME: Rename to sem_fast_lab.  */
#endif
} DECODE;

/* Execution support.

   Semantic functions come in two versions.
   One that uses the cache, and one that doesn't.
   ??? The one that doesn't may eventually be thrown away or replaced with
   something else.  */

#ifdef SCACHE_P

/* instruction address */
typedef PCADDR IADDR;
/* current instruction address */
typedef PCADDR CIA;
/* argument to semantic functions */
typedef SCACHE *SEM_ARG;

#else /* ! SCACHE_P */

/* instruction address */
typedef PCADDR IADDR;
/* current instruction address */
typedef PCADDR CIA;
/* argument to semantic functions */
typedef ARGBUF *SEM_ARG;

#endif /* ! SCACHE_P */

/* Scache data for each cpu.  */

typedef struct cpu_scache {
  /* Simulator cache size.  */
  int size;
#define CPU_SCACHE_SIZE(cpu) ((cpu) -> cgen_cpu.scache.size)
  /* Cache.  */
  SCACHE *cache;
#define CPU_SCACHE_CACHE(cpu) ((cpu) -> cgen_cpu.scache.cache)
#if 0 /* FIXME: wip */
  /* Free list.  */
  SCACHE *free;
#define CPU_SCACHE_FREE(cpu) ((cpu) -> cgen_cpu.scache.free)
  /* Hash table.  */
  SCACHE **hash_table;
#define CPU_SCACHE_HASH_TABLE(cpu) ((cpu) -> cgen_cpu.scache.hash_table)
#endif

#if WITH_PROFILE_SCACHE_P
  /* Cache hits, misses.  */
  unsigned long hits, misses;
#define CPU_SCACHE_HITS(cpu) ((cpu) -> cgen_cpu.scache.hits)
#define CPU_SCACHE_MISSES(cpu) ((cpu) -> cgen_cpu.scache.misses)
#endif
} CPU_SCACHE;

/* Default number of cached blocks.  */
#ifdef CONFIG_SIM_CACHE_SIZE
#define SCACHE_DEFAULT_CACHE_SIZE CONFIG_SIM_CACHE_SIZE
#else
#define SCACHE_DEFAULT_CACHE_SIZE 1024
#endif

/* Hash a PC value.  */
/* FIXME: cpu specific */
#define SCACHE_HASH_PC(state, pc) \
(((pc) >> 1) & (STATE_SCACHE_SIZE (sd) - 1))

/* Non-zero if cache is in use.  */
#define USING_SCACHE_P(sd) (STATE_SCACHE_SIZE (sd) > 0)

/* Install the simulator cache into the simulator.  */
MODULE_INSTALL_FN scache_install;

/* Flush all cpu's caches.  */
void scache_flush (SIM_DESC);
\f
/* Scache profiling support.  */

/* Print summary scache usage information.  */
void scache_print_profile (SIM_CPU *cpu, int verbose);

#if WITH_PROFILE_SCACHE_P
#define PROFILE_COUNT_SCACHE_HIT(cpu) \
do { \
  if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \
    ++ CPU_SCACHE_HITS (cpu); \
} while (0)
#define PROFILE_COUNT_SCACHE_MISS(cpu) \
do { \
  if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \
    ++ CPU_SCACHE_MISSES (cpu); \
} while (0)
#else
#define PROFILE_COUNT_SCACHE_HIT(cpu)
#define PROFILE_COUNT_SCACHE_MISS(cpu)
#endif
\f
/* Engine support.  */

/* Values to denote parallel/sequential execution.  */
#define EXEC_SEQUENCE 0
#define EXEC_PARALLEL 1

#ifdef SCACHE_P

#define CIA_ADDR(cia) (cia)

/* These are used so that we can compile two copies of the semantic code,
   one with scache support and one without.  */
/* FIXME: Do we want _ex_ or _exc_?  */
/*#define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_exc_,fn)*/
#define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_ex_,fn)
#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semc_,fn)

/* extract.c support */
/* scache_unset is a cache entry that is never used.
   It's raison d'etre is so BRANCH_VIA_CACHE doesn't have to test for
   newval.cache == NULL.  */
extern struct scache scache_unset;
#define RECORD_IADDR(fld, val) \
do { (fld) = (val); } while (0)

/* semantics.c support */
#define SEM_ARGBUF(sem_arg) (&(sem_arg) -> argbuf)
#define SEM_INSN(sem_arg) shouldnt_be_used
#define SEM_NEXT_PC(sc) ((sc) -> next)
#define SEM_BRANCH_VIA_CACHE(sc, newval) (newval)
#define SEM_BRANCH_VIA_ADDR(sc, newval) (newval)
/* Return address a branch insn will branch to.
   This is only used during tracing.  */
#define SEM_NEW_PC_ADDR(new_pc) (new_pc)

#else /* ! SCACHE_P */

#define CIA_ADDR(cia) (cia)

/* These are used so that we can compile two copies of the semantic code,
   one with scache support and one without.  */
#define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_ex_,fn)
#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)

/* extract.c support */
#define RECORD_IADDR(fld, val) \
do { (fld) = (val); } while (0)

/* semantics.c support */
#define SEM_ARGBUF(sem_arg) (sem_arg)
#define SEM_INSN(sem_arg) (SEM_ARGBUF (sem_arg) -> insn)
#define SEM_NEXT_PC(abuf) (abuf -> addr + abuf -> length)
#define SEM_BRANCH_VIA_CACHE(abuf, newval) (newval)
#define SEM_BRANCH_VIA_ADDR(abuf, newval) (newval)
#define SEM_NEW_PC_ADDR(new_pc) (new_pc)

#endif /* ! SCACHE_P */

/* GNU C's "computed goto" facility is used to speed things up where
   possible.  These macros provide a portable way to use them.
   Nesting of these switch statements is done by providing an extra argument
   that distinguishes them.  `N' can be a number or symbol.
   Variable `labels_##N' must be initialized with the labels of each case.  */
#ifdef __GNUC__
#define SWITCH(N, X) goto *X;
#define CASE(N, X) case_##N##_##X
#define BREAK(N) goto end_switch_##N
#define DEFAULT(N) default_##N
#define ENDSWITCH(N) end_switch_##N:
#else
#define SWITCH(N, X) switch (X)
#define CASE(N, X) case X /* FIXME: old sem-switch had (@arch@_,X) here */
#define BREAK(N) break
#define DEFAULT(N) default
#define ENDSWITCH(N)
#endif

/* Engine control (FIXME).  */
int engine_stop (SIM_DESC);
void engine_run (SIM_DESC, int, int);
/*void engine_resume (SIM_DESC, int, int);*/
\f
/* Simulator state.  */

/* Records simulator descriptor so utilities like @cpu@_dump_regs can be
   called from gdb.  */
extern SIM_DESC current_state;

/* Simulator state.  */

/* CGEN_STATE contains additional state information not present in
   sim_state_base.  */

typedef struct cgen_state {
  /* FIXME: Moved to sim_state_base.  */
  /* argv, env */
  char **argv;
#define STATE_ARGV(s) ((s) -> cgen_state.argv)
  /* FIXME: Move to sim_state_base.  */
  char **envp;
#define STATE_ENVP(s) ((s) -> cgen_state.envp)

  /* Non-zero if no tracing or profiling is selected.  */
  int run_fast_p;
#define STATE_RUN_FAST_P(sd) ((sd) -> cgen_state.run_fast_p)
} CGEN_STATE;

/* Additional non-machine generated per-cpu data to go in SIM_CPU.
   The member's name must be `cgen_cpu'.  */

typedef struct {
  /* Simulator's execution cache.  */
#if WITH_SCACHE
  CPU_SCACHE scache;
#endif /* WITH_SCACHE */

  /* Allow slop in size calcs for case where multiple cpu types are supported
     and space for the specified cpu is malloc'd at run time.  */
  double slop;
} CGEN_CPU;
\f
/* Various utilities.  */

/* Called after sim_post_argv_init to do any cgen initialization.  */
void cgen_init (SIM_DESC);

void
sim_disassemble_insn (SIM_CPU *, const struct cgen_insn *,
		      const struct argbuf *, PCADDR, char *);

#endif /* CGEN_SIM_H */
Commit	Line	Data
b9c8cd10	1	/* Simulator header for Cpu tools GENerated simulators.
61b62559	2	Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
b9c8cd10 DE	3	Contributed by Cygnus Support.
	4
	5	This file is part of GDB, the GNU debugger.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 2, or (at your option)
	10	any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License along
	18	with this program; if not, write to the Free Software Foundation, Inc.,
	19	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	20
	21	#ifndef CGEN_SIM_H
	22	#define CGEN_SIM_H
	23
61b62559 DE	24	#include "sim-xcat.h"
	25
	26	#define PC CPU (h_pc)
b9c8cd10	27	\f
2c8f0de6 DE	28	/* Instruction field support macros. */
	29
	30	#define EXTRACT_SIGNED(val, total, start, length) \
	31	(((((val) >> ((total) - ((start) + (length)))) & ((1 << (length)) - 1)) \
	32	^ (1 << ((length) - 1))) \
	33	- (1 << ((length) - 1)))
	34
	35	#define EXTRACT_UNSIGNED(val, total, start, length) \
	36	(((val) >> ((total) - ((start) + (length)))) & ((1 << (length)) - 1))
	37
	38	/* Compute number of longs required to hold N bits. */
	39	#define HOST_LONGS_FOR_BITS(n) \
	40	(((n) + sizeof (long) * 8 - 1) / sizeof (long) * 8)
	41	\f
61b62559 DE	42	/* Execution support. */
	43
	44	/* Forward decls. Defined in the machine generated arch.h and cpu.h files. */
	45	typedef struct argbuf ARGBUF;
	46	typedef struct scache SCACHE;
	47	typedef struct parallel_exec PARALLEL_EXEC;
b9c8cd10	48
61b62559 DE	49	/* Types of the machine generated extract and semantic fns. */
	50	typedef void (EXTRACT_FN) (SIM_CPU , PCADDR, insn_t, ARGBUF );
	51	typedef void (READ_FN) (SIM_CPU , PCADDR, insn_t, PARALLEL_EXEC );
	52	/typedef CIA (SEMANTIC_FN) (SEM_ARG);/
	53	typedef PCADDR (SEMANTIC_FN) (SIM_CPU , ARGBUF );
b9c8cd10	54	#if 0 /* wip */
61b62559	55	typedef void (EXTRACT_CACHE_FN) (SIM_CPU , PCADDR, insn_t, ARGBUF );
b9c8cd10	56	#endif
61b62559	57	typedef PCADDR (SEMANTIC_CACHE_FN) (SIM_CPU , SCACHE );
b9c8cd10 DE	58
	59	typedef struct {
	60	/* Using cgen_insn_type requires <cpu>-opc.h. */
	61	int /enum cgen_insn_type/ insn_type;
	62	const struct cgen_insn *opcode;
b9c8cd10	63	EXTRACT_FN *extract;
61b62559 DE	64	#ifdef HAVE_PARALLEL_EXEC
	65	#ifdef USE_READ_SWITCH
	66	#ifdef __GNUC__
	67	void *read;
	68	#else
	69	int read;
	70	#endif
	71	#else
	72	READ_FN *read;
	73	#endif
	74	#endif
b9c8cd10 DE	75	SEMANTIC_FN *semantic;
	76	#if 0 /* wip */
	77	EXTRACT_CACHE_FN *extract_fast;
	78	#endif
	79	SEMANTIC_CACHE_FN *semantic_fast;
61b62559 DE	80	#if WITH_SEM_SWITCH_FULL && defined (__GNUC__)
	81	/* Set at runtime. */
	82	void *sem_full_lab;
	83	#endif
	84	#if WITH_SEM_SWITCH_FAST && defined (__GNUC__)
	85	/* Set at runtime. */
	86	void semantic_lab; / FIXME: Rename to sem_fast_lab. */
b9c8cd10 DE	87	#endif
	88	} DECODE;
	89
61b62559 DE	90	/* Execution support.
	91
	92	Semantic functions come in two versions.
	93	One that uses the cache, and one that doesn't.
	94	??? The one that doesn't may eventually be thrown away or replaced with
	95	something else. */
	96
	97	#ifdef SCACHE_P
	98
	99	/* instruction address */
	100	typedef PCADDR IADDR;
	101	/* current instruction address */
	102	typedef PCADDR CIA;
	103	/* argument to semantic functions */
	104	typedef SCACHE *SEM_ARG;
	105
	106	#else /* ! SCACHE_P */
	107
	108	/* instruction address */
	109	typedef PCADDR IADDR;
	110	/* current instruction address */
	111	typedef PCADDR CIA;
	112	/* argument to semantic functions */
	113	typedef ARGBUF *SEM_ARG;
	114
	115	#endif /* ! SCACHE_P */
	116
	117	/* Scache data for each cpu. */
	118
	119	typedef struct cpu_scache {
	120	/* Simulator cache size. */
	121	int size;
	122	#define CPU_SCACHE_SIZE(cpu) ((cpu) -> cgen_cpu.scache.size)
	123	/* Cache. */
	124	SCACHE *cache;
	125	#define CPU_SCACHE_CACHE(cpu) ((cpu) -> cgen_cpu.scache.cache)
	126	#if 0 /* FIXME: wip */
	127	/* Free list. */
	128	SCACHE *free;
	129	#define CPU_SCACHE_FREE(cpu) ((cpu) -> cgen_cpu.scache.free)
	130	/* Hash table. */
	131	SCACHE **hash_table;
	132	#define CPU_SCACHE_HASH_TABLE(cpu) ((cpu) -> cgen_cpu.scache.hash_table)
	133	#endif
	134
	135	#if WITH_PROFILE_SCACHE_P
	136	/* Cache hits, misses. */
	137	unsigned long hits, misses;
	138	#define CPU_SCACHE_HITS(cpu) ((cpu) -> cgen_cpu.scache.hits)
	139	#define CPU_SCACHE_MISSES(cpu) ((cpu) -> cgen_cpu.scache.misses)
	140	#endif
	141	} CPU_SCACHE;
	142
	143	/* Default number of cached blocks. */
	144	#ifdef CONFIG_SIM_CACHE_SIZE
	145	#define SCACHE_DEFAULT_CACHE_SIZE CONFIG_SIM_CACHE_SIZE
	146	#else
	147	#define SCACHE_DEFAULT_CACHE_SIZE 1024
	148	#endif
	149
	150	/* Hash a PC value. */
	151	/* FIXME: cpu specific */
	152	#define SCACHE_HASH_PC(state, pc) \
	153	(((pc) >> 1) & (STATE_SCACHE_SIZE (sd) - 1))
154
155	/* Non-zero if cache is in use. */
156	#define USING_SCACHE_P(sd) (STATE_SCACHE_SIZE (sd) > 0)
157
158	/* Install the simulator cache into the simulator. */
159	MODULE_INSTALL_FN scache_install;
160
161	/* Flush all cpu's caches. */
162	void scache_flush (SIM_DESC);
b9c8cd10	163	\f
61b62559	164	/* Scache profiling support. */
b9c8cd10	165
61b62559 DE	166	/* Print summary scache usage information. */
	167	void scache_print_profile (SIM_CPU *cpu, int verbose);
	168
	169	#if WITH_PROFILE_SCACHE_P
	170	#define PROFILE_COUNT_SCACHE_HIT(cpu) \
	171	do { \
	172	if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \
	173	++ CPU_SCACHE_HITS (cpu); \
	174	} while (0)
	175	#define PROFILE_COUNT_SCACHE_MISS(cpu) \
	176	do { \
	177	if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \
	178	++ CPU_SCACHE_MISSES (cpu); \
	179	} while (0)
	180	#else
	181	#define PROFILE_COUNT_SCACHE_HIT(cpu)
	182	#define PROFILE_COUNT_SCACHE_MISS(cpu)
	183	#endif
	184	\f
	185	/* Engine support. */
	186
	187	/* Values to denote parallel/sequential execution. */
	188	#define EXEC_SEQUENCE 0
	189	#define EXEC_PARALLEL 1
	190
	191	#ifdef SCACHE_P
	192
	193	#define CIA_ADDR(cia) (cia)
	194
	195	/* These are used so that we can compile two copies of the semantic code,
	196	one with scache support and one without. */
	197	/* FIXME: Do we want _ex_ or _exc_? */
	198	/#define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_exc_,fn)/
	199	#define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_ex_,fn)
	200	#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semc_,fn)
	201
	202	/* extract.c support */
	203	/* scache_unset is a cache entry that is never used.
	204	It's raison d'etre is so BRANCH_VIA_CACHE doesn't have to test for
	205	newval.cache == NULL. */
	206	extern struct scache scache_unset;
	207	#define RECORD_IADDR(fld, val) \
	208	do { (fld) = (val); } while (0)
	209
	210	/* semantics.c support */
	211	#define SEM_ARGBUF(sem_arg) (&(sem_arg) -> argbuf)
	212	#define SEM_INSN(sem_arg) shouldnt_be_used
	213	#define SEM_NEXT_PC(sc) ((sc) -> next)
	214	#define SEM_BRANCH_VIA_CACHE(sc, newval) (newval)
	215	#define SEM_BRANCH_VIA_ADDR(sc, newval) (newval)
	216	/* Return address a branch insn will branch to.
	217	This is only used during tracing. */
	218	#define SEM_NEW_PC_ADDR(new_pc) (new_pc)
	219
	220	#else /* ! SCACHE_P */
	221
	222	#define CIA_ADDR(cia) (cia)
	223
	224	/* These are used so that we can compile two copies of the semantic code,
	225	one with scache support and one without. */
	226	#define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_ex_,fn)
	227	#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
	228
	229	/* extract.c support */
230	#define RECORD_IADDR(fld, val) \
231	do { (fld) = (val); } while (0)
232
233	/* semantics.c support */
234	#define SEM_ARGBUF(sem_arg) (sem_arg)
235	#define SEM_INSN(sem_arg) (SEM_ARGBUF (sem_arg) -> insn)
236	#define SEM_NEXT_PC(abuf) (abuf -> addr + abuf -> length)
237	#define SEM_BRANCH_VIA_CACHE(abuf, newval) (newval)
238	#define SEM_BRANCH_VIA_ADDR(abuf, newval) (newval)
239	#define SEM_NEW_PC_ADDR(new_pc) (new_pc)
240
241	#endif /* ! SCACHE_P */
242
243	/* GNU C's "computed goto" facility is used to speed things up where
244	possible. These macros provide a portable way to use them.
245	Nesting of these switch statements is done by providing an extra argument
246	that distinguishes them. `N' can be a number or symbol.
247	Variable `labels_##N' must be initialized with the labels of each case. */
248	#ifdef __GNUC__
249	#define SWITCH(N, X) goto *X;
250	#define CASE(N, X) case_##N##_##X
251	#define BREAK(N) goto end_switch_##N
252	#define DEFAULT(N) default_##N
253	#define ENDSWITCH(N) end_switch_##N:
254	#else
255	#define SWITCH(N, X) switch (X)
256	#define CASE(N, X) case X /* FIXME: old sem-switch had (@arch@_,X) here */
257	#define BREAK(N) break
258	#define DEFAULT(N) default
259	#define ENDSWITCH(N)
b9c8cd10 DE	260	#endif
b9c8cd10 DE	261
61b62559 DE	262	/* Engine control (FIXME). */
	263	int engine_stop (SIM_DESC);
	264	void engine_run (SIM_DESC, int, int);
	265	/void engine_resume (SIM_DESC, int, int);/
	266	\f
	267	/* Simulator state. */
b9c8cd10	268
61b62559 DE	269	/* Records simulator descriptor so utilities like @cpu@_dump_regs can be
	270	called from gdb. */
	271	extern SIM_DESC current_state;
b9c8cd10 DE	272
	273	/* Simulator state. */
	274
61b62559	275	/* CGEN_STATE contains additional state information not present in
b9c8cd10 DE	276	sim_state_base. */
	277
	278	typedef struct cgen_state {
61b62559	279	/* FIXME: Moved to sim_state_base. */
b9c8cd10 DE	280	/* argv, env */
b9c8cd10 DE	281	char **argv;
61b62559 DE	282	#define STATE_ARGV(s) ((s) -> cgen_state.argv)
61b62559 DE	283	/* FIXME: Move to sim_state_base. */
b9c8cd10	284	char **envp;
61b62559 DE	285	#define STATE_ENVP(s) ((s) -> cgen_state.envp)
	286
	287	/* Non-zero if no tracing or profiling is selected. */
	288	int run_fast_p;
	289	#define STATE_RUN_FAST_P(sd) ((sd) -> cgen_state.run_fast_p)
b9c8cd10 DE	290	} CGEN_STATE;
b9c8cd10 DE	291
61b62559 DE	292	/* Additional non-machine generated per-cpu data to go in SIM_CPU.
61b62559 DE	293	The member's name must be `cgen_cpu'. */
b9c8cd10 DE	294
	295	typedef struct {
	296	/* Simulator's execution cache. */
	297	#if WITH_SCACHE
	298	CPU_SCACHE scache;
	299	#endif /* WITH_SCACHE */
	300
61b62559 DE	301	/* Allow slop in size calcs for case where multiple cpu types are supported
	302	and space for the specified cpu is malloc'd at run time. */
	303	double slop;
b9c8cd10 DE	304	} CGEN_CPU;
	305	\f
	306	/* Various utilities. */
	307
61b62559 DE	308	/* Called after sim_post_argv_init to do any cgen initialization. */
61b62559 DE	309	void cgen_init (SIM_DESC);
b9c8cd10 DE	310
b9c8cd10 DE	311	void
61b62559 DE	312	sim_disassemble_insn (SIM_CPU , const struct cgen_insn ,
61b62559 DE	313	const struct argbuf , PCADDR, char );
b9c8cd10 DE	314
b9c8cd10 DE	315	#endif /* CGEN_SIM_H */