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b85e4829 AC |
1 | /* The common simulator framework for GDB, the GNU Debugger. |
2 | ||
3 | Copyright 2002 Free Software Foundation, Inc. | |
4 | ||
5 | Contributed by Andrew Cagney and Red Hat. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 59 Temple Place - Suite 330, | |
22 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
23 | |
24 | ||
25 | #ifndef SIM_CORE_C | |
26 | #define SIM_CORE_C | |
27 | ||
28 | #include "sim-main.h" | |
29 | #include "sim-assert.h" | |
30 | ||
31 | #if (WITH_HW) | |
32 | #include "sim-hw.h" | |
33 | #endif | |
34 | ||
c906108c SS |
35 | /* "core" module install handler. |
36 | ||
37 | This is called via sim_module_install to install the "core" | |
38 | subsystem into the simulator. */ | |
39 | ||
40 | #if EXTERN_SIM_CORE_P | |
41 | static MODULE_INIT_FN sim_core_init; | |
42 | static MODULE_UNINSTALL_FN sim_core_uninstall; | |
43 | #endif | |
44 | ||
45 | #if EXTERN_SIM_CORE_P | |
46 | SIM_RC | |
47 | sim_core_install (SIM_DESC sd) | |
48 | { | |
49 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); | |
50 | ||
51 | /* establish the other handlers */ | |
52 | sim_module_add_uninstall_fn (sd, sim_core_uninstall); | |
53 | sim_module_add_init_fn (sd, sim_core_init); | |
54 | ||
55 | /* establish any initial data structures - none */ | |
56 | return SIM_RC_OK; | |
57 | } | |
58 | #endif | |
59 | ||
60 | ||
61 | /* Uninstall the "core" subsystem from the simulator. */ | |
62 | ||
63 | #if EXTERN_SIM_CORE_P | |
64 | static void | |
65 | sim_core_uninstall (SIM_DESC sd) | |
66 | { | |
67 | sim_core *core = STATE_CORE(sd); | |
68 | unsigned map; | |
69 | /* blow away any mappings */ | |
70 | for (map = 0; map < nr_maps; map++) { | |
71 | sim_core_mapping *curr = core->common.map[map].first; | |
72 | while (curr != NULL) { | |
73 | sim_core_mapping *tbd = curr; | |
74 | curr = curr->next; | |
75 | if (tbd->free_buffer != NULL) { | |
76 | SIM_ASSERT(tbd->buffer != NULL); | |
77 | zfree(tbd->free_buffer); | |
78 | } | |
79 | zfree(tbd); | |
80 | } | |
81 | core->common.map[map].first = NULL; | |
82 | } | |
83 | } | |
84 | #endif | |
85 | ||
86 | ||
87 | #if EXTERN_SIM_CORE_P | |
88 | static SIM_RC | |
89 | sim_core_init (SIM_DESC sd) | |
90 | { | |
91 | /* Nothing to do */ | |
92 | return SIM_RC_OK; | |
93 | } | |
94 | #endif | |
95 | ||
96 | ||
97 | ||
98 | #ifndef SIM_CORE_SIGNAL | |
99 | #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ | |
100 | sim_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR)) | |
101 | #endif | |
102 | ||
103 | #if EXTERN_SIM_CORE_P | |
104 | void | |
105 | sim_core_signal (SIM_DESC sd, | |
106 | sim_cpu *cpu, | |
107 | sim_cia cia, | |
108 | unsigned map, | |
109 | int nr_bytes, | |
110 | address_word addr, | |
111 | transfer_type transfer, | |
112 | sim_core_signals sig) | |
113 | { | |
114 | const char *copy = (transfer == read_transfer ? "read" : "write"); | |
115 | address_word ip = CIA_ADDR (cia); | |
116 | switch (sig) | |
117 | { | |
118 | case sim_core_unmapped_signal: | |
119 | sim_io_eprintf (sd, "core: %d byte %s to unmapped address 0x%lx at 0x%lx\n", | |
120 | nr_bytes, copy, (unsigned long) addr, (unsigned long) ip); | |
121 | sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGSEGV); | |
122 | break; | |
123 | case sim_core_unaligned_signal: | |
124 | sim_io_eprintf (sd, "core: %d byte misaligned %s to address 0x%lx at 0x%lx\n", | |
125 | nr_bytes, copy, (unsigned long) addr, (unsigned long) ip); | |
126 | sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGBUS); | |
127 | break; | |
128 | default: | |
129 | sim_engine_abort (sd, cpu, cia, | |
130 | "sim_core_signal - internal error - bad switch"); | |
131 | } | |
132 | } | |
133 | #endif | |
134 | ||
135 | ||
136 | #if EXTERN_SIM_CORE_P | |
137 | static sim_core_mapping * | |
138 | new_sim_core_mapping (SIM_DESC sd, | |
139 | int level, | |
140 | int space, | |
141 | address_word addr, | |
142 | address_word nr_bytes, | |
143 | unsigned modulo, | |
144 | #if WITH_HW | |
145 | struct hw *device, | |
146 | #else | |
147 | device *device, | |
148 | #endif | |
149 | void *buffer, | |
150 | void *free_buffer) | |
151 | { | |
152 | sim_core_mapping *new_mapping = ZALLOC(sim_core_mapping); | |
153 | /* common */ | |
154 | new_mapping->level = level; | |
155 | new_mapping->space = space; | |
156 | new_mapping->base = addr; | |
157 | new_mapping->nr_bytes = nr_bytes; | |
158 | new_mapping->bound = addr + (nr_bytes - 1); | |
159 | if (modulo == 0) | |
160 | new_mapping->mask = (unsigned) 0 - 1; | |
161 | else | |
162 | new_mapping->mask = modulo - 1; | |
163 | new_mapping->buffer = buffer; | |
164 | new_mapping->free_buffer = free_buffer; | |
165 | new_mapping->device = device; | |
166 | return new_mapping; | |
167 | } | |
168 | #endif | |
169 | ||
170 | ||
171 | #if EXTERN_SIM_CORE_P | |
172 | static void | |
173 | sim_core_map_attach (SIM_DESC sd, | |
174 | sim_core_map *access_map, | |
175 | int level, | |
176 | int space, | |
177 | address_word addr, | |
178 | address_word nr_bytes, | |
179 | unsigned modulo, | |
180 | #if WITH_HW | |
181 | struct hw *client, /*callback/default*/ | |
182 | #else | |
183 | device *client, /*callback/default*/ | |
184 | #endif | |
185 | void *buffer, /*raw_memory*/ | |
186 | void *free_buffer) /*raw_memory*/ | |
187 | { | |
188 | /* find the insertion point for this additional mapping and then | |
189 | insert */ | |
190 | sim_core_mapping *next_mapping; | |
191 | sim_core_mapping **last_mapping; | |
192 | ||
193 | SIM_ASSERT ((client == NULL) != (buffer == NULL)); | |
194 | SIM_ASSERT ((client == NULL) >= (free_buffer != NULL)); | |
195 | ||
196 | /* actually do occasionally get a zero size map */ | |
197 | if (nr_bytes == 0) | |
198 | { | |
199 | #if (WITH_DEVICES) | |
200 | device_error(client, "called on sim_core_map_attach with size zero"); | |
201 | #endif | |
202 | #if (WITH_HW) | |
203 | sim_hw_abort (sd, client, "called on sim_core_map_attach with size zero"); | |
204 | #endif | |
205 | sim_io_error (sd, "called on sim_core_map_attach with size zero"); | |
206 | } | |
207 | ||
208 | /* find the insertion point (between last/next) */ | |
209 | next_mapping = access_map->first; | |
210 | last_mapping = &access_map->first; | |
211 | while(next_mapping != NULL | |
212 | && (next_mapping->level < level | |
213 | || (next_mapping->level == level | |
214 | && next_mapping->bound < addr))) | |
215 | { | |
216 | /* provided levels are the same */ | |
217 | /* assert: next_mapping->base > all bases before next_mapping */ | |
218 | /* assert: next_mapping->bound >= all bounds before next_mapping */ | |
219 | last_mapping = &next_mapping->next; | |
220 | next_mapping = next_mapping->next; | |
221 | } | |
222 | ||
223 | /* check insertion point correct */ | |
224 | SIM_ASSERT (next_mapping == NULL || next_mapping->level >= level); | |
225 | if (next_mapping != NULL && next_mapping->level == level | |
226 | && next_mapping->base < (addr + (nr_bytes - 1))) | |
227 | { | |
228 | #if (WITH_DEVICES) | |
229 | device_error (client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)", | |
230 | space, | |
231 | (long) addr, | |
35c20992 | 232 | (long) (addr + nr_bytes - 1), |
c906108c | 233 | (long) nr_bytes, |
c906108c SS |
234 | next_mapping->space, |
235 | (long) next_mapping->base, | |
236 | (long) next_mapping->bound, | |
237 | (long) next_mapping->nr_bytes); | |
238 | #endif | |
239 | #if WITH_HW | |
240 | sim_hw_abort (sd, client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)", | |
241 | space, | |
242 | (long) addr, | |
c906108c | 243 | (long) (addr + (nr_bytes - 1)), |
35c20992 | 244 | (long) nr_bytes, |
c906108c SS |
245 | next_mapping->space, |
246 | (long) next_mapping->base, | |
247 | (long) next_mapping->bound, | |
248 | (long) next_mapping->nr_bytes); | |
249 | #endif | |
250 | sim_io_error (sd, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)", | |
251 | space, | |
252 | (long) addr, | |
c906108c | 253 | (long) (addr + (nr_bytes - 1)), |
35c20992 | 254 | (long) nr_bytes, |
c906108c SS |
255 | next_mapping->space, |
256 | (long) next_mapping->base, | |
257 | (long) next_mapping->bound, | |
258 | (long) next_mapping->nr_bytes); | |
259 | } | |
260 | ||
261 | /* create/insert the new mapping */ | |
262 | *last_mapping = new_sim_core_mapping(sd, | |
263 | level, | |
264 | space, addr, nr_bytes, modulo, | |
265 | client, buffer, free_buffer); | |
266 | (*last_mapping)->next = next_mapping; | |
267 | } | |
268 | #endif | |
269 | ||
270 | ||
271 | /* Attach memory or a memory mapped device to the simulator. | |
272 | See sim-core.h for a full description. */ | |
273 | ||
274 | #if EXTERN_SIM_CORE_P | |
275 | void | |
276 | sim_core_attach (SIM_DESC sd, | |
277 | sim_cpu *cpu, | |
278 | int level, | |
279 | unsigned mapmask, | |
280 | int space, | |
281 | address_word addr, | |
282 | address_word nr_bytes, | |
283 | unsigned modulo, | |
284 | #if WITH_HW | |
285 | struct hw *client, | |
286 | #else | |
287 | device *client, | |
288 | #endif | |
289 | void *optional_buffer) | |
290 | { | |
291 | sim_core *memory = STATE_CORE(sd); | |
292 | unsigned map; | |
293 | void *buffer; | |
294 | void *free_buffer; | |
295 | ||
296 | /* check for for attempt to use unimplemented per-processor core map */ | |
297 | if (cpu != NULL) | |
298 | sim_io_error (sd, "sim_core_map_attach - processor specific memory map not yet supported"); | |
299 | ||
300 | /* verify modulo memory */ | |
301 | if (!WITH_MODULO_MEMORY && modulo != 0) | |
302 | { | |
303 | #if (WITH_DEVICES) | |
304 | device_error (client, "sim_core_attach - internal error - modulo memory disabled"); | |
305 | #endif | |
306 | #if (WITH_HW) | |
307 | sim_hw_abort (sd, client, "sim_core_attach - internal error - modulo memory disabled"); | |
308 | #endif | |
309 | sim_io_error (sd, "sim_core_attach - internal error - modulo memory disabled"); | |
310 | } | |
311 | if (client != NULL && modulo != 0) | |
312 | { | |
313 | #if (WITH_DEVICES) | |
314 | device_error (client, "sim_core_attach - internal error - modulo and callback memory conflict"); | |
315 | #endif | |
316 | #if (WITH_HW) | |
317 | sim_hw_abort (sd, client, "sim_core_attach - internal error - modulo and callback memory conflict"); | |
318 | #endif | |
319 | sim_io_error (sd, "sim_core_attach - internal error - modulo and callback memory conflict"); | |
320 | } | |
321 | if (modulo != 0) | |
322 | { | |
323 | unsigned mask = modulo - 1; | |
324 | /* any zero bits */ | |
325 | while (mask >= sizeof (unsigned64)) /* minimum modulo */ | |
326 | { | |
327 | if ((mask & 1) == 0) | |
328 | mask = 0; | |
329 | else | |
330 | mask >>= 1; | |
331 | } | |
332 | if (mask != sizeof (unsigned64) - 1) | |
333 | { | |
334 | #if (WITH_DEVICES) | |
335 | device_error (client, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo); | |
336 | #endif | |
337 | #if (WITH_HW) | |
338 | sim_hw_abort (sd, client, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo); | |
339 | #endif | |
340 | sim_io_error (sd, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo); | |
341 | } | |
342 | } | |
343 | ||
344 | /* verify consistency between device and buffer */ | |
345 | if (client != NULL && optional_buffer != NULL) | |
346 | { | |
347 | #if (WITH_DEVICES) | |
348 | device_error (client, "sim_core_attach - internal error - conflicting buffer and attach arguments"); | |
349 | #endif | |
350 | #if (WITH_HW) | |
351 | sim_hw_abort (sd, client, "sim_core_attach - internal error - conflicting buffer and attach arguments"); | |
352 | #endif | |
353 | sim_io_error (sd, "sim_core_attach - internal error - conflicting buffer and attach arguments"); | |
354 | } | |
355 | if (client == NULL) | |
356 | { | |
357 | if (optional_buffer == NULL) | |
358 | { | |
359 | int padding = (addr % sizeof (unsigned64)); | |
360 | unsigned long bytes = (modulo == 0 ? nr_bytes : modulo) + padding; | |
361 | free_buffer = zalloc (bytes); | |
362 | buffer = (char*) free_buffer + padding; | |
363 | } | |
364 | else | |
365 | { | |
366 | buffer = optional_buffer; | |
367 | free_buffer = NULL; | |
368 | } | |
369 | } | |
370 | else | |
371 | { | |
372 | /* a device */ | |
373 | buffer = NULL; | |
374 | free_buffer = NULL; | |
375 | } | |
376 | ||
377 | /* attach the region to all applicable access maps */ | |
378 | for (map = 0; | |
379 | map < nr_maps; | |
380 | map++) | |
381 | { | |
382 | if (mapmask & (1 << map)) | |
383 | { | |
384 | sim_core_map_attach (sd, &memory->common.map[map], | |
385 | level, space, addr, nr_bytes, modulo, | |
386 | client, buffer, free_buffer); | |
387 | free_buffer = NULL; | |
388 | } | |
389 | } | |
390 | ||
391 | /* Just copy this map to each of the processor specific data structures. | |
392 | FIXME - later this will be replaced by true processor specific | |
393 | maps. */ | |
394 | { | |
395 | int i; | |
396 | for (i = 0; i < MAX_NR_PROCESSORS; i++) | |
397 | { | |
398 | CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common; | |
399 | } | |
400 | } | |
401 | } | |
402 | #endif | |
403 | ||
404 | ||
405 | /* Remove any memory reference related to this address */ | |
406 | #if EXTERN_SIM_CORE_P | |
407 | static void | |
408 | sim_core_map_detach (SIM_DESC sd, | |
409 | sim_core_map *access_map, | |
410 | int level, | |
411 | int space, | |
412 | address_word addr) | |
413 | { | |
414 | sim_core_mapping **entry; | |
415 | for (entry = &access_map->first; | |
416 | (*entry) != NULL; | |
417 | entry = &(*entry)->next) | |
418 | { | |
419 | if ((*entry)->base == addr | |
420 | && (*entry)->level == level | |
421 | && (*entry)->space == space) | |
422 | { | |
423 | sim_core_mapping *dead = (*entry); | |
424 | (*entry) = dead->next; | |
425 | if (dead->free_buffer != NULL) | |
426 | zfree (dead->free_buffer); | |
427 | zfree (dead); | |
428 | return; | |
429 | } | |
430 | } | |
431 | } | |
432 | #endif | |
433 | ||
434 | #if EXTERN_SIM_CORE_P | |
435 | void | |
436 | sim_core_detach (SIM_DESC sd, | |
437 | sim_cpu *cpu, | |
438 | int level, | |
439 | int address_space, | |
440 | address_word addr) | |
441 | { | |
442 | sim_core *memory = STATE_CORE (sd); | |
443 | unsigned map; | |
444 | for (map = 0; map < nr_maps; map++) | |
445 | { | |
446 | sim_core_map_detach (sd, &memory->common.map[map], | |
447 | level, address_space, addr); | |
448 | } | |
449 | /* Just copy this update to each of the processor specific data | |
450 | structures. FIXME - later this will be replaced by true | |
451 | processor specific maps. */ | |
452 | { | |
453 | int i; | |
454 | for (i = 0; i < MAX_NR_PROCESSORS; i++) | |
455 | { | |
456 | CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common; | |
457 | } | |
458 | } | |
459 | } | |
460 | #endif | |
461 | ||
462 | ||
463 | STATIC_INLINE_SIM_CORE\ | |
464 | (sim_core_mapping *) | |
465 | sim_core_find_mapping(sim_core_common *core, | |
466 | unsigned map, | |
467 | address_word addr, | |
468 | unsigned nr_bytes, | |
469 | transfer_type transfer, | |
470 | int abort, /*either 0 or 1 - hint to inline/-O */ | |
471 | sim_cpu *cpu, /* abort => cpu != NULL */ | |
472 | sim_cia cia) | |
473 | { | |
474 | sim_core_mapping *mapping = core->map[map].first; | |
475 | ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */ | |
476 | ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */ | |
477 | ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */ | |
478 | while (mapping != NULL) | |
479 | { | |
480 | if (addr >= mapping->base | |
481 | && (addr + (nr_bytes - 1)) <= mapping->bound) | |
482 | return mapping; | |
483 | mapping = mapping->next; | |
484 | } | |
485 | if (abort) | |
486 | { | |
487 | SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, nr_bytes, addr, transfer, | |
488 | sim_core_unmapped_signal); | |
489 | } | |
490 | return NULL; | |
491 | } | |
492 | ||
493 | ||
494 | STATIC_INLINE_SIM_CORE\ | |
495 | (void *) | |
496 | sim_core_translate (sim_core_mapping *mapping, | |
497 | address_word addr) | |
498 | { | |
499 | if (WITH_MODULO_MEMORY) | |
500 | return (void *)((unsigned8 *) mapping->buffer | |
501 | + ((addr - mapping->base) & mapping->mask)); | |
502 | else | |
503 | return (void *)((unsigned8 *) mapping->buffer | |
504 | + addr - mapping->base); | |
505 | } | |
506 | ||
507 | ||
508 | #if EXTERN_SIM_CORE_P | |
509 | unsigned | |
510 | sim_core_read_buffer (SIM_DESC sd, | |
511 | sim_cpu *cpu, | |
512 | unsigned map, | |
513 | void *buffer, | |
514 | address_word addr, | |
515 | unsigned len) | |
516 | { | |
517 | sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common); | |
518 | unsigned count = 0; | |
519 | while (count < len) | |
520 | { | |
521 | unsigned_word raddr = addr + count; | |
522 | sim_core_mapping *mapping = | |
523 | sim_core_find_mapping (core, map, | |
524 | raddr, /*nr-bytes*/1, | |
525 | read_transfer, | |
526 | 0 /*dont-abort*/, NULL, NULL_CIA); | |
527 | if (mapping == NULL) | |
528 | break; | |
529 | #if (WITH_DEVICES) | |
530 | if (mapping->device != NULL) | |
531 | { | |
532 | int nr_bytes = len - count; | |
7a292a7a | 533 | sim_cia cia = cpu ? CIA_GET (cpu) : NULL_CIA; |
c906108c SS |
534 | if (raddr + nr_bytes - 1> mapping->bound) |
535 | nr_bytes = mapping->bound - raddr + 1; | |
536 | if (device_io_read_buffer (mapping->device, | |
537 | (unsigned_1*)buffer + count, | |
538 | mapping->space, | |
539 | raddr, | |
540 | nr_bytes, | |
7a292a7a | 541 | sd, |
c906108c | 542 | cpu, |
7a292a7a | 543 | cia) != nr_bytes) |
c906108c SS |
544 | break; |
545 | count += nr_bytes; | |
546 | continue; | |
547 | } | |
548 | #endif | |
549 | #if (WITH_HW) | |
550 | if (mapping->device != NULL) | |
551 | { | |
552 | int nr_bytes = len - count; | |
553 | if (raddr + nr_bytes - 1> mapping->bound) | |
554 | nr_bytes = mapping->bound - raddr + 1; | |
555 | if (sim_hw_io_read_buffer (sd, mapping->device, | |
556 | (unsigned_1*)buffer + count, | |
557 | mapping->space, | |
558 | raddr, | |
559 | nr_bytes) != nr_bytes) | |
560 | break; | |
561 | count += nr_bytes; | |
562 | continue; | |
563 | } | |
564 | #endif | |
565 | ((unsigned_1*)buffer)[count] = | |
566 | *(unsigned_1*)sim_core_translate(mapping, raddr); | |
567 | count += 1; | |
568 | } | |
569 | return count; | |
570 | } | |
571 | #endif | |
572 | ||
573 | ||
574 | #if EXTERN_SIM_CORE_P | |
575 | unsigned | |
576 | sim_core_write_buffer (SIM_DESC sd, | |
577 | sim_cpu *cpu, | |
578 | unsigned map, | |
579 | const void *buffer, | |
580 | address_word addr, | |
581 | unsigned len) | |
582 | { | |
583 | sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common); | |
584 | unsigned count = 0; | |
585 | while (count < len) | |
586 | { | |
587 | unsigned_word raddr = addr + count; | |
588 | sim_core_mapping *mapping = | |
589 | sim_core_find_mapping (core, map, | |
590 | raddr, /*nr-bytes*/1, | |
591 | write_transfer, | |
592 | 0 /*dont-abort*/, NULL, NULL_CIA); | |
593 | if (mapping == NULL) | |
594 | break; | |
595 | #if (WITH_DEVICES) | |
596 | if (WITH_CALLBACK_MEMORY | |
597 | && mapping->device != NULL) | |
598 | { | |
599 | int nr_bytes = len - count; | |
7a292a7a | 600 | sim_cia cia = cpu ? CIA_GET (cpu) : NULL_CIA; |
c906108c SS |
601 | if (raddr + nr_bytes - 1 > mapping->bound) |
602 | nr_bytes = mapping->bound - raddr + 1; | |
603 | if (device_io_write_buffer (mapping->device, | |
604 | (unsigned_1*)buffer + count, | |
605 | mapping->space, | |
606 | raddr, | |
607 | nr_bytes, | |
7a292a7a | 608 | sd, |
c906108c | 609 | cpu, |
7a292a7a | 610 | cia) != nr_bytes) |
c906108c SS |
611 | break; |
612 | count += nr_bytes; | |
613 | continue; | |
614 | } | |
615 | #endif | |
616 | #if (WITH_HW) | |
617 | if (WITH_CALLBACK_MEMORY | |
618 | && mapping->device != NULL) | |
619 | { | |
620 | int nr_bytes = len - count; | |
621 | if (raddr + nr_bytes - 1 > mapping->bound) | |
622 | nr_bytes = mapping->bound - raddr + 1; | |
623 | if (sim_hw_io_write_buffer (sd, mapping->device, | |
624 | (unsigned_1*)buffer + count, | |
625 | mapping->space, | |
626 | raddr, | |
627 | nr_bytes) != nr_bytes) | |
628 | break; | |
629 | count += nr_bytes; | |
630 | continue; | |
631 | } | |
632 | #endif | |
633 | *(unsigned_1*)sim_core_translate(mapping, raddr) = | |
634 | ((unsigned_1*)buffer)[count]; | |
635 | count += 1; | |
636 | } | |
637 | return count; | |
638 | } | |
639 | #endif | |
640 | ||
641 | ||
642 | #if EXTERN_SIM_CORE_P | |
643 | void | |
644 | sim_core_set_xor (SIM_DESC sd, | |
645 | sim_cpu *cpu, | |
646 | int is_xor) | |
647 | { | |
648 | /* set up the XOR map if required. */ | |
649 | if (WITH_XOR_ENDIAN) { | |
650 | { | |
651 | sim_core *core = STATE_CORE (sd); | |
652 | sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL); | |
653 | if (cpu_core != NULL) | |
654 | { | |
655 | int i = 1; | |
656 | unsigned mask; | |
657 | if (is_xor) | |
658 | mask = WITH_XOR_ENDIAN - 1; | |
659 | else | |
660 | mask = 0; | |
661 | while (i - 1 < WITH_XOR_ENDIAN) | |
662 | { | |
663 | cpu_core->xor[i-1] = mask; | |
664 | mask = (mask << 1) & (WITH_XOR_ENDIAN - 1); | |
665 | i = (i << 1); | |
666 | } | |
667 | } | |
668 | else | |
669 | { | |
670 | if (is_xor) | |
671 | core->byte_xor = WITH_XOR_ENDIAN - 1; | |
672 | else | |
673 | core->byte_xor = 0; | |
674 | } | |
675 | } | |
676 | } | |
677 | else { | |
678 | if (is_xor) | |
679 | sim_engine_abort (sd, NULL, NULL_CIA, | |
680 | "Attempted to enable xor-endian mode when permenantly disabled."); | |
681 | } | |
682 | } | |
683 | #endif | |
684 | ||
685 | ||
686 | #if EXTERN_SIM_CORE_P | |
687 | static void | |
688 | reverse_n (unsigned_1 *dest, | |
689 | const unsigned_1 *src, | |
690 | int nr_bytes) | |
691 | { | |
692 | int i; | |
693 | for (i = 0; i < nr_bytes; i++) | |
694 | { | |
695 | dest [nr_bytes - i - 1] = src [i]; | |
696 | } | |
697 | } | |
698 | #endif | |
699 | ||
700 | ||
701 | #if EXTERN_SIM_CORE_P | |
702 | unsigned | |
703 | sim_core_xor_read_buffer (SIM_DESC sd, | |
704 | sim_cpu *cpu, | |
705 | unsigned map, | |
706 | void *buffer, | |
707 | address_word addr, | |
708 | unsigned nr_bytes) | |
709 | { | |
710 | address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]); | |
711 | if (!WITH_XOR_ENDIAN || !byte_xor) | |
712 | return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes); | |
713 | else | |
714 | /* only break up transfers when xor-endian is both selected and enabled */ | |
715 | { | |
716 | unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */ | |
717 | unsigned nr_transfered = 0; | |
718 | address_word start = addr; | |
719 | unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1))); | |
720 | address_word stop; | |
721 | /* initial and intermediate transfers are broken when they cross | |
722 | an XOR endian boundary */ | |
723 | while (nr_transfered + nr_this_transfer < nr_bytes) | |
724 | /* initial/intermediate transfers */ | |
725 | { | |
726 | /* since xor-endian is enabled stop^xor defines the start | |
727 | address of the transfer */ | |
728 | stop = start + nr_this_transfer - 1; | |
729 | SIM_ASSERT (start <= stop); | |
730 | SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor)); | |
731 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
732 | != nr_this_transfer) | |
733 | return nr_transfered; | |
734 | reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer); | |
735 | nr_transfered += nr_this_transfer; | |
736 | nr_this_transfer = WITH_XOR_ENDIAN; | |
737 | start = stop + 1; | |
738 | } | |
739 | /* final transfer */ | |
740 | nr_this_transfer = nr_bytes - nr_transfered; | |
741 | stop = start + nr_this_transfer - 1; | |
742 | SIM_ASSERT (stop == (addr + nr_bytes - 1)); | |
743 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
744 | != nr_this_transfer) | |
745 | return nr_transfered; | |
746 | reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer); | |
747 | return nr_bytes; | |
748 | } | |
749 | } | |
750 | #endif | |
751 | ||
752 | ||
753 | #if EXTERN_SIM_CORE_P | |
754 | unsigned | |
755 | sim_core_xor_write_buffer (SIM_DESC sd, | |
756 | sim_cpu *cpu, | |
757 | unsigned map, | |
758 | const void *buffer, | |
759 | address_word addr, | |
760 | unsigned nr_bytes) | |
761 | { | |
762 | address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]); | |
763 | if (!WITH_XOR_ENDIAN || !byte_xor) | |
764 | return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes); | |
765 | else | |
766 | /* only break up transfers when xor-endian is both selected and enabled */ | |
767 | { | |
768 | unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero sized array */ | |
769 | unsigned nr_transfered = 0; | |
770 | address_word start = addr; | |
771 | unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1))); | |
772 | address_word stop; | |
773 | /* initial and intermediate transfers are broken when they cross | |
774 | an XOR endian boundary */ | |
775 | while (nr_transfered + nr_this_transfer < nr_bytes) | |
776 | /* initial/intermediate transfers */ | |
777 | { | |
778 | /* since xor-endian is enabled stop^xor defines the start | |
779 | address of the transfer */ | |
780 | stop = start + nr_this_transfer - 1; | |
781 | SIM_ASSERT (start <= stop); | |
782 | SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor)); | |
783 | reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer); | |
784 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
785 | != nr_this_transfer) | |
786 | return nr_transfered; | |
787 | nr_transfered += nr_this_transfer; | |
788 | nr_this_transfer = WITH_XOR_ENDIAN; | |
789 | start = stop + 1; | |
790 | } | |
791 | /* final transfer */ | |
792 | nr_this_transfer = nr_bytes - nr_transfered; | |
793 | stop = start + nr_this_transfer - 1; | |
794 | SIM_ASSERT (stop == (addr + nr_bytes - 1)); | |
795 | reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer); | |
796 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
797 | != nr_this_transfer) | |
798 | return nr_transfered; | |
799 | return nr_bytes; | |
800 | } | |
801 | } | |
802 | #endif | |
803 | ||
6edf0760 NC |
804 | #if EXTERN_SIM_CORE_P |
805 | void * | |
806 | sim_core_trans_addr (SIM_DESC sd, | |
807 | sim_cpu *cpu, | |
808 | unsigned map, | |
809 | address_word addr) | |
810 | { | |
811 | sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common); | |
812 | sim_core_mapping *mapping = | |
813 | sim_core_find_mapping (core, map, | |
814 | addr, /*nr-bytes*/1, | |
815 | write_transfer, | |
816 | 0 /*dont-abort*/, NULL, NULL_CIA); | |
817 | if (mapping == NULL) | |
818 | return NULL; | |
819 | return sim_core_translate(mapping, addr); | |
820 | } | |
821 | #endif | |
822 | ||
c906108c SS |
823 | |
824 | ||
825 | /* define the read/write 1/2/4/8/16/word functions */ | |
826 | ||
827 | #define N 16 | |
828 | #include "sim-n-core.h" | |
829 | ||
830 | #define N 8 | |
831 | #include "sim-n-core.h" | |
832 | ||
833 | #define N 7 | |
834 | #define M 8 | |
835 | #include "sim-n-core.h" | |
836 | ||
837 | #define N 6 | |
838 | #define M 8 | |
839 | #include "sim-n-core.h" | |
840 | ||
841 | #define N 5 | |
842 | #define M 8 | |
843 | #include "sim-n-core.h" | |
844 | ||
845 | #define N 4 | |
846 | #include "sim-n-core.h" | |
847 | ||
848 | #define N 3 | |
849 | #define M 4 | |
850 | #include "sim-n-core.h" | |
851 | ||
852 | #define N 2 | |
853 | #include "sim-n-core.h" | |
854 | ||
855 | #define N 1 | |
856 | #include "sim-n-core.h" | |
857 | ||
858 | #endif |