Commit | Line | Data |
---|---|---|
f2de7dfd AC |
1 | /* This file is part of the program psim. |
2 | ||
3 | Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
17 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | ||
19 | */ | |
20 | ||
21 | ||
22 | #ifndef _SIM_CORE_C_ | |
23 | #define _SIM_CORE_C_ | |
24 | ||
c967f187 DE |
25 | #include "sim-main.h" |
26 | #include "sim-assert.h" | |
f2de7dfd | 27 | |
fd89abc2 AC |
28 | #include <signal.h> |
29 | ||
30 | /* for Windows builds. signal numbers used by MSVC are mostly | |
31 | the same as non-linux unixen. */ | |
32 | #ifndef SIGBUS | |
33 | # define SIGBUS 10 | |
34 | #endif | |
35 | ||
f2de7dfd | 36 | |
c967f187 | 37 | /* "core" module install handler. |
cd0d873d | 38 | |
c967f187 DE |
39 | This is called via sim_module_install to install the "core" subsystem |
40 | into the simulator. */ | |
41 | ||
cd0d873d AC |
42 | static MODULE_INIT_FN sim_core_init; |
43 | static MODULE_UNINSTALL_FN sim_core_uninstall; | |
44 | ||
c967f187 DE |
45 | EXTERN_SIM_CORE\ |
46 | (SIM_RC) | |
47 | sim_core_install (SIM_DESC sd) | |
48 | { | |
50a2a691 | 49 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); |
a34abff8 AC |
50 | |
51 | /* establish the other handlers */ | |
c967f187 DE |
52 | sim_module_add_uninstall_fn (sd, sim_core_uninstall); |
53 | sim_module_add_init_fn (sd, sim_core_init); | |
a34abff8 AC |
54 | |
55 | /* establish any initial data structures - none */ | |
c967f187 DE |
56 | return SIM_RC_OK; |
57 | } | |
58 | ||
59 | ||
60 | /* Uninstall the "core" subsystem from the simulator. */ | |
61 | ||
cd0d873d | 62 | STATIC_SIM_CORE\ |
f2de7dfd | 63 | (void) |
c967f187 | 64 | sim_core_uninstall (SIM_DESC sd) |
f2de7dfd | 65 | { |
f90b720b | 66 | sim_core *core = STATE_CORE(sd); |
c967f187 | 67 | sim_core_maps map; |
a34abff8 | 68 | /* blow away any mappings */ |
f90b720b | 69 | for (map = 0; map < nr_sim_core_maps; map++) { |
f90b720b | 70 | sim_core_mapping *curr = core->common.map[map].first; |
f2de7dfd | 71 | while (curr != NULL) { |
c967f187 | 72 | sim_core_mapping *tbd = curr; |
f2de7dfd | 73 | curr = curr->next; |
fd89abc2 | 74 | if (tbd->free_buffer != NULL) { |
c967f187 | 75 | SIM_ASSERT(tbd->buffer != NULL); |
fd89abc2 | 76 | zfree(tbd->free_buffer); |
f2de7dfd AC |
77 | } |
78 | zfree(tbd); | |
79 | } | |
f90b720b AC |
80 | core->common.map[map].first = NULL; |
81 | } | |
a34abff8 AC |
82 | } |
83 | ||
84 | ||
85 | STATIC_SIM_CORE\ | |
86 | (SIM_RC) | |
87 | sim_core_init (SIM_DESC sd) | |
88 | { | |
89 | /* Nothing to do */ | |
c967f187 | 90 | return SIM_RC_OK; |
f2de7dfd AC |
91 | } |
92 | ||
93 | ||
94 | ||
50a2a691 AC |
95 | #ifndef SIM_CORE_SIGNAL |
96 | #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ | |
97 | sim_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR)) | |
98 | ||
cd0d873d AC |
99 | STATIC_SIM_CORE\ |
100 | (void) | |
50a2a691 AC |
101 | sim_core_signal (SIM_DESC sd, |
102 | sim_cpu *cpu, | |
103 | sim_cia cia, | |
104 | sim_core_maps map, | |
105 | int nr_bytes, | |
106 | address_word addr, | |
107 | transfer_type transfer, | |
108 | sim_core_signals sig) | |
109 | { | |
110 | const char *copy = (transfer == read_transfer ? "read" : "write"); | |
111 | switch (sig) | |
112 | { | |
113 | case sim_core_unmapped_signal: | |
fd89abc2 AC |
114 | sim_io_eprintf (sd, "core: %d byte %s to unmaped address 0x%lx\n", |
115 | nr_bytes, copy, (unsigned long) addr); | |
116 | sim_engine_halt (sd, cpu, NULL, cia, sim_signalled, SIGSEGV); | |
50a2a691 AC |
117 | break; |
118 | case sim_core_unaligned_signal: | |
fd89abc2 AC |
119 | sim_io_eprintf (sd, "core: %d byte misaligned %s to address 0x%lx", |
120 | nr_bytes, copy, (unsigned long) addr); | |
121 | sim_engine_halt (sd, cpu, NULL, cia, sim_signalled, SIGBUS); | |
50a2a691 AC |
122 | break; |
123 | default: | |
fd89abc2 AC |
124 | sim_engine_abort (sd, cpu, cia, |
125 | "sim_core_signal - internal error - bad switch"); | |
50a2a691 AC |
126 | } |
127 | } | |
50a2a691 AC |
128 | #endif |
129 | ||
cd0d873d | 130 | |
1fe05280 AC |
131 | STATIC_INLINE_SIM_CORE\ |
132 | (const char *) | |
133 | sim_core_map_to_str (sim_core_maps map) | |
134 | { | |
135 | switch (map) | |
136 | { | |
137 | case sim_core_read_map: return "read"; | |
138 | case sim_core_write_map: return "write"; | |
139 | case sim_core_execute_map: return "exec"; | |
140 | default: return "(invalid-map)"; | |
141 | } | |
142 | } | |
143 | ||
144 | ||
cd0d873d | 145 | STATIC_SIM_CORE\ |
c967f187 | 146 | (sim_core_mapping *) |
a34abff8 | 147 | new_sim_core_mapping (SIM_DESC sd, |
fcc86d82 | 148 | int level, |
a34abff8 AC |
149 | int space, |
150 | address_word addr, | |
151 | address_word nr_bytes, | |
152 | unsigned modulo, | |
153 | device *device, | |
154 | void *buffer, | |
fd89abc2 | 155 | void *free_buffer) |
f2de7dfd | 156 | { |
c967f187 | 157 | sim_core_mapping *new_mapping = ZALLOC(sim_core_mapping); |
f2de7dfd | 158 | /* common */ |
fcc86d82 | 159 | new_mapping->level = level; |
f2de7dfd AC |
160 | new_mapping->space = space; |
161 | new_mapping->base = addr; | |
162 | new_mapping->nr_bytes = nr_bytes; | |
163 | new_mapping->bound = addr + (nr_bytes - 1); | |
a34abff8 AC |
164 | if (modulo == 0) |
165 | new_mapping->mask = (unsigned) 0 - 1; | |
166 | else | |
167 | new_mapping->mask = modulo - 1; | |
fcc86d82 AC |
168 | new_mapping->buffer = buffer; |
169 | new_mapping->free_buffer = free_buffer; | |
170 | new_mapping->device = device; | |
f2de7dfd AC |
171 | return new_mapping; |
172 | } | |
173 | ||
174 | ||
cd0d873d | 175 | STATIC_SIM_CORE\ |
f2de7dfd | 176 | (void) |
a34abff8 AC |
177 | sim_core_map_attach (SIM_DESC sd, |
178 | sim_core_map *access_map, | |
fcc86d82 | 179 | int level, |
a34abff8 AC |
180 | int space, |
181 | address_word addr, | |
182 | address_word nr_bytes, | |
183 | unsigned modulo, | |
184 | device *client, /*callback/default*/ | |
185 | void *buffer, /*raw_memory*/ | |
fd89abc2 | 186 | void *free_buffer) /*raw_memory*/ |
f2de7dfd AC |
187 | { |
188 | /* find the insertion point for this additional mapping and then | |
189 | insert */ | |
c967f187 DE |
190 | sim_core_mapping *next_mapping; |
191 | sim_core_mapping **last_mapping; | |
f2de7dfd | 192 | |
fcc86d82 AC |
193 | SIM_ASSERT ((client == NULL) != (buffer == NULL)); |
194 | SIM_ASSERT ((client == NULL) >= (free_buffer != NULL)); | |
f2de7dfd AC |
195 | |
196 | /* actually do occasionally get a zero size map */ | |
a34abff8 AC |
197 | if (nr_bytes == 0) |
198 | { | |
f2de7dfd | 199 | #if (WITH_DEVICES) |
a34abff8 | 200 | device_error(client, "called on sim_core_map_attach with size zero"); |
f2de7dfd | 201 | #else |
a34abff8 | 202 | sim_io_error (sd, "called on sim_core_map_attach with size zero"); |
f2de7dfd | 203 | #endif |
a34abff8 | 204 | } |
f2de7dfd AC |
205 | |
206 | /* find the insertion point (between last/next) */ | |
207 | next_mapping = access_map->first; | |
208 | last_mapping = &access_map->first; | |
209 | while(next_mapping != NULL | |
fcc86d82 AC |
210 | && (next_mapping->level < level |
211 | || (next_mapping->level == level | |
a34abff8 AC |
212 | && next_mapping->bound < addr))) |
213 | { | |
214 | /* provided levels are the same */ | |
215 | /* assert: next_mapping->base > all bases before next_mapping */ | |
216 | /* assert: next_mapping->bound >= all bounds before next_mapping */ | |
217 | last_mapping = &next_mapping->next; | |
218 | next_mapping = next_mapping->next; | |
219 | } | |
220 | ||
f2de7dfd | 221 | /* check insertion point correct */ |
fcc86d82 AC |
222 | SIM_ASSERT (next_mapping == NULL || next_mapping->level >= level); |
223 | if (next_mapping != NULL && next_mapping->level == level | |
80c651f0 AC |
224 | && next_mapping->base < (addr + (nr_bytes - 1))) |
225 | { | |
f2de7dfd | 226 | #if (WITH_DEVICES) |
80c651f0 AC |
227 | device_error (client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)", |
228 | space, | |
229 | (long) addr, | |
230 | (long) nr_bytes, | |
231 | (long) (addr + (nr_bytes - 1)), | |
232 | next_mapping->space, | |
233 | (long) next_mapping->base, | |
234 | (long) next_mapping->bound, | |
235 | (long) next_mapping->nr_bytes); | |
f2de7dfd | 236 | #else |
80c651f0 AC |
237 | sim_io_error (sd, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)", |
238 | space, | |
239 | (long) addr, | |
240 | (long) nr_bytes, | |
241 | (long) (addr + (nr_bytes - 1)), | |
242 | next_mapping->space, | |
243 | (long) next_mapping->base, | |
244 | (long) next_mapping->bound, | |
245 | (long) next_mapping->nr_bytes); | |
f2de7dfd AC |
246 | #endif |
247 | } | |
248 | ||
249 | /* create/insert the new mapping */ | |
c967f187 | 250 | *last_mapping = new_sim_core_mapping(sd, |
fcc86d82 | 251 | level, |
a34abff8 | 252 | space, addr, nr_bytes, modulo, |
80c651f0 | 253 | client, buffer, free_buffer); |
f2de7dfd AC |
254 | (*last_mapping)->next = next_mapping; |
255 | } | |
256 | ||
257 | ||
cd0d873d | 258 | EXTERN_SIM_CORE\ |
f2de7dfd | 259 | (void) |
a34abff8 AC |
260 | sim_core_attach (SIM_DESC sd, |
261 | sim_cpu *cpu, | |
fcc86d82 | 262 | int level, |
a34abff8 AC |
263 | access_type access, |
264 | int space, | |
265 | address_word addr, | |
266 | address_word nr_bytes, | |
267 | unsigned modulo, | |
268 | device *client, | |
269 | void *optional_buffer) | |
f2de7dfd | 270 | { |
1fe05280 | 271 | sim_core *memory = STATE_CORE(sd); |
c967f187 | 272 | sim_core_maps map; |
f2de7dfd | 273 | void *buffer; |
fd89abc2 | 274 | void *free_buffer; |
7a418800 AC |
275 | |
276 | /* check for for attempt to use unimplemented per-processor core map */ | |
277 | if (cpu != NULL) | |
278 | sim_io_error (sd, "sim_core_map_attach - processor specific memory map not yet supported"); | |
279 | ||
f2de7dfd | 280 | if ((access & access_read_write_exec) == 0 |
a34abff8 AC |
281 | || (access & ~access_read_write_exec) != 0) |
282 | { | |
f2de7dfd | 283 | #if (WITH_DEVICES) |
a34abff8 | 284 | device_error(client, "invalid access for core attach"); |
f2de7dfd | 285 | #else |
a34abff8 | 286 | sim_io_error (sd, "invalid access for core attach"); |
f2de7dfd | 287 | #endif |
a34abff8 AC |
288 | } |
289 | ||
fcc86d82 AC |
290 | /* verify modulo memory */ |
291 | if (!WITH_MODULO_MEMORY && modulo != 0) | |
292 | { | |
293 | #if (WITH_DEVICES) | |
294 | device_error (client, "sim_core_attach - internal error - modulo memory disabled"); | |
295 | #else | |
296 | sim_io_error (sd, "sim_core_attach - internal error - modulo memory disabled"); | |
297 | #endif | |
298 | } | |
299 | if (client != NULL && modulo != 0) | |
a34abff8 | 300 | { |
a34abff8 | 301 | #if (WITH_DEVICES) |
fcc86d82 | 302 | device_error (client, "sim_core_attach - internal error - modulo and callback memory conflict"); |
a34abff8 | 303 | #else |
fcc86d82 | 304 | sim_io_error (sd, "sim_core_attach - internal error - modulo and callback memory conflict"); |
a34abff8 | 305 | #endif |
fcc86d82 AC |
306 | } |
307 | if (modulo != 0) | |
308 | { | |
309 | unsigned mask = modulo - 1; | |
310 | /* any zero bits */ | |
311 | while (mask >= sizeof (unsigned64)) /* minimum modulo */ | |
312 | { | |
313 | if ((mask & 1) == 0) | |
314 | mask = 0; | |
315 | else | |
316 | mask >>= 1; | |
a34abff8 | 317 | } |
fcc86d82 | 318 | if (mask != sizeof (unsigned64) - 1) |
a34abff8 AC |
319 | { |
320 | #if (WITH_DEVICES) | |
fcc86d82 | 321 | device_error (client, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo); |
a34abff8 | 322 | #else |
fcc86d82 | 323 | sim_io_error (sd, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo); |
a34abff8 AC |
324 | #endif |
325 | } | |
fcc86d82 AC |
326 | } |
327 | ||
328 | /* verify consistency between device and buffer */ | |
329 | if (client != NULL && optional_buffer != NULL) | |
330 | { | |
331 | #if (WITH_DEVICES) | |
332 | device_error (client, "sim_core_attach - internal error - conflicting buffer and attach arguments"); | |
333 | #else | |
334 | sim_io_error (sd, "sim_core_attach - internal error - conflicting buffer and attach arguments"); | |
335 | #endif | |
336 | } | |
337 | if (client == NULL) | |
338 | { | |
a34abff8 AC |
339 | if (optional_buffer == NULL) |
340 | { | |
fd89abc2 AC |
341 | int padding = (addr % sizeof (unsigned64)); |
342 | free_buffer = zalloc ((modulo == 0 ? nr_bytes : modulo) + padding); | |
343 | buffer = (char*) free_buffer + padding; | |
a34abff8 AC |
344 | } |
345 | else | |
346 | { | |
347 | buffer = optional_buffer; | |
fd89abc2 | 348 | free_buffer = NULL; |
a34abff8 | 349 | } |
f2de7dfd | 350 | } |
a34abff8 AC |
351 | else |
352 | { | |
fcc86d82 | 353 | /* a device */ |
a34abff8 | 354 | buffer = NULL; |
fd89abc2 | 355 | free_buffer = NULL; |
a34abff8 AC |
356 | } |
357 | ||
f2de7dfd AC |
358 | /* attach the region to all applicable access maps */ |
359 | for (map = 0; | |
c967f187 | 360 | map < nr_sim_core_maps; |
a34abff8 AC |
361 | map++) |
362 | { | |
363 | switch (map) | |
364 | { | |
365 | case sim_core_read_map: | |
366 | if (access & access_read) | |
367 | sim_core_map_attach (sd, &memory->common.map[map], | |
fcc86d82 | 368 | level, space, addr, nr_bytes, modulo, |
fd89abc2 AC |
369 | client, buffer, free_buffer); |
370 | free_buffer = NULL; | |
a34abff8 AC |
371 | break; |
372 | case sim_core_write_map: | |
373 | if (access & access_write) | |
374 | sim_core_map_attach (sd, &memory->common.map[map], | |
fcc86d82 | 375 | level, space, addr, nr_bytes, modulo, |
fd89abc2 AC |
376 | client, buffer, free_buffer); |
377 | free_buffer = NULL; | |
a34abff8 AC |
378 | break; |
379 | case sim_core_execute_map: | |
380 | if (access & access_exec) | |
381 | sim_core_map_attach (sd, &memory->common.map[map], | |
fcc86d82 | 382 | level, space, addr, nr_bytes, modulo, |
fd89abc2 AC |
383 | client, buffer, free_buffer); |
384 | free_buffer = NULL; | |
a34abff8 AC |
385 | break; |
386 | case nr_sim_core_maps: | |
387 | sim_io_error (sd, "sim_core_attach - internal error - bad switch"); | |
388 | break; | |
389 | } | |
f2de7dfd | 390 | } |
a34abff8 | 391 | |
7a418800 AC |
392 | /* Just copy this map to each of the processor specific data structures. |
393 | FIXME - later this will be replaced by true processor specific | |
394 | maps. */ | |
f90b720b AC |
395 | { |
396 | int i; | |
397 | for (i = 0; i < MAX_NR_PROCESSORS; i++) | |
398 | { | |
399 | CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common; | |
400 | } | |
401 | } | |
f2de7dfd AC |
402 | } |
403 | ||
404 | ||
a34abff8 AC |
405 | /* Remove any memory reference related to this address */ |
406 | STATIC_INLINE_SIM_CORE\ | |
407 | (void) | |
408 | sim_core_map_detach (SIM_DESC sd, | |
409 | sim_core_map *access_map, | |
fcc86d82 | 410 | int level, |
a34abff8 AC |
411 | int space, |
412 | address_word addr) | |
413 | { | |
414 | sim_core_mapping **entry; | |
415 | for (entry = &access_map->first; | |
416 | (*entry) != NULL; | |
417 | entry = &(*entry)->next) | |
418 | { | |
419 | if ((*entry)->base == addr | |
fcc86d82 | 420 | && (*entry)->level == level |
a34abff8 AC |
421 | && (*entry)->space == space) |
422 | { | |
423 | sim_core_mapping *dead = (*entry); | |
424 | (*entry) = dead->next; | |
fd89abc2 AC |
425 | if (dead->free_buffer != NULL) |
426 | zfree (dead->free_buffer); | |
a34abff8 AC |
427 | zfree (dead); |
428 | return; | |
429 | } | |
430 | } | |
431 | } | |
432 | ||
433 | EXTERN_SIM_CORE\ | |
434 | (void) | |
435 | sim_core_detach (SIM_DESC sd, | |
436 | sim_cpu *cpu, | |
fcc86d82 | 437 | int level, |
a34abff8 AC |
438 | int address_space, |
439 | address_word addr) | |
440 | { | |
441 | sim_core *memory = STATE_CORE (sd); | |
442 | sim_core_maps map; | |
443 | for (map = 0; map < nr_sim_core_maps; map++) | |
444 | { | |
445 | sim_core_map_detach (sd, &memory->common.map[map], | |
fcc86d82 | 446 | level, address_space, addr); |
a34abff8 AC |
447 | } |
448 | /* Just copy this update to each of the processor specific data | |
449 | structures. FIXME - later this will be replaced by true | |
450 | processor specific maps. */ | |
451 | { | |
452 | int i; | |
453 | for (i = 0; i < MAX_NR_PROCESSORS; i++) | |
454 | { | |
455 | CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common; | |
456 | } | |
457 | } | |
458 | } | |
459 | ||
460 | ||
f2de7dfd | 461 | STATIC_INLINE_SIM_CORE\ |
c967f187 | 462 | (sim_core_mapping *) |
f90b720b | 463 | sim_core_find_mapping(sim_core_common *core, |
c967f187 | 464 | sim_core_maps map, |
cd0d873d | 465 | address_word addr, |
f2de7dfd | 466 | unsigned nr_bytes, |
50a2a691 | 467 | transfer_type transfer, |
7a418800 AC |
468 | int abort, /*either 0 or 1 - hint to inline/-O */ |
469 | sim_cpu *cpu, /* abort => cpu != NULL */ | |
1fe05280 | 470 | sim_cia cia) |
f2de7dfd | 471 | { |
7a418800 AC |
472 | sim_core_mapping *mapping = core->map[map].first; |
473 | ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */ | |
474 | ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */ | |
475 | ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */ | |
476 | while (mapping != NULL) | |
477 | { | |
478 | if (addr >= mapping->base | |
479 | && (addr + (nr_bytes - 1)) <= mapping->bound) | |
480 | return mapping; | |
481 | mapping = mapping->next; | |
482 | } | |
f2de7dfd | 483 | if (abort) |
7a418800 | 484 | { |
50a2a691 AC |
485 | SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, nr_bytes, addr, transfer, |
486 | sim_core_unmapped_signal); | |
7a418800 | 487 | } |
f2de7dfd AC |
488 | return NULL; |
489 | } | |
490 | ||
491 | ||
492 | STATIC_INLINE_SIM_CORE\ | |
493 | (void *) | |
f90b720b AC |
494 | sim_core_translate (sim_core_mapping *mapping, |
495 | address_word addr) | |
f2de7dfd | 496 | { |
a34abff8 AC |
497 | if (WITH_MODULO_MEMORY) |
498 | return (void *)((unsigned8 *) mapping->buffer | |
499 | + ((addr - mapping->base) & mapping->mask)); | |
500 | else | |
501 | return (void *)((unsigned8 *) mapping->buffer | |
502 | + addr - mapping->base); | |
f2de7dfd AC |
503 | } |
504 | ||
505 | ||
cd0d873d | 506 | EXTERN_SIM_CORE\ |
f2de7dfd | 507 | (unsigned) |
f90b720b AC |
508 | sim_core_read_buffer (SIM_DESC sd, |
509 | sim_cpu *cpu, | |
510 | sim_core_maps map, | |
511 | void *buffer, | |
512 | address_word addr, | |
513 | unsigned len) | |
f2de7dfd | 514 | { |
f90b720b | 515 | sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common); |
f2de7dfd AC |
516 | unsigned count = 0; |
517 | while (count < len) { | |
518 | unsigned_word raddr = addr + count; | |
c967f187 | 519 | sim_core_mapping *mapping = |
f90b720b | 520 | sim_core_find_mapping(core, map, |
50a2a691 AC |
521 | raddr, /*nr-bytes*/1, |
522 | read_transfer, | |
f90b720b | 523 | 0 /*dont-abort*/, NULL, NULL_CIA); |
f2de7dfd AC |
524 | if (mapping == NULL) |
525 | break; | |
526 | #if (WITH_DEVICES) | |
527 | if (mapping->device != NULL) { | |
528 | int nr_bytes = len - count; | |
529 | if (raddr + nr_bytes - 1> mapping->bound) | |
530 | nr_bytes = mapping->bound - raddr + 1; | |
531 | if (device_io_read_buffer(mapping->device, | |
532 | (unsigned_1*)buffer + count, | |
533 | mapping->space, | |
534 | raddr, | |
535 | nr_bytes) != nr_bytes) | |
536 | break; | |
537 | count += nr_bytes; | |
538 | } | |
539 | else | |
540 | #endif | |
541 | { | |
542 | ((unsigned_1*)buffer)[count] = | |
c967f187 | 543 | *(unsigned_1*)sim_core_translate(mapping, raddr); |
f2de7dfd AC |
544 | count += 1; |
545 | } | |
546 | } | |
547 | return count; | |
548 | } | |
549 | ||
550 | ||
cd0d873d | 551 | EXTERN_SIM_CORE\ |
f2de7dfd | 552 | (unsigned) |
f90b720b AC |
553 | sim_core_write_buffer (SIM_DESC sd, |
554 | sim_cpu *cpu, | |
555 | sim_core_maps map, | |
556 | const void *buffer, | |
557 | address_word addr, | |
558 | unsigned len) | |
f2de7dfd | 559 | { |
f90b720b | 560 | sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common); |
f2de7dfd AC |
561 | unsigned count = 0; |
562 | while (count < len) { | |
563 | unsigned_word raddr = addr + count; | |
f90b720b AC |
564 | sim_core_mapping *mapping = |
565 | sim_core_find_mapping(core, map, | |
566 | raddr, /*nr-bytes*/1, | |
567 | write_transfer, | |
568 | 0 /*dont-abort*/, NULL, NULL_CIA); | |
f2de7dfd AC |
569 | if (mapping == NULL) |
570 | break; | |
571 | #if (WITH_DEVICES) | |
572 | if (WITH_CALLBACK_MEMORY | |
573 | && mapping->device != NULL) { | |
574 | int nr_bytes = len - count; | |
575 | if (raddr + nr_bytes - 1 > mapping->bound) | |
576 | nr_bytes = mapping->bound - raddr + 1; | |
577 | if (device_io_write_buffer(mapping->device, | |
578 | (unsigned_1*)buffer + count, | |
579 | mapping->space, | |
580 | raddr, | |
581 | nr_bytes) != nr_bytes) | |
582 | break; | |
583 | count += nr_bytes; | |
584 | } | |
585 | else | |
586 | #endif | |
587 | { | |
c967f187 | 588 | *(unsigned_1*)sim_core_translate(mapping, raddr) = |
f2de7dfd AC |
589 | ((unsigned_1*)buffer)[count]; |
590 | count += 1; | |
591 | } | |
592 | } | |
593 | return count; | |
594 | } | |
595 | ||
596 | ||
cd0d873d AC |
597 | EXTERN_SIM_CORE\ |
598 | (void) | |
f90b720b AC |
599 | sim_core_set_xor (SIM_DESC sd, |
600 | sim_cpu *cpu, | |
cd0d873d AC |
601 | int is_xor) |
602 | { | |
f90b720b | 603 | /* set up the XOR map if required. */ |
cd0d873d AC |
604 | if (WITH_XOR_ENDIAN) { |
605 | { | |
f90b720b AC |
606 | sim_core *core = STATE_CORE (sd); |
607 | sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL); | |
608 | if (cpu_core != NULL) | |
cd0d873d | 609 | { |
f90b720b AC |
610 | int i = 1; |
611 | unsigned mask; | |
612 | if (is_xor) | |
613 | mask = WITH_XOR_ENDIAN - 1; | |
614 | else | |
615 | mask = 0; | |
616 | while (i - 1 < WITH_XOR_ENDIAN) | |
617 | { | |
618 | cpu_core->xor[i-1] = mask; | |
619 | mask = (mask << 1) & (WITH_XOR_ENDIAN - 1); | |
620 | i = (i << 1); | |
621 | } | |
cd0d873d | 622 | } |
f90b720b AC |
623 | else |
624 | { | |
625 | if (is_xor) | |
626 | core->byte_xor = WITH_XOR_ENDIAN - 1; | |
627 | else | |
628 | core->byte_xor = 0; | |
629 | } | |
cd0d873d AC |
630 | } |
631 | } | |
632 | else { | |
633 | if (is_xor) | |
f90b720b | 634 | sim_engine_abort (sd, cpu, NULL_CIA, |
cd0d873d AC |
635 | "Attempted to enable xor-endian mode when permenantly disabled."); |
636 | } | |
637 | } | |
638 | ||
f90b720b AC |
639 | STATIC_INLINE_SIM_CORE\ |
640 | (void) | |
641 | reverse_n (unsigned_1 *dest, | |
642 | const unsigned_1 *src, | |
643 | int nr_bytes) | |
644 | { | |
645 | int i; | |
646 | for (i = 0; i < nr_bytes; i++) | |
647 | { | |
648 | dest [nr_bytes - i - 1] = src [i]; | |
649 | } | |
650 | } | |
651 | ||
652 | ||
653 | EXTERN_SIM_CORE\ | |
654 | (unsigned) | |
655 | sim_core_xor_read_buffer (SIM_DESC sd, | |
656 | sim_cpu *cpu, | |
657 | sim_core_maps map, | |
658 | void *buffer, | |
659 | address_word addr, | |
660 | unsigned nr_bytes) | |
661 | { | |
662 | address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]); | |
663 | if (!WITH_XOR_ENDIAN || !byte_xor) | |
664 | return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes); | |
665 | else | |
666 | /* only break up transfers when xor-endian is both selected and enabled */ | |
667 | { | |
31dda65a | 668 | unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */ |
f90b720b AC |
669 | unsigned nr_transfered = 0; |
670 | address_word start = addr; | |
671 | unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1))); | |
672 | address_word stop; | |
673 | /* initial and intermediate transfers are broken when they cross | |
674 | an XOR endian boundary */ | |
675 | while (nr_transfered + nr_this_transfer < nr_bytes) | |
676 | /* initial/intermediate transfers */ | |
677 | { | |
678 | /* since xor-endian is enabled stop^xor defines the start | |
679 | address of the transfer */ | |
680 | stop = start + nr_this_transfer - 1; | |
681 | SIM_ASSERT (start <= stop); | |
682 | SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor)); | |
683 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
684 | != nr_this_transfer) | |
685 | return nr_transfered; | |
686 | reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer); | |
687 | nr_transfered += nr_this_transfer; | |
688 | nr_this_transfer = WITH_XOR_ENDIAN; | |
689 | start = stop + 1; | |
690 | } | |
691 | /* final transfer */ | |
692 | nr_this_transfer = nr_bytes - nr_transfered; | |
693 | stop = start + nr_this_transfer - 1; | |
694 | SIM_ASSERT (stop == (addr + nr_bytes - 1)); | |
695 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
696 | != nr_this_transfer) | |
697 | return nr_transfered; | |
698 | reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer); | |
699 | return nr_bytes; | |
700 | } | |
701 | } | |
702 | ||
703 | ||
704 | EXTERN_SIM_CORE\ | |
705 | (unsigned) | |
706 | sim_core_xor_write_buffer (SIM_DESC sd, | |
707 | sim_cpu *cpu, | |
708 | sim_core_maps map, | |
709 | const void *buffer, | |
710 | address_word addr, | |
711 | unsigned nr_bytes) | |
712 | { | |
713 | address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]); | |
714 | if (!WITH_XOR_ENDIAN || !byte_xor) | |
715 | return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes); | |
716 | else | |
717 | /* only break up transfers when xor-endian is both selected and enabled */ | |
718 | { | |
fd89abc2 | 719 | unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero sized array */ |
f90b720b AC |
720 | unsigned nr_transfered = 0; |
721 | address_word start = addr; | |
722 | unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1))); | |
723 | address_word stop; | |
724 | /* initial and intermediate transfers are broken when they cross | |
725 | an XOR endian boundary */ | |
726 | while (nr_transfered + nr_this_transfer < nr_bytes) | |
727 | /* initial/intermediate transfers */ | |
728 | { | |
729 | /* since xor-endian is enabled stop^xor defines the start | |
730 | address of the transfer */ | |
731 | stop = start + nr_this_transfer - 1; | |
732 | SIM_ASSERT (start <= stop); | |
733 | SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor)); | |
734 | reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer); | |
735 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
736 | != nr_this_transfer) | |
737 | return nr_transfered; | |
738 | nr_transfered += nr_this_transfer; | |
739 | nr_this_transfer = WITH_XOR_ENDIAN; | |
740 | start = stop + 1; | |
741 | } | |
742 | /* final transfer */ | |
743 | nr_this_transfer = nr_bytes - nr_transfered; | |
744 | stop = start + nr_this_transfer - 1; | |
745 | SIM_ASSERT (stop == (addr + nr_bytes - 1)); | |
746 | reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer); | |
747 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
748 | != nr_this_transfer) | |
749 | return nr_transfered; | |
750 | return nr_bytes; | |
751 | } | |
752 | } | |
cd0d873d AC |
753 | |
754 | ||
755 | ||
f45dd42b | 756 | /* define the read/write 1/2/4/8/16/word functions */ |
f2de7dfd AC |
757 | |
758 | #define N 1 | |
759 | #include "sim-n-core.h" | |
760 | #undef N | |
761 | ||
762 | #define N 2 | |
763 | #include "sim-n-core.h" | |
764 | #undef N | |
765 | ||
766 | #define N 4 | |
767 | #include "sim-n-core.h" | |
768 | #undef N | |
769 | ||
770 | #define N 8 | |
771 | #include "sim-n-core.h" | |
772 | #undef N | |
773 | ||
f45dd42b AC |
774 | #define N 16 |
775 | #include "sim-n-core.h" | |
776 | #undef N | |
777 | ||
f2de7dfd | 778 | #endif |