Commit | Line | Data |
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f2de7dfd AC |
1 | /* This file is part of the program psim. |
2 | ||
3 | Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
17 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | ||
19 | */ | |
20 | ||
21 | ||
22 | #ifndef _SIM_CORE_C_ | |
23 | #define _SIM_CORE_C_ | |
24 | ||
c967f187 DE |
25 | #include "sim-main.h" |
26 | #include "sim-assert.h" | |
f2de7dfd AC |
27 | |
28 | ||
c967f187 | 29 | /* "core" module install handler. |
cd0d873d | 30 | |
c967f187 DE |
31 | This is called via sim_module_install to install the "core" subsystem |
32 | into the simulator. */ | |
33 | ||
cd0d873d AC |
34 | static MODULE_INIT_FN sim_core_init; |
35 | static MODULE_UNINSTALL_FN sim_core_uninstall; | |
36 | ||
c967f187 DE |
37 | EXTERN_SIM_CORE\ |
38 | (SIM_RC) | |
39 | sim_core_install (SIM_DESC sd) | |
40 | { | |
50a2a691 | 41 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); |
a34abff8 AC |
42 | |
43 | /* establish the other handlers */ | |
c967f187 DE |
44 | sim_module_add_uninstall_fn (sd, sim_core_uninstall); |
45 | sim_module_add_init_fn (sd, sim_core_init); | |
a34abff8 AC |
46 | |
47 | /* establish any initial data structures - none */ | |
c967f187 DE |
48 | return SIM_RC_OK; |
49 | } | |
50 | ||
51 | ||
52 | /* Uninstall the "core" subsystem from the simulator. */ | |
53 | ||
cd0d873d | 54 | STATIC_SIM_CORE\ |
f2de7dfd | 55 | (void) |
c967f187 | 56 | sim_core_uninstall (SIM_DESC sd) |
f2de7dfd | 57 | { |
f90b720b | 58 | sim_core *core = STATE_CORE(sd); |
c967f187 | 59 | sim_core_maps map; |
a34abff8 | 60 | /* blow away any mappings */ |
f90b720b | 61 | for (map = 0; map < nr_sim_core_maps; map++) { |
f90b720b | 62 | sim_core_mapping *curr = core->common.map[map].first; |
f2de7dfd | 63 | while (curr != NULL) { |
c967f187 | 64 | sim_core_mapping *tbd = curr; |
f2de7dfd AC |
65 | curr = curr->next; |
66 | if (tbd->free_buffer) { | |
c967f187 | 67 | SIM_ASSERT(tbd->buffer != NULL); |
f2de7dfd AC |
68 | zfree(tbd->buffer); |
69 | } | |
70 | zfree(tbd); | |
71 | } | |
f90b720b AC |
72 | core->common.map[map].first = NULL; |
73 | } | |
a34abff8 AC |
74 | } |
75 | ||
76 | ||
77 | STATIC_SIM_CORE\ | |
78 | (SIM_RC) | |
79 | sim_core_init (SIM_DESC sd) | |
80 | { | |
81 | /* Nothing to do */ | |
c967f187 | 82 | return SIM_RC_OK; |
f2de7dfd AC |
83 | } |
84 | ||
85 | ||
86 | ||
50a2a691 AC |
87 | #ifndef SIM_CORE_SIGNAL |
88 | #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ | |
89 | sim_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR)) | |
90 | ||
cd0d873d AC |
91 | STATIC_SIM_CORE\ |
92 | (void) | |
50a2a691 AC |
93 | sim_core_signal (SIM_DESC sd, |
94 | sim_cpu *cpu, | |
95 | sim_cia cia, | |
96 | sim_core_maps map, | |
97 | int nr_bytes, | |
98 | address_word addr, | |
99 | transfer_type transfer, | |
100 | sim_core_signals sig) | |
101 | { | |
102 | const char *copy = (transfer == read_transfer ? "read" : "write"); | |
103 | switch (sig) | |
104 | { | |
105 | case sim_core_unmapped_signal: | |
106 | sim_engine_abort (sd, cpu, cia, "sim-core: %d byte %s to unmaped address 0x%lx", | |
107 | nr_bytes, copy, (unsigned long) addr); | |
108 | break; | |
109 | case sim_core_unaligned_signal: | |
110 | sim_engine_abort (sd, cpu, cia, "sim-core: %d byte misaligned %s to address 0x%lx", | |
111 | nr_bytes, copy, (unsigned long) addr); | |
112 | break; | |
113 | default: | |
114 | sim_engine_abort (sd, cpu, cia, "sim_core_signal - internal error - bad switch"); | |
115 | } | |
116 | } | |
50a2a691 AC |
117 | #endif |
118 | ||
cd0d873d | 119 | |
1fe05280 AC |
120 | STATIC_INLINE_SIM_CORE\ |
121 | (const char *) | |
122 | sim_core_map_to_str (sim_core_maps map) | |
123 | { | |
124 | switch (map) | |
125 | { | |
126 | case sim_core_read_map: return "read"; | |
127 | case sim_core_write_map: return "write"; | |
128 | case sim_core_execute_map: return "exec"; | |
129 | default: return "(invalid-map)"; | |
130 | } | |
131 | } | |
132 | ||
133 | ||
cd0d873d | 134 | STATIC_SIM_CORE\ |
c967f187 | 135 | (sim_core_mapping *) |
a34abff8 AC |
136 | new_sim_core_mapping (SIM_DESC sd, |
137 | attach_type attach, | |
138 | int space, | |
139 | address_word addr, | |
140 | address_word nr_bytes, | |
141 | unsigned modulo, | |
142 | device *device, | |
143 | void *buffer, | |
144 | int free_buffer) | |
f2de7dfd | 145 | { |
c967f187 | 146 | sim_core_mapping *new_mapping = ZALLOC(sim_core_mapping); |
f2de7dfd AC |
147 | /* common */ |
148 | new_mapping->level = attach; | |
149 | new_mapping->space = space; | |
150 | new_mapping->base = addr; | |
151 | new_mapping->nr_bytes = nr_bytes; | |
152 | new_mapping->bound = addr + (nr_bytes - 1); | |
a34abff8 AC |
153 | if (modulo == 0) |
154 | new_mapping->mask = (unsigned) 0 - 1; | |
155 | else | |
156 | new_mapping->mask = modulo - 1; | |
157 | if (attach == attach_raw_memory) | |
158 | { | |
159 | new_mapping->buffer = buffer; | |
160 | new_mapping->free_buffer = free_buffer; | |
161 | } | |
162 | else if (attach >= attach_callback) | |
163 | { | |
164 | new_mapping->device = device; | |
165 | } | |
f2de7dfd | 166 | else { |
c967f187 | 167 | sim_io_error (sd, "new_sim_core_mapping - internal error - unknown attach type %d\n", |
a34abff8 | 168 | attach); |
f2de7dfd AC |
169 | } |
170 | return new_mapping; | |
171 | } | |
172 | ||
173 | ||
cd0d873d | 174 | STATIC_SIM_CORE\ |
f2de7dfd | 175 | (void) |
a34abff8 AC |
176 | sim_core_map_attach (SIM_DESC sd, |
177 | sim_core_map *access_map, | |
178 | attach_type attach, | |
179 | int space, | |
180 | address_word addr, | |
181 | address_word nr_bytes, | |
182 | unsigned modulo, | |
183 | device *client, /*callback/default*/ | |
184 | void *buffer, /*raw_memory*/ | |
185 | int free_buffer) /*raw_memory*/ | |
f2de7dfd AC |
186 | { |
187 | /* find the insertion point for this additional mapping and then | |
188 | insert */ | |
c967f187 DE |
189 | sim_core_mapping *next_mapping; |
190 | sim_core_mapping **last_mapping; | |
f2de7dfd | 191 | |
a34abff8 AC |
192 | SIM_ASSERT ((attach >= attach_callback) |
193 | <= (client != NULL && buffer == NULL && !free_buffer)); | |
194 | SIM_ASSERT ((attach == attach_raw_memory) | |
195 | <= (client == NULL && buffer != NULL)); | |
f2de7dfd AC |
196 | |
197 | /* actually do occasionally get a zero size map */ | |
a34abff8 AC |
198 | if (nr_bytes == 0) |
199 | { | |
f2de7dfd | 200 | #if (WITH_DEVICES) |
a34abff8 | 201 | device_error(client, "called on sim_core_map_attach with size zero"); |
f2de7dfd | 202 | #else |
a34abff8 | 203 | sim_io_error (sd, "called on sim_core_map_attach with size zero"); |
f2de7dfd | 204 | #endif |
a34abff8 | 205 | } |
f2de7dfd AC |
206 | |
207 | /* find the insertion point (between last/next) */ | |
208 | next_mapping = access_map->first; | |
209 | last_mapping = &access_map->first; | |
210 | while(next_mapping != NULL | |
f90b720b AC |
211 | && (next_mapping->level < (int) attach |
212 | || (next_mapping->level == (int) attach | |
a34abff8 AC |
213 | && next_mapping->bound < addr))) |
214 | { | |
215 | /* provided levels are the same */ | |
216 | /* assert: next_mapping->base > all bases before next_mapping */ | |
217 | /* assert: next_mapping->bound >= all bounds before next_mapping */ | |
218 | last_mapping = &next_mapping->next; | |
219 | next_mapping = next_mapping->next; | |
220 | } | |
221 | ||
f2de7dfd | 222 | /* check insertion point correct */ |
f90b720b AC |
223 | SIM_ASSERT (next_mapping == NULL || next_mapping->level >= (int) attach); |
224 | if (next_mapping != NULL && next_mapping->level == (int) attach | |
80c651f0 AC |
225 | && next_mapping->base < (addr + (nr_bytes - 1))) |
226 | { | |
f2de7dfd | 227 | #if (WITH_DEVICES) |
80c651f0 AC |
228 | device_error (client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)", |
229 | space, | |
230 | (long) addr, | |
231 | (long) nr_bytes, | |
232 | (long) (addr + (nr_bytes - 1)), | |
233 | next_mapping->space, | |
234 | (long) next_mapping->base, | |
235 | (long) next_mapping->bound, | |
236 | (long) next_mapping->nr_bytes); | |
f2de7dfd | 237 | #else |
80c651f0 AC |
238 | sim_io_error (sd, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)", |
239 | space, | |
240 | (long) addr, | |
241 | (long) nr_bytes, | |
242 | (long) (addr + (nr_bytes - 1)), | |
243 | next_mapping->space, | |
244 | (long) next_mapping->base, | |
245 | (long) next_mapping->bound, | |
246 | (long) next_mapping->nr_bytes); | |
f2de7dfd AC |
247 | #endif |
248 | } | |
249 | ||
250 | /* create/insert the new mapping */ | |
c967f187 | 251 | *last_mapping = new_sim_core_mapping(sd, |
80c651f0 | 252 | attach, |
a34abff8 | 253 | space, addr, nr_bytes, modulo, |
80c651f0 | 254 | client, buffer, free_buffer); |
f2de7dfd AC |
255 | (*last_mapping)->next = next_mapping; |
256 | } | |
257 | ||
258 | ||
cd0d873d | 259 | EXTERN_SIM_CORE\ |
f2de7dfd | 260 | (void) |
a34abff8 AC |
261 | sim_core_attach (SIM_DESC sd, |
262 | sim_cpu *cpu, | |
263 | attach_type attach, | |
264 | access_type access, | |
265 | int space, | |
266 | address_word addr, | |
267 | address_word nr_bytes, | |
268 | unsigned modulo, | |
269 | device *client, | |
270 | void *optional_buffer) | |
f2de7dfd | 271 | { |
1fe05280 | 272 | sim_core *memory = STATE_CORE(sd); |
c967f187 | 273 | sim_core_maps map; |
f2de7dfd AC |
274 | void *buffer; |
275 | int buffer_freed; | |
7a418800 AC |
276 | |
277 | /* check for for attempt to use unimplemented per-processor core map */ | |
278 | if (cpu != NULL) | |
279 | sim_io_error (sd, "sim_core_map_attach - processor specific memory map not yet supported"); | |
280 | ||
f2de7dfd | 281 | if ((access & access_read_write_exec) == 0 |
a34abff8 AC |
282 | || (access & ~access_read_write_exec) != 0) |
283 | { | |
f2de7dfd | 284 | #if (WITH_DEVICES) |
a34abff8 | 285 | device_error(client, "invalid access for core attach"); |
f2de7dfd | 286 | #else |
a34abff8 | 287 | sim_io_error (sd, "invalid access for core attach"); |
f2de7dfd | 288 | #endif |
a34abff8 AC |
289 | } |
290 | ||
f2de7dfd | 291 | /* verify the attach type */ |
a34abff8 AC |
292 | if (attach == attach_raw_memory) |
293 | { | |
294 | if (WITH_MODULO_MEMORY && modulo != 0) | |
295 | { | |
296 | unsigned mask = modulo - 1; | |
297 | if (mask < 7) /* 8 is minimum modulo */ | |
298 | mask = 0; | |
299 | while (mask > 1) /* no zero bits */ | |
1bba340a AC |
300 | { |
301 | if ((mask & 1) == 0) | |
302 | mask = 0; | |
303 | else | |
304 | mask >>= 1; | |
305 | } | |
a34abff8 AC |
306 | if (mask == 0) |
307 | { | |
308 | #if (WITH_DEVICES) | |
309 | device_error (client, "sim_core_attach - internal error - modulo not power of two"); | |
310 | #else | |
311 | sim_io_error (sd, "sim_core_attach - internal error - modulo not power of two"); | |
312 | #endif | |
313 | } | |
314 | } | |
1bba340a | 315 | else if (!WITH_MODULO_MEMORY && modulo != 0) |
a34abff8 AC |
316 | { |
317 | #if (WITH_DEVICES) | |
318 | device_error (client, "sim_core_attach - internal error - modulo memory disabled"); | |
319 | #else | |
320 | sim_io_error (sd, "sim_core_attach - internal error - modulo memory disabled"); | |
321 | #endif | |
322 | } | |
323 | if (optional_buffer == NULL) | |
324 | { | |
325 | buffer = zalloc (modulo == 0 ? nr_bytes : modulo); | |
326 | buffer_freed = 0; | |
327 | } | |
328 | else | |
329 | { | |
330 | buffer = optional_buffer; | |
331 | buffer_freed = 1; | |
332 | } | |
f2de7dfd | 333 | } |
a34abff8 AC |
334 | else if (attach >= attach_callback) |
335 | { | |
336 | buffer = NULL; | |
f2de7dfd AC |
337 | buffer_freed = 1; |
338 | } | |
a34abff8 AC |
339 | else |
340 | { | |
f2de7dfd | 341 | #if (WITH_DEVICES) |
a34abff8 | 342 | device_error (client, "sim_core_attach - internal error - conflicting buffer and attach arguments"); |
f2de7dfd | 343 | #else |
a34abff8 | 344 | sim_io_error (sd, "sim_core_attach - internal error - conflicting buffer and attach arguments"); |
f2de7dfd | 345 | #endif |
a34abff8 AC |
346 | buffer = NULL; |
347 | buffer_freed = 1; | |
348 | } | |
349 | ||
f2de7dfd AC |
350 | /* attach the region to all applicable access maps */ |
351 | for (map = 0; | |
c967f187 | 352 | map < nr_sim_core_maps; |
a34abff8 AC |
353 | map++) |
354 | { | |
355 | switch (map) | |
356 | { | |
357 | case sim_core_read_map: | |
358 | if (access & access_read) | |
359 | sim_core_map_attach (sd, &memory->common.map[map], | |
360 | attach, | |
361 | space, addr, nr_bytes, modulo, | |
362 | client, buffer, !buffer_freed); | |
363 | buffer_freed ++; | |
364 | break; | |
365 | case sim_core_write_map: | |
366 | if (access & access_write) | |
367 | sim_core_map_attach (sd, &memory->common.map[map], | |
368 | attach, | |
369 | space, addr, nr_bytes, modulo, | |
370 | client, buffer, !buffer_freed); | |
371 | buffer_freed ++; | |
372 | break; | |
373 | case sim_core_execute_map: | |
374 | if (access & access_exec) | |
375 | sim_core_map_attach (sd, &memory->common.map[map], | |
376 | attach, | |
377 | space, addr, nr_bytes, modulo, | |
378 | client, buffer, !buffer_freed); | |
379 | buffer_freed ++; | |
380 | break; | |
381 | case nr_sim_core_maps: | |
382 | sim_io_error (sd, "sim_core_attach - internal error - bad switch"); | |
383 | break; | |
384 | } | |
f2de7dfd | 385 | } |
a34abff8 | 386 | |
7a418800 AC |
387 | /* Just copy this map to each of the processor specific data structures. |
388 | FIXME - later this will be replaced by true processor specific | |
389 | maps. */ | |
f90b720b AC |
390 | { |
391 | int i; | |
392 | for (i = 0; i < MAX_NR_PROCESSORS; i++) | |
393 | { | |
394 | CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common; | |
395 | } | |
396 | } | |
f2de7dfd AC |
397 | } |
398 | ||
399 | ||
a34abff8 AC |
400 | /* Remove any memory reference related to this address */ |
401 | STATIC_INLINE_SIM_CORE\ | |
402 | (void) | |
403 | sim_core_map_detach (SIM_DESC sd, | |
404 | sim_core_map *access_map, | |
405 | attach_type attach, | |
406 | int space, | |
407 | address_word addr) | |
408 | { | |
409 | sim_core_mapping **entry; | |
410 | for (entry = &access_map->first; | |
411 | (*entry) != NULL; | |
412 | entry = &(*entry)->next) | |
413 | { | |
414 | if ((*entry)->base == addr | |
30efae3a | 415 | && (*entry)->level == (int) attach |
a34abff8 AC |
416 | && (*entry)->space == space) |
417 | { | |
418 | sim_core_mapping *dead = (*entry); | |
419 | (*entry) = dead->next; | |
420 | if (dead->free_buffer) | |
421 | zfree (dead->buffer); | |
422 | zfree (dead); | |
423 | return; | |
424 | } | |
425 | } | |
426 | } | |
427 | ||
428 | EXTERN_SIM_CORE\ | |
429 | (void) | |
430 | sim_core_detach (SIM_DESC sd, | |
431 | sim_cpu *cpu, | |
432 | attach_type attach, | |
433 | int address_space, | |
434 | address_word addr) | |
435 | { | |
436 | sim_core *memory = STATE_CORE (sd); | |
437 | sim_core_maps map; | |
438 | for (map = 0; map < nr_sim_core_maps; map++) | |
439 | { | |
440 | sim_core_map_detach (sd, &memory->common.map[map], | |
441 | attach, address_space, addr); | |
442 | } | |
443 | /* Just copy this update to each of the processor specific data | |
444 | structures. FIXME - later this will be replaced by true | |
445 | processor specific maps. */ | |
446 | { | |
447 | int i; | |
448 | for (i = 0; i < MAX_NR_PROCESSORS; i++) | |
449 | { | |
450 | CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common; | |
451 | } | |
452 | } | |
453 | } | |
454 | ||
455 | ||
f2de7dfd | 456 | STATIC_INLINE_SIM_CORE\ |
c967f187 | 457 | (sim_core_mapping *) |
f90b720b | 458 | sim_core_find_mapping(sim_core_common *core, |
c967f187 | 459 | sim_core_maps map, |
cd0d873d | 460 | address_word addr, |
f2de7dfd | 461 | unsigned nr_bytes, |
50a2a691 | 462 | transfer_type transfer, |
7a418800 AC |
463 | int abort, /*either 0 or 1 - hint to inline/-O */ |
464 | sim_cpu *cpu, /* abort => cpu != NULL */ | |
1fe05280 | 465 | sim_cia cia) |
f2de7dfd | 466 | { |
7a418800 AC |
467 | sim_core_mapping *mapping = core->map[map].first; |
468 | ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */ | |
469 | ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */ | |
470 | ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */ | |
471 | while (mapping != NULL) | |
472 | { | |
473 | if (addr >= mapping->base | |
474 | && (addr + (nr_bytes - 1)) <= mapping->bound) | |
475 | return mapping; | |
476 | mapping = mapping->next; | |
477 | } | |
f2de7dfd | 478 | if (abort) |
7a418800 | 479 | { |
50a2a691 AC |
480 | SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, nr_bytes, addr, transfer, |
481 | sim_core_unmapped_signal); | |
7a418800 | 482 | } |
f2de7dfd AC |
483 | return NULL; |
484 | } | |
485 | ||
486 | ||
487 | STATIC_INLINE_SIM_CORE\ | |
488 | (void *) | |
f90b720b AC |
489 | sim_core_translate (sim_core_mapping *mapping, |
490 | address_word addr) | |
f2de7dfd | 491 | { |
a34abff8 AC |
492 | if (WITH_MODULO_MEMORY) |
493 | return (void *)((unsigned8 *) mapping->buffer | |
494 | + ((addr - mapping->base) & mapping->mask)); | |
495 | else | |
496 | return (void *)((unsigned8 *) mapping->buffer | |
497 | + addr - mapping->base); | |
f2de7dfd AC |
498 | } |
499 | ||
500 | ||
cd0d873d | 501 | EXTERN_SIM_CORE\ |
f2de7dfd | 502 | (unsigned) |
f90b720b AC |
503 | sim_core_read_buffer (SIM_DESC sd, |
504 | sim_cpu *cpu, | |
505 | sim_core_maps map, | |
506 | void *buffer, | |
507 | address_word addr, | |
508 | unsigned len) | |
f2de7dfd | 509 | { |
f90b720b | 510 | sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common); |
f2de7dfd AC |
511 | unsigned count = 0; |
512 | while (count < len) { | |
513 | unsigned_word raddr = addr + count; | |
c967f187 | 514 | sim_core_mapping *mapping = |
f90b720b | 515 | sim_core_find_mapping(core, map, |
50a2a691 AC |
516 | raddr, /*nr-bytes*/1, |
517 | read_transfer, | |
f90b720b | 518 | 0 /*dont-abort*/, NULL, NULL_CIA); |
f2de7dfd AC |
519 | if (mapping == NULL) |
520 | break; | |
521 | #if (WITH_DEVICES) | |
522 | if (mapping->device != NULL) { | |
523 | int nr_bytes = len - count; | |
524 | if (raddr + nr_bytes - 1> mapping->bound) | |
525 | nr_bytes = mapping->bound - raddr + 1; | |
526 | if (device_io_read_buffer(mapping->device, | |
527 | (unsigned_1*)buffer + count, | |
528 | mapping->space, | |
529 | raddr, | |
530 | nr_bytes) != nr_bytes) | |
531 | break; | |
532 | count += nr_bytes; | |
533 | } | |
534 | else | |
535 | #endif | |
536 | { | |
537 | ((unsigned_1*)buffer)[count] = | |
c967f187 | 538 | *(unsigned_1*)sim_core_translate(mapping, raddr); |
f2de7dfd AC |
539 | count += 1; |
540 | } | |
541 | } | |
542 | return count; | |
543 | } | |
544 | ||
545 | ||
cd0d873d | 546 | EXTERN_SIM_CORE\ |
f2de7dfd | 547 | (unsigned) |
f90b720b AC |
548 | sim_core_write_buffer (SIM_DESC sd, |
549 | sim_cpu *cpu, | |
550 | sim_core_maps map, | |
551 | const void *buffer, | |
552 | address_word addr, | |
553 | unsigned len) | |
f2de7dfd | 554 | { |
f90b720b | 555 | sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common); |
f2de7dfd AC |
556 | unsigned count = 0; |
557 | while (count < len) { | |
558 | unsigned_word raddr = addr + count; | |
f90b720b AC |
559 | sim_core_mapping *mapping = |
560 | sim_core_find_mapping(core, map, | |
561 | raddr, /*nr-bytes*/1, | |
562 | write_transfer, | |
563 | 0 /*dont-abort*/, NULL, NULL_CIA); | |
f2de7dfd AC |
564 | if (mapping == NULL) |
565 | break; | |
566 | #if (WITH_DEVICES) | |
567 | if (WITH_CALLBACK_MEMORY | |
568 | && mapping->device != NULL) { | |
569 | int nr_bytes = len - count; | |
570 | if (raddr + nr_bytes - 1 > mapping->bound) | |
571 | nr_bytes = mapping->bound - raddr + 1; | |
572 | if (device_io_write_buffer(mapping->device, | |
573 | (unsigned_1*)buffer + count, | |
574 | mapping->space, | |
575 | raddr, | |
576 | nr_bytes) != nr_bytes) | |
577 | break; | |
578 | count += nr_bytes; | |
579 | } | |
580 | else | |
581 | #endif | |
582 | { | |
c967f187 | 583 | *(unsigned_1*)sim_core_translate(mapping, raddr) = |
f2de7dfd AC |
584 | ((unsigned_1*)buffer)[count]; |
585 | count += 1; | |
586 | } | |
587 | } | |
588 | return count; | |
589 | } | |
590 | ||
591 | ||
cd0d873d AC |
592 | EXTERN_SIM_CORE\ |
593 | (void) | |
f90b720b AC |
594 | sim_core_set_xor (SIM_DESC sd, |
595 | sim_cpu *cpu, | |
cd0d873d AC |
596 | int is_xor) |
597 | { | |
f90b720b | 598 | /* set up the XOR map if required. */ |
cd0d873d AC |
599 | if (WITH_XOR_ENDIAN) { |
600 | { | |
f90b720b AC |
601 | sim_core *core = STATE_CORE (sd); |
602 | sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL); | |
603 | if (cpu_core != NULL) | |
cd0d873d | 604 | { |
f90b720b AC |
605 | int i = 1; |
606 | unsigned mask; | |
607 | if (is_xor) | |
608 | mask = WITH_XOR_ENDIAN - 1; | |
609 | else | |
610 | mask = 0; | |
611 | while (i - 1 < WITH_XOR_ENDIAN) | |
612 | { | |
613 | cpu_core->xor[i-1] = mask; | |
614 | mask = (mask << 1) & (WITH_XOR_ENDIAN - 1); | |
615 | i = (i << 1); | |
616 | } | |
cd0d873d | 617 | } |
f90b720b AC |
618 | else |
619 | { | |
620 | if (is_xor) | |
621 | core->byte_xor = WITH_XOR_ENDIAN - 1; | |
622 | else | |
623 | core->byte_xor = 0; | |
624 | } | |
cd0d873d AC |
625 | } |
626 | } | |
627 | else { | |
628 | if (is_xor) | |
f90b720b | 629 | sim_engine_abort (sd, cpu, NULL_CIA, |
cd0d873d AC |
630 | "Attempted to enable xor-endian mode when permenantly disabled."); |
631 | } | |
632 | } | |
633 | ||
f90b720b AC |
634 | STATIC_INLINE_SIM_CORE\ |
635 | (void) | |
636 | reverse_n (unsigned_1 *dest, | |
637 | const unsigned_1 *src, | |
638 | int nr_bytes) | |
639 | { | |
640 | int i; | |
641 | for (i = 0; i < nr_bytes; i++) | |
642 | { | |
643 | dest [nr_bytes - i - 1] = src [i]; | |
644 | } | |
645 | } | |
646 | ||
647 | ||
648 | EXTERN_SIM_CORE\ | |
649 | (unsigned) | |
650 | sim_core_xor_read_buffer (SIM_DESC sd, | |
651 | sim_cpu *cpu, | |
652 | sim_core_maps map, | |
653 | void *buffer, | |
654 | address_word addr, | |
655 | unsigned nr_bytes) | |
656 | { | |
657 | address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]); | |
658 | if (!WITH_XOR_ENDIAN || !byte_xor) | |
659 | return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes); | |
660 | else | |
661 | /* only break up transfers when xor-endian is both selected and enabled */ | |
662 | { | |
31dda65a | 663 | unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */ |
f90b720b AC |
664 | unsigned nr_transfered = 0; |
665 | address_word start = addr; | |
666 | unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1))); | |
667 | address_word stop; | |
668 | /* initial and intermediate transfers are broken when they cross | |
669 | an XOR endian boundary */ | |
670 | while (nr_transfered + nr_this_transfer < nr_bytes) | |
671 | /* initial/intermediate transfers */ | |
672 | { | |
673 | /* since xor-endian is enabled stop^xor defines the start | |
674 | address of the transfer */ | |
675 | stop = start + nr_this_transfer - 1; | |
676 | SIM_ASSERT (start <= stop); | |
677 | SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor)); | |
678 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
679 | != nr_this_transfer) | |
680 | return nr_transfered; | |
681 | reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer); | |
682 | nr_transfered += nr_this_transfer; | |
683 | nr_this_transfer = WITH_XOR_ENDIAN; | |
684 | start = stop + 1; | |
685 | } | |
686 | /* final transfer */ | |
687 | nr_this_transfer = nr_bytes - nr_transfered; | |
688 | stop = start + nr_this_transfer - 1; | |
689 | SIM_ASSERT (stop == (addr + nr_bytes - 1)); | |
690 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
691 | != nr_this_transfer) | |
692 | return nr_transfered; | |
693 | reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer); | |
694 | return nr_bytes; | |
695 | } | |
696 | } | |
697 | ||
698 | ||
699 | EXTERN_SIM_CORE\ | |
700 | (unsigned) | |
701 | sim_core_xor_write_buffer (SIM_DESC sd, | |
702 | sim_cpu *cpu, | |
703 | sim_core_maps map, | |
704 | const void *buffer, | |
705 | address_word addr, | |
706 | unsigned nr_bytes) | |
707 | { | |
708 | address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]); | |
709 | if (!WITH_XOR_ENDIAN || !byte_xor) | |
710 | return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes); | |
711 | else | |
712 | /* only break up transfers when xor-endian is both selected and enabled */ | |
713 | { | |
714 | unsigned_1 x[WITH_XOR_ENDIAN]; | |
715 | unsigned nr_transfered = 0; | |
716 | address_word start = addr; | |
717 | unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1))); | |
718 | address_word stop; | |
719 | /* initial and intermediate transfers are broken when they cross | |
720 | an XOR endian boundary */ | |
721 | while (nr_transfered + nr_this_transfer < nr_bytes) | |
722 | /* initial/intermediate transfers */ | |
723 | { | |
724 | /* since xor-endian is enabled stop^xor defines the start | |
725 | address of the transfer */ | |
726 | stop = start + nr_this_transfer - 1; | |
727 | SIM_ASSERT (start <= stop); | |
728 | SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor)); | |
729 | reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer); | |
730 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
731 | != nr_this_transfer) | |
732 | return nr_transfered; | |
733 | nr_transfered += nr_this_transfer; | |
734 | nr_this_transfer = WITH_XOR_ENDIAN; | |
735 | start = stop + 1; | |
736 | } | |
737 | /* final transfer */ | |
738 | nr_this_transfer = nr_bytes - nr_transfered; | |
739 | stop = start + nr_this_transfer - 1; | |
740 | SIM_ASSERT (stop == (addr + nr_bytes - 1)); | |
741 | reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer); | |
742 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
743 | != nr_this_transfer) | |
744 | return nr_transfered; | |
745 | return nr_bytes; | |
746 | } | |
747 | } | |
cd0d873d AC |
748 | |
749 | ||
750 | ||
f2de7dfd AC |
751 | /* define the read/write 1/2/4/8/word functions */ |
752 | ||
753 | #define N 1 | |
754 | #include "sim-n-core.h" | |
755 | #undef N | |
756 | ||
757 | #define N 2 | |
758 | #include "sim-n-core.h" | |
759 | #undef N | |
760 | ||
761 | #define N 4 | |
762 | #include "sim-n-core.h" | |
763 | #undef N | |
764 | ||
765 | #define N 8 | |
766 | #include "sim-n-core.h" | |
767 | #undef N | |
768 | ||
769 | #define N word | |
770 | #include "sim-n-core.h" | |
771 | #undef N | |
772 | ||
773 | #endif |