Commit | Line | Data |
---|---|---|
f2de7dfd AC |
1 | /* This file is part of the program psim. |
2 | ||
3 | Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
17 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | ||
19 | */ | |
20 | ||
21 | ||
22 | #ifndef _SIM_CORE_C_ | |
23 | #define _SIM_CORE_C_ | |
24 | ||
c967f187 DE |
25 | #include "sim-main.h" |
26 | #include "sim-assert.h" | |
f2de7dfd AC |
27 | |
28 | ||
c967f187 | 29 | /* "core" module install handler. |
cd0d873d | 30 | |
c967f187 DE |
31 | This is called via sim_module_install to install the "core" subsystem |
32 | into the simulator. */ | |
33 | ||
cd0d873d AC |
34 | static MODULE_INIT_FN sim_core_init; |
35 | static MODULE_UNINSTALL_FN sim_core_uninstall; | |
36 | ||
c967f187 DE |
37 | EXTERN_SIM_CORE\ |
38 | (SIM_RC) | |
39 | sim_core_install (SIM_DESC sd) | |
40 | { | |
50a2a691 | 41 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); |
c967f187 DE |
42 | sim_module_add_uninstall_fn (sd, sim_core_uninstall); |
43 | sim_module_add_init_fn (sd, sim_core_init); | |
44 | return SIM_RC_OK; | |
45 | } | |
46 | ||
47 | ||
48 | /* Uninstall the "core" subsystem from the simulator. */ | |
49 | ||
cd0d873d | 50 | STATIC_SIM_CORE\ |
f2de7dfd | 51 | (void) |
c967f187 DE |
52 | sim_core_uninstall (SIM_DESC sd) |
53 | { | |
54 | /* FIXME: free buffers, etc. */ | |
55 | } | |
56 | ||
57 | ||
cd0d873d | 58 | STATIC_SIM_CORE\ |
c967f187 DE |
59 | (SIM_RC) |
60 | sim_core_init (SIM_DESC sd) | |
f2de7dfd | 61 | { |
f90b720b | 62 | sim_core *core = STATE_CORE(sd); |
c967f187 | 63 | sim_core_maps map; |
f90b720b | 64 | for (map = 0; map < nr_sim_core_maps; map++) { |
f2de7dfd | 65 | /* blow away old mappings */ |
f90b720b | 66 | sim_core_mapping *curr = core->common.map[map].first; |
f2de7dfd | 67 | while (curr != NULL) { |
c967f187 | 68 | sim_core_mapping *tbd = curr; |
f2de7dfd AC |
69 | curr = curr->next; |
70 | if (tbd->free_buffer) { | |
c967f187 | 71 | SIM_ASSERT(tbd->buffer != NULL); |
f2de7dfd AC |
72 | zfree(tbd->buffer); |
73 | } | |
74 | zfree(tbd); | |
75 | } | |
f90b720b AC |
76 | core->common.map[map].first = NULL; |
77 | } | |
78 | core->byte_xor = 0; | |
79 | /* Just copy this map to each of the processor specific data structures. | |
80 | FIXME - later this will be replaced by true processor specific | |
81 | maps. */ | |
82 | { | |
83 | int i; | |
84 | for (i = 0; i < MAX_NR_PROCESSORS; i++) | |
85 | { | |
86 | int j; | |
87 | CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common; | |
88 | for (j = 0; j < WITH_XOR_ENDIAN; j++) | |
89 | CPU_CORE (STATE_CPU (sd, i))->xor [j] = 0; | |
90 | } | |
f2de7dfd | 91 | } |
c967f187 | 92 | return SIM_RC_OK; |
f2de7dfd AC |
93 | } |
94 | ||
95 | ||
96 | ||
50a2a691 AC |
97 | #ifndef SIM_CORE_SIGNAL |
98 | #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ | |
99 | sim_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR)) | |
100 | ||
cd0d873d AC |
101 | STATIC_SIM_CORE\ |
102 | (void) | |
50a2a691 AC |
103 | sim_core_signal (SIM_DESC sd, |
104 | sim_cpu *cpu, | |
105 | sim_cia cia, | |
106 | sim_core_maps map, | |
107 | int nr_bytes, | |
108 | address_word addr, | |
109 | transfer_type transfer, | |
110 | sim_core_signals sig) | |
111 | { | |
112 | const char *copy = (transfer == read_transfer ? "read" : "write"); | |
113 | switch (sig) | |
114 | { | |
115 | case sim_core_unmapped_signal: | |
116 | sim_engine_abort (sd, cpu, cia, "sim-core: %d byte %s to unmaped address 0x%lx", | |
117 | nr_bytes, copy, (unsigned long) addr); | |
118 | break; | |
119 | case sim_core_unaligned_signal: | |
120 | sim_engine_abort (sd, cpu, cia, "sim-core: %d byte misaligned %s to address 0x%lx", | |
121 | nr_bytes, copy, (unsigned long) addr); | |
122 | break; | |
123 | default: | |
124 | sim_engine_abort (sd, cpu, cia, "sim_core_signal - internal error - bad switch"); | |
125 | } | |
126 | } | |
50a2a691 AC |
127 | #endif |
128 | ||
cd0d873d | 129 | |
1fe05280 AC |
130 | STATIC_INLINE_SIM_CORE\ |
131 | (const char *) | |
132 | sim_core_map_to_str (sim_core_maps map) | |
133 | { | |
134 | switch (map) | |
135 | { | |
136 | case sim_core_read_map: return "read"; | |
137 | case sim_core_write_map: return "write"; | |
138 | case sim_core_execute_map: return "exec"; | |
139 | default: return "(invalid-map)"; | |
140 | } | |
141 | } | |
142 | ||
143 | ||
cd0d873d | 144 | STATIC_SIM_CORE\ |
c967f187 DE |
145 | (sim_core_mapping *) |
146 | new_sim_core_mapping(SIM_DESC sd, | |
50a2a691 AC |
147 | attach_type attach, |
148 | int space, | |
cd0d873d | 149 | address_word addr, |
50a2a691 AC |
150 | unsigned nr_bytes, |
151 | device *device, | |
152 | void *buffer, | |
153 | int free_buffer) | |
f2de7dfd | 154 | { |
c967f187 | 155 | sim_core_mapping *new_mapping = ZALLOC(sim_core_mapping); |
f2de7dfd AC |
156 | /* common */ |
157 | new_mapping->level = attach; | |
158 | new_mapping->space = space; | |
159 | new_mapping->base = addr; | |
160 | new_mapping->nr_bytes = nr_bytes; | |
161 | new_mapping->bound = addr + (nr_bytes - 1); | |
162 | if (attach == attach_raw_memory) { | |
163 | new_mapping->buffer = buffer; | |
164 | new_mapping->free_buffer = free_buffer; | |
165 | } | |
166 | else if (attach >= attach_callback) { | |
167 | new_mapping->device = device; | |
168 | } | |
169 | else { | |
c967f187 | 170 | sim_io_error (sd, "new_sim_core_mapping - internal error - unknown attach type %d\n", |
f2de7dfd AC |
171 | attach); |
172 | } | |
173 | return new_mapping; | |
174 | } | |
175 | ||
176 | ||
cd0d873d | 177 | STATIC_SIM_CORE\ |
f2de7dfd | 178 | (void) |
c967f187 | 179 | sim_core_map_attach(SIM_DESC sd, |
7a418800 AC |
180 | sim_core_map *access_map, |
181 | attach_type attach, | |
182 | int space, | |
cd0d873d | 183 | address_word addr, |
7a418800 AC |
184 | unsigned nr_bytes, /* host limited */ |
185 | device *client, /*callback/default*/ | |
186 | void *buffer, /*raw_memory*/ | |
187 | int free_buffer) /*raw_memory*/ | |
f2de7dfd AC |
188 | { |
189 | /* find the insertion point for this additional mapping and then | |
190 | insert */ | |
c967f187 DE |
191 | sim_core_mapping *next_mapping; |
192 | sim_core_mapping **last_mapping; | |
f2de7dfd | 193 | |
c967f187 | 194 | SIM_ASSERT((attach >= attach_callback && client != NULL && buffer == NULL && !free_buffer) |
f2de7dfd AC |
195 | || (attach == attach_raw_memory && client == NULL && buffer != NULL)); |
196 | ||
197 | /* actually do occasionally get a zero size map */ | |
198 | if (nr_bytes == 0) { | |
199 | #if (WITH_DEVICES) | |
c967f187 | 200 | device_error(client, "called on sim_core_map_attach with size zero"); |
f2de7dfd | 201 | #else |
c967f187 | 202 | sim_io_error (sd, "called on sim_core_map_attach with size zero"); |
f2de7dfd AC |
203 | #endif |
204 | } | |
205 | ||
206 | /* find the insertion point (between last/next) */ | |
207 | next_mapping = access_map->first; | |
208 | last_mapping = &access_map->first; | |
209 | while(next_mapping != NULL | |
f90b720b AC |
210 | && (next_mapping->level < (int) attach |
211 | || (next_mapping->level == (int) attach | |
f2de7dfd AC |
212 | && next_mapping->bound < addr))) { |
213 | /* provided levels are the same */ | |
214 | /* assert: next_mapping->base > all bases before next_mapping */ | |
215 | /* assert: next_mapping->bound >= all bounds before next_mapping */ | |
216 | last_mapping = &next_mapping->next; | |
217 | next_mapping = next_mapping->next; | |
218 | } | |
219 | ||
220 | /* check insertion point correct */ | |
f90b720b AC |
221 | SIM_ASSERT (next_mapping == NULL || next_mapping->level >= (int) attach); |
222 | if (next_mapping != NULL && next_mapping->level == (int) attach | |
80c651f0 AC |
223 | && next_mapping->base < (addr + (nr_bytes - 1))) |
224 | { | |
f2de7dfd | 225 | #if (WITH_DEVICES) |
80c651f0 AC |
226 | device_error (client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)", |
227 | space, | |
228 | (long) addr, | |
229 | (long) nr_bytes, | |
230 | (long) (addr + (nr_bytes - 1)), | |
231 | next_mapping->space, | |
232 | (long) next_mapping->base, | |
233 | (long) next_mapping->bound, | |
234 | (long) next_mapping->nr_bytes); | |
f2de7dfd | 235 | #else |
80c651f0 AC |
236 | sim_io_error (sd, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)", |
237 | space, | |
238 | (long) addr, | |
239 | (long) nr_bytes, | |
240 | (long) (addr + (nr_bytes - 1)), | |
241 | next_mapping->space, | |
242 | (long) next_mapping->base, | |
243 | (long) next_mapping->bound, | |
244 | (long) next_mapping->nr_bytes); | |
f2de7dfd AC |
245 | #endif |
246 | } | |
247 | ||
248 | /* create/insert the new mapping */ | |
c967f187 | 249 | *last_mapping = new_sim_core_mapping(sd, |
80c651f0 AC |
250 | attach, |
251 | space, addr, nr_bytes, | |
252 | client, buffer, free_buffer); | |
f2de7dfd AC |
253 | (*last_mapping)->next = next_mapping; |
254 | } | |
255 | ||
256 | ||
cd0d873d | 257 | EXTERN_SIM_CORE\ |
f2de7dfd | 258 | (void) |
c967f187 | 259 | sim_core_attach(SIM_DESC sd, |
7a418800 AC |
260 | sim_cpu *cpu, |
261 | attach_type attach, | |
262 | access_type access, | |
263 | int space, | |
cd0d873d | 264 | address_word addr, |
7a418800 AC |
265 | unsigned nr_bytes, /* host limited */ |
266 | device *client, | |
267 | void *optional_buffer) | |
f2de7dfd | 268 | { |
1fe05280 | 269 | sim_core *memory = STATE_CORE(sd); |
c967f187 | 270 | sim_core_maps map; |
f2de7dfd AC |
271 | void *buffer; |
272 | int buffer_freed; | |
7a418800 AC |
273 | |
274 | /* check for for attempt to use unimplemented per-processor core map */ | |
275 | if (cpu != NULL) | |
276 | sim_io_error (sd, "sim_core_map_attach - processor specific memory map not yet supported"); | |
277 | ||
f2de7dfd AC |
278 | if ((access & access_read_write_exec) == 0 |
279 | || (access & ~access_read_write_exec) != 0) { | |
280 | #if (WITH_DEVICES) | |
281 | device_error(client, "invalid access for core attach"); | |
282 | #else | |
c967f187 | 283 | sim_io_error (sd, "invalid access for core attach"); |
f2de7dfd AC |
284 | #endif |
285 | } | |
286 | /* verify the attach type */ | |
287 | if (attach == attach_raw_memory) { | |
288 | if (optional_buffer == NULL) { | |
289 | buffer = zalloc(nr_bytes); | |
290 | buffer_freed = 0; | |
291 | } | |
292 | else { | |
293 | buffer = optional_buffer; | |
294 | buffer_freed = 1; | |
295 | } | |
296 | } | |
297 | else if (attach >= attach_callback) { | |
298 | buffer = NULL; | |
299 | buffer_freed = 1; | |
300 | } | |
301 | else { | |
302 | #if (WITH_DEVICES) | |
c967f187 | 303 | device_error(client, "sim_core_attach - conflicting buffer and attach arguments"); |
f2de7dfd | 304 | #else |
c967f187 | 305 | sim_io_error (sd, "sim_core_attach - conflicting buffer and attach arguments"); |
f2de7dfd AC |
306 | #endif |
307 | buffer = NULL; | |
308 | buffer_freed = 1; | |
309 | } | |
310 | /* attach the region to all applicable access maps */ | |
311 | for (map = 0; | |
c967f187 | 312 | map < nr_sim_core_maps; |
f2de7dfd AC |
313 | map++) { |
314 | switch (map) { | |
c967f187 | 315 | case sim_core_read_map: |
f2de7dfd | 316 | if (access & access_read) |
f90b720b AC |
317 | sim_core_map_attach(sd, &memory->common.map[map], |
318 | attach, | |
319 | space, addr, nr_bytes, | |
320 | client, buffer, !buffer_freed); | |
f2de7dfd AC |
321 | buffer_freed ++; |
322 | break; | |
c967f187 | 323 | case sim_core_write_map: |
f2de7dfd | 324 | if (access & access_write) |
f90b720b | 325 | sim_core_map_attach(sd, &memory->common.map[map], |
f2de7dfd AC |
326 | attach, |
327 | space, addr, nr_bytes, | |
328 | client, buffer, !buffer_freed); | |
329 | buffer_freed ++; | |
330 | break; | |
c967f187 | 331 | case sim_core_execute_map: |
f2de7dfd | 332 | if (access & access_exec) |
f90b720b | 333 | sim_core_map_attach(sd, &memory->common.map[map], |
f2de7dfd AC |
334 | attach, |
335 | space, addr, nr_bytes, | |
336 | client, buffer, !buffer_freed); | |
337 | buffer_freed ++; | |
338 | break; | |
c967f187 DE |
339 | case nr_sim_core_maps: |
340 | sim_io_error (sd, "sim_core_attach - internal error - bad switch"); | |
f2de7dfd AC |
341 | break; |
342 | } | |
343 | } | |
7a418800 AC |
344 | |
345 | /* Just copy this map to each of the processor specific data structures. | |
346 | FIXME - later this will be replaced by true processor specific | |
347 | maps. */ | |
f90b720b AC |
348 | { |
349 | int i; | |
350 | for (i = 0; i < MAX_NR_PROCESSORS; i++) | |
351 | { | |
352 | CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common; | |
353 | } | |
354 | } | |
f2de7dfd AC |
355 | } |
356 | ||
357 | ||
358 | STATIC_INLINE_SIM_CORE\ | |
c967f187 | 359 | (sim_core_mapping *) |
f90b720b | 360 | sim_core_find_mapping(sim_core_common *core, |
c967f187 | 361 | sim_core_maps map, |
cd0d873d | 362 | address_word addr, |
f2de7dfd | 363 | unsigned nr_bytes, |
50a2a691 | 364 | transfer_type transfer, |
7a418800 AC |
365 | int abort, /*either 0 or 1 - hint to inline/-O */ |
366 | sim_cpu *cpu, /* abort => cpu != NULL */ | |
1fe05280 | 367 | sim_cia cia) |
f2de7dfd | 368 | { |
7a418800 AC |
369 | sim_core_mapping *mapping = core->map[map].first; |
370 | ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */ | |
371 | ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */ | |
372 | ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */ | |
373 | while (mapping != NULL) | |
374 | { | |
375 | if (addr >= mapping->base | |
376 | && (addr + (nr_bytes - 1)) <= mapping->bound) | |
377 | return mapping; | |
378 | mapping = mapping->next; | |
379 | } | |
f2de7dfd | 380 | if (abort) |
7a418800 | 381 | { |
50a2a691 AC |
382 | SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, nr_bytes, addr, transfer, |
383 | sim_core_unmapped_signal); | |
7a418800 | 384 | } |
f2de7dfd AC |
385 | return NULL; |
386 | } | |
387 | ||
388 | ||
389 | STATIC_INLINE_SIM_CORE\ | |
390 | (void *) | |
f90b720b AC |
391 | sim_core_translate (sim_core_mapping *mapping, |
392 | address_word addr) | |
f2de7dfd AC |
393 | { |
394 | return (void *)(((char *)mapping->buffer) + addr - mapping->base); | |
395 | } | |
396 | ||
397 | ||
cd0d873d | 398 | EXTERN_SIM_CORE\ |
f2de7dfd | 399 | (unsigned) |
f90b720b AC |
400 | sim_core_read_buffer (SIM_DESC sd, |
401 | sim_cpu *cpu, | |
402 | sim_core_maps map, | |
403 | void *buffer, | |
404 | address_word addr, | |
405 | unsigned len) | |
f2de7dfd | 406 | { |
f90b720b | 407 | sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common); |
f2de7dfd AC |
408 | unsigned count = 0; |
409 | while (count < len) { | |
410 | unsigned_word raddr = addr + count; | |
c967f187 | 411 | sim_core_mapping *mapping = |
f90b720b | 412 | sim_core_find_mapping(core, map, |
50a2a691 AC |
413 | raddr, /*nr-bytes*/1, |
414 | read_transfer, | |
f90b720b | 415 | 0 /*dont-abort*/, NULL, NULL_CIA); |
f2de7dfd AC |
416 | if (mapping == NULL) |
417 | break; | |
418 | #if (WITH_DEVICES) | |
419 | if (mapping->device != NULL) { | |
420 | int nr_bytes = len - count; | |
421 | if (raddr + nr_bytes - 1> mapping->bound) | |
422 | nr_bytes = mapping->bound - raddr + 1; | |
423 | if (device_io_read_buffer(mapping->device, | |
424 | (unsigned_1*)buffer + count, | |
425 | mapping->space, | |
426 | raddr, | |
427 | nr_bytes) != nr_bytes) | |
428 | break; | |
429 | count += nr_bytes; | |
430 | } | |
431 | else | |
432 | #endif | |
433 | { | |
434 | ((unsigned_1*)buffer)[count] = | |
c967f187 | 435 | *(unsigned_1*)sim_core_translate(mapping, raddr); |
f2de7dfd AC |
436 | count += 1; |
437 | } | |
438 | } | |
439 | return count; | |
440 | } | |
441 | ||
442 | ||
cd0d873d | 443 | EXTERN_SIM_CORE\ |
f2de7dfd | 444 | (unsigned) |
f90b720b AC |
445 | sim_core_write_buffer (SIM_DESC sd, |
446 | sim_cpu *cpu, | |
447 | sim_core_maps map, | |
448 | const void *buffer, | |
449 | address_word addr, | |
450 | unsigned len) | |
f2de7dfd | 451 | { |
f90b720b | 452 | sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common); |
f2de7dfd AC |
453 | unsigned count = 0; |
454 | while (count < len) { | |
455 | unsigned_word raddr = addr + count; | |
f90b720b AC |
456 | sim_core_mapping *mapping = |
457 | sim_core_find_mapping(core, map, | |
458 | raddr, /*nr-bytes*/1, | |
459 | write_transfer, | |
460 | 0 /*dont-abort*/, NULL, NULL_CIA); | |
f2de7dfd AC |
461 | if (mapping == NULL) |
462 | break; | |
463 | #if (WITH_DEVICES) | |
464 | if (WITH_CALLBACK_MEMORY | |
465 | && mapping->device != NULL) { | |
466 | int nr_bytes = len - count; | |
467 | if (raddr + nr_bytes - 1 > mapping->bound) | |
468 | nr_bytes = mapping->bound - raddr + 1; | |
469 | if (device_io_write_buffer(mapping->device, | |
470 | (unsigned_1*)buffer + count, | |
471 | mapping->space, | |
472 | raddr, | |
473 | nr_bytes) != nr_bytes) | |
474 | break; | |
475 | count += nr_bytes; | |
476 | } | |
477 | else | |
478 | #endif | |
479 | { | |
c967f187 | 480 | *(unsigned_1*)sim_core_translate(mapping, raddr) = |
f2de7dfd AC |
481 | ((unsigned_1*)buffer)[count]; |
482 | count += 1; | |
483 | } | |
484 | } | |
485 | return count; | |
486 | } | |
487 | ||
488 | ||
cd0d873d AC |
489 | EXTERN_SIM_CORE\ |
490 | (void) | |
f90b720b AC |
491 | sim_core_set_xor (SIM_DESC sd, |
492 | sim_cpu *cpu, | |
cd0d873d AC |
493 | int is_xor) |
494 | { | |
f90b720b | 495 | /* set up the XOR map if required. */ |
cd0d873d AC |
496 | if (WITH_XOR_ENDIAN) { |
497 | { | |
f90b720b AC |
498 | sim_core *core = STATE_CORE (sd); |
499 | sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL); | |
500 | if (cpu_core != NULL) | |
cd0d873d | 501 | { |
f90b720b AC |
502 | int i = 1; |
503 | unsigned mask; | |
504 | if (is_xor) | |
505 | mask = WITH_XOR_ENDIAN - 1; | |
506 | else | |
507 | mask = 0; | |
508 | while (i - 1 < WITH_XOR_ENDIAN) | |
509 | { | |
510 | cpu_core->xor[i-1] = mask; | |
511 | mask = (mask << 1) & (WITH_XOR_ENDIAN - 1); | |
512 | i = (i << 1); | |
513 | } | |
cd0d873d | 514 | } |
f90b720b AC |
515 | else |
516 | { | |
517 | if (is_xor) | |
518 | core->byte_xor = WITH_XOR_ENDIAN - 1; | |
519 | else | |
520 | core->byte_xor = 0; | |
521 | } | |
cd0d873d AC |
522 | } |
523 | } | |
524 | else { | |
525 | if (is_xor) | |
f90b720b | 526 | sim_engine_abort (sd, cpu, NULL_CIA, |
cd0d873d AC |
527 | "Attempted to enable xor-endian mode when permenantly disabled."); |
528 | } | |
529 | } | |
530 | ||
f90b720b AC |
531 | STATIC_INLINE_SIM_CORE\ |
532 | (void) | |
533 | reverse_n (unsigned_1 *dest, | |
534 | const unsigned_1 *src, | |
535 | int nr_bytes) | |
536 | { | |
537 | int i; | |
538 | for (i = 0; i < nr_bytes; i++) | |
539 | { | |
540 | dest [nr_bytes - i - 1] = src [i]; | |
541 | } | |
542 | } | |
543 | ||
544 | ||
545 | EXTERN_SIM_CORE\ | |
546 | (unsigned) | |
547 | sim_core_xor_read_buffer (SIM_DESC sd, | |
548 | sim_cpu *cpu, | |
549 | sim_core_maps map, | |
550 | void *buffer, | |
551 | address_word addr, | |
552 | unsigned nr_bytes) | |
553 | { | |
554 | address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]); | |
555 | if (!WITH_XOR_ENDIAN || !byte_xor) | |
556 | return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes); | |
557 | else | |
558 | /* only break up transfers when xor-endian is both selected and enabled */ | |
559 | { | |
560 | unsigned_1 x[WITH_XOR_ENDIAN]; | |
561 | unsigned nr_transfered = 0; | |
562 | address_word start = addr; | |
563 | unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1))); | |
564 | address_word stop; | |
565 | /* initial and intermediate transfers are broken when they cross | |
566 | an XOR endian boundary */ | |
567 | while (nr_transfered + nr_this_transfer < nr_bytes) | |
568 | /* initial/intermediate transfers */ | |
569 | { | |
570 | /* since xor-endian is enabled stop^xor defines the start | |
571 | address of the transfer */ | |
572 | stop = start + nr_this_transfer - 1; | |
573 | SIM_ASSERT (start <= stop); | |
574 | SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor)); | |
575 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
576 | != nr_this_transfer) | |
577 | return nr_transfered; | |
578 | reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer); | |
579 | nr_transfered += nr_this_transfer; | |
580 | nr_this_transfer = WITH_XOR_ENDIAN; | |
581 | start = stop + 1; | |
582 | } | |
583 | /* final transfer */ | |
584 | nr_this_transfer = nr_bytes - nr_transfered; | |
585 | stop = start + nr_this_transfer - 1; | |
586 | SIM_ASSERT (stop == (addr + nr_bytes - 1)); | |
587 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
588 | != nr_this_transfer) | |
589 | return nr_transfered; | |
590 | reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer); | |
591 | return nr_bytes; | |
592 | } | |
593 | } | |
594 | ||
595 | ||
596 | EXTERN_SIM_CORE\ | |
597 | (unsigned) | |
598 | sim_core_xor_write_buffer (SIM_DESC sd, | |
599 | sim_cpu *cpu, | |
600 | sim_core_maps map, | |
601 | const void *buffer, | |
602 | address_word addr, | |
603 | unsigned nr_bytes) | |
604 | { | |
605 | address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]); | |
606 | if (!WITH_XOR_ENDIAN || !byte_xor) | |
607 | return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes); | |
608 | else | |
609 | /* only break up transfers when xor-endian is both selected and enabled */ | |
610 | { | |
611 | unsigned_1 x[WITH_XOR_ENDIAN]; | |
612 | unsigned nr_transfered = 0; | |
613 | address_word start = addr; | |
614 | unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1))); | |
615 | address_word stop; | |
616 | /* initial and intermediate transfers are broken when they cross | |
617 | an XOR endian boundary */ | |
618 | while (nr_transfered + nr_this_transfer < nr_bytes) | |
619 | /* initial/intermediate transfers */ | |
620 | { | |
621 | /* since xor-endian is enabled stop^xor defines the start | |
622 | address of the transfer */ | |
623 | stop = start + nr_this_transfer - 1; | |
624 | SIM_ASSERT (start <= stop); | |
625 | SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor)); | |
626 | reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer); | |
627 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
628 | != nr_this_transfer) | |
629 | return nr_transfered; | |
630 | nr_transfered += nr_this_transfer; | |
631 | nr_this_transfer = WITH_XOR_ENDIAN; | |
632 | start = stop + 1; | |
633 | } | |
634 | /* final transfer */ | |
635 | nr_this_transfer = nr_bytes - nr_transfered; | |
636 | stop = start + nr_this_transfer - 1; | |
637 | SIM_ASSERT (stop == (addr + nr_bytes - 1)); | |
638 | reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer); | |
639 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
640 | != nr_this_transfer) | |
641 | return nr_transfered; | |
642 | return nr_bytes; | |
643 | } | |
644 | } | |
cd0d873d AC |
645 | |
646 | ||
647 | ||
f2de7dfd AC |
648 | /* define the read/write 1/2/4/8/word functions */ |
649 | ||
650 | #define N 1 | |
651 | #include "sim-n-core.h" | |
652 | #undef N | |
653 | ||
654 | #define N 2 | |
655 | #include "sim-n-core.h" | |
656 | #undef N | |
657 | ||
658 | #define N 4 | |
659 | #include "sim-n-core.h" | |
660 | #undef N | |
661 | ||
662 | #define N 8 | |
663 | #include "sim-n-core.h" | |
664 | #undef N | |
665 | ||
666 | #define N word | |
667 | #include "sim-n-core.h" | |
668 | #undef N | |
669 | ||
670 | #endif |