Commit | Line | Data |
---|---|---|
f2de7dfd AC |
1 | /* This file is part of the program psim. |
2 | ||
3 | Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
17 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | ||
19 | */ | |
20 | ||
21 | ||
22 | #ifndef _SIM_CORE_C_ | |
23 | #define _SIM_CORE_C_ | |
24 | ||
c967f187 DE |
25 | #include "sim-main.h" |
26 | #include "sim-assert.h" | |
f2de7dfd | 27 | |
fd89abc2 AC |
28 | #include <signal.h> |
29 | ||
30 | /* for Windows builds. signal numbers used by MSVC are mostly | |
31 | the same as non-linux unixen. */ | |
32 | #ifndef SIGBUS | |
33 | # define SIGBUS 10 | |
34 | #endif | |
35 | ||
f2de7dfd | 36 | |
c967f187 | 37 | /* "core" module install handler. |
cd0d873d | 38 | |
c967f187 DE |
39 | This is called via sim_module_install to install the "core" subsystem |
40 | into the simulator. */ | |
41 | ||
cd0d873d AC |
42 | static MODULE_INIT_FN sim_core_init; |
43 | static MODULE_UNINSTALL_FN sim_core_uninstall; | |
44 | ||
c967f187 DE |
45 | EXTERN_SIM_CORE\ |
46 | (SIM_RC) | |
47 | sim_core_install (SIM_DESC sd) | |
48 | { | |
50a2a691 | 49 | SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); |
a34abff8 AC |
50 | |
51 | /* establish the other handlers */ | |
c967f187 DE |
52 | sim_module_add_uninstall_fn (sd, sim_core_uninstall); |
53 | sim_module_add_init_fn (sd, sim_core_init); | |
a34abff8 AC |
54 | |
55 | /* establish any initial data structures - none */ | |
c967f187 DE |
56 | return SIM_RC_OK; |
57 | } | |
58 | ||
59 | ||
60 | /* Uninstall the "core" subsystem from the simulator. */ | |
61 | ||
cd0d873d | 62 | STATIC_SIM_CORE\ |
f2de7dfd | 63 | (void) |
c967f187 | 64 | sim_core_uninstall (SIM_DESC sd) |
f2de7dfd | 65 | { |
f90b720b | 66 | sim_core *core = STATE_CORE(sd); |
c967f187 | 67 | sim_core_maps map; |
a34abff8 | 68 | /* blow away any mappings */ |
f90b720b | 69 | for (map = 0; map < nr_sim_core_maps; map++) { |
f90b720b | 70 | sim_core_mapping *curr = core->common.map[map].first; |
f2de7dfd | 71 | while (curr != NULL) { |
c967f187 | 72 | sim_core_mapping *tbd = curr; |
f2de7dfd | 73 | curr = curr->next; |
fd89abc2 | 74 | if (tbd->free_buffer != NULL) { |
c967f187 | 75 | SIM_ASSERT(tbd->buffer != NULL); |
fd89abc2 | 76 | zfree(tbd->free_buffer); |
f2de7dfd AC |
77 | } |
78 | zfree(tbd); | |
79 | } | |
f90b720b AC |
80 | core->common.map[map].first = NULL; |
81 | } | |
a34abff8 AC |
82 | } |
83 | ||
84 | ||
85 | STATIC_SIM_CORE\ | |
86 | (SIM_RC) | |
87 | sim_core_init (SIM_DESC sd) | |
88 | { | |
89 | /* Nothing to do */ | |
c967f187 | 90 | return SIM_RC_OK; |
f2de7dfd AC |
91 | } |
92 | ||
93 | ||
94 | ||
50a2a691 AC |
95 | #ifndef SIM_CORE_SIGNAL |
96 | #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ | |
97 | sim_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR)) | |
98 | ||
cd0d873d AC |
99 | STATIC_SIM_CORE\ |
100 | (void) | |
50a2a691 AC |
101 | sim_core_signal (SIM_DESC sd, |
102 | sim_cpu *cpu, | |
103 | sim_cia cia, | |
104 | sim_core_maps map, | |
105 | int nr_bytes, | |
106 | address_word addr, | |
107 | transfer_type transfer, | |
108 | sim_core_signals sig) | |
109 | { | |
110 | const char *copy = (transfer == read_transfer ? "read" : "write"); | |
111 | switch (sig) | |
112 | { | |
113 | case sim_core_unmapped_signal: | |
fd89abc2 AC |
114 | sim_io_eprintf (sd, "core: %d byte %s to unmaped address 0x%lx\n", |
115 | nr_bytes, copy, (unsigned long) addr); | |
116 | sim_engine_halt (sd, cpu, NULL, cia, sim_signalled, SIGSEGV); | |
50a2a691 AC |
117 | break; |
118 | case sim_core_unaligned_signal: | |
fd89abc2 AC |
119 | sim_io_eprintf (sd, "core: %d byte misaligned %s to address 0x%lx", |
120 | nr_bytes, copy, (unsigned long) addr); | |
121 | sim_engine_halt (sd, cpu, NULL, cia, sim_signalled, SIGBUS); | |
50a2a691 AC |
122 | break; |
123 | default: | |
fd89abc2 AC |
124 | sim_engine_abort (sd, cpu, cia, |
125 | "sim_core_signal - internal error - bad switch"); | |
50a2a691 AC |
126 | } |
127 | } | |
50a2a691 AC |
128 | #endif |
129 | ||
cd0d873d | 130 | |
1fe05280 AC |
131 | STATIC_INLINE_SIM_CORE\ |
132 | (const char *) | |
133 | sim_core_map_to_str (sim_core_maps map) | |
134 | { | |
135 | switch (map) | |
136 | { | |
137 | case sim_core_read_map: return "read"; | |
138 | case sim_core_write_map: return "write"; | |
139 | case sim_core_execute_map: return "exec"; | |
140 | default: return "(invalid-map)"; | |
141 | } | |
142 | } | |
143 | ||
144 | ||
cd0d873d | 145 | STATIC_SIM_CORE\ |
c967f187 | 146 | (sim_core_mapping *) |
a34abff8 AC |
147 | new_sim_core_mapping (SIM_DESC sd, |
148 | attach_type attach, | |
149 | int space, | |
150 | address_word addr, | |
151 | address_word nr_bytes, | |
152 | unsigned modulo, | |
153 | device *device, | |
154 | void *buffer, | |
fd89abc2 | 155 | void *free_buffer) |
f2de7dfd | 156 | { |
c967f187 | 157 | sim_core_mapping *new_mapping = ZALLOC(sim_core_mapping); |
f2de7dfd AC |
158 | /* common */ |
159 | new_mapping->level = attach; | |
160 | new_mapping->space = space; | |
161 | new_mapping->base = addr; | |
162 | new_mapping->nr_bytes = nr_bytes; | |
163 | new_mapping->bound = addr + (nr_bytes - 1); | |
a34abff8 AC |
164 | if (modulo == 0) |
165 | new_mapping->mask = (unsigned) 0 - 1; | |
166 | else | |
167 | new_mapping->mask = modulo - 1; | |
168 | if (attach == attach_raw_memory) | |
169 | { | |
170 | new_mapping->buffer = buffer; | |
171 | new_mapping->free_buffer = free_buffer; | |
172 | } | |
173 | else if (attach >= attach_callback) | |
174 | { | |
175 | new_mapping->device = device; | |
176 | } | |
f2de7dfd | 177 | else { |
c967f187 | 178 | sim_io_error (sd, "new_sim_core_mapping - internal error - unknown attach type %d\n", |
a34abff8 | 179 | attach); |
f2de7dfd AC |
180 | } |
181 | return new_mapping; | |
182 | } | |
183 | ||
184 | ||
cd0d873d | 185 | STATIC_SIM_CORE\ |
f2de7dfd | 186 | (void) |
a34abff8 AC |
187 | sim_core_map_attach (SIM_DESC sd, |
188 | sim_core_map *access_map, | |
189 | attach_type attach, | |
190 | int space, | |
191 | address_word addr, | |
192 | address_word nr_bytes, | |
193 | unsigned modulo, | |
194 | device *client, /*callback/default*/ | |
195 | void *buffer, /*raw_memory*/ | |
fd89abc2 | 196 | void *free_buffer) /*raw_memory*/ |
f2de7dfd AC |
197 | { |
198 | /* find the insertion point for this additional mapping and then | |
199 | insert */ | |
c967f187 DE |
200 | sim_core_mapping *next_mapping; |
201 | sim_core_mapping **last_mapping; | |
f2de7dfd | 202 | |
a34abff8 | 203 | SIM_ASSERT ((attach >= attach_callback) |
fd89abc2 | 204 | <= (client != NULL && buffer == NULL && free_buffer == NULL)); |
a34abff8 AC |
205 | SIM_ASSERT ((attach == attach_raw_memory) |
206 | <= (client == NULL && buffer != NULL)); | |
f2de7dfd AC |
207 | |
208 | /* actually do occasionally get a zero size map */ | |
a34abff8 AC |
209 | if (nr_bytes == 0) |
210 | { | |
f2de7dfd | 211 | #if (WITH_DEVICES) |
a34abff8 | 212 | device_error(client, "called on sim_core_map_attach with size zero"); |
f2de7dfd | 213 | #else |
a34abff8 | 214 | sim_io_error (sd, "called on sim_core_map_attach with size zero"); |
f2de7dfd | 215 | #endif |
a34abff8 | 216 | } |
f2de7dfd AC |
217 | |
218 | /* find the insertion point (between last/next) */ | |
219 | next_mapping = access_map->first; | |
220 | last_mapping = &access_map->first; | |
221 | while(next_mapping != NULL | |
f90b720b AC |
222 | && (next_mapping->level < (int) attach |
223 | || (next_mapping->level == (int) attach | |
a34abff8 AC |
224 | && next_mapping->bound < addr))) |
225 | { | |
226 | /* provided levels are the same */ | |
227 | /* assert: next_mapping->base > all bases before next_mapping */ | |
228 | /* assert: next_mapping->bound >= all bounds before next_mapping */ | |
229 | last_mapping = &next_mapping->next; | |
230 | next_mapping = next_mapping->next; | |
231 | } | |
232 | ||
f2de7dfd | 233 | /* check insertion point correct */ |
f90b720b AC |
234 | SIM_ASSERT (next_mapping == NULL || next_mapping->level >= (int) attach); |
235 | if (next_mapping != NULL && next_mapping->level == (int) attach | |
80c651f0 AC |
236 | && next_mapping->base < (addr + (nr_bytes - 1))) |
237 | { | |
f2de7dfd | 238 | #if (WITH_DEVICES) |
80c651f0 AC |
239 | device_error (client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)", |
240 | space, | |
241 | (long) addr, | |
242 | (long) nr_bytes, | |
243 | (long) (addr + (nr_bytes - 1)), | |
244 | next_mapping->space, | |
245 | (long) next_mapping->base, | |
246 | (long) next_mapping->bound, | |
247 | (long) next_mapping->nr_bytes); | |
f2de7dfd | 248 | #else |
80c651f0 AC |
249 | sim_io_error (sd, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)", |
250 | space, | |
251 | (long) addr, | |
252 | (long) nr_bytes, | |
253 | (long) (addr + (nr_bytes - 1)), | |
254 | next_mapping->space, | |
255 | (long) next_mapping->base, | |
256 | (long) next_mapping->bound, | |
257 | (long) next_mapping->nr_bytes); | |
f2de7dfd AC |
258 | #endif |
259 | } | |
260 | ||
261 | /* create/insert the new mapping */ | |
c967f187 | 262 | *last_mapping = new_sim_core_mapping(sd, |
80c651f0 | 263 | attach, |
a34abff8 | 264 | space, addr, nr_bytes, modulo, |
80c651f0 | 265 | client, buffer, free_buffer); |
f2de7dfd AC |
266 | (*last_mapping)->next = next_mapping; |
267 | } | |
268 | ||
269 | ||
cd0d873d | 270 | EXTERN_SIM_CORE\ |
f2de7dfd | 271 | (void) |
a34abff8 AC |
272 | sim_core_attach (SIM_DESC sd, |
273 | sim_cpu *cpu, | |
274 | attach_type attach, | |
275 | access_type access, | |
276 | int space, | |
277 | address_word addr, | |
278 | address_word nr_bytes, | |
279 | unsigned modulo, | |
280 | device *client, | |
281 | void *optional_buffer) | |
f2de7dfd | 282 | { |
1fe05280 | 283 | sim_core *memory = STATE_CORE(sd); |
c967f187 | 284 | sim_core_maps map; |
f2de7dfd | 285 | void *buffer; |
fd89abc2 | 286 | void *free_buffer; |
7a418800 AC |
287 | |
288 | /* check for for attempt to use unimplemented per-processor core map */ | |
289 | if (cpu != NULL) | |
290 | sim_io_error (sd, "sim_core_map_attach - processor specific memory map not yet supported"); | |
291 | ||
f2de7dfd | 292 | if ((access & access_read_write_exec) == 0 |
a34abff8 AC |
293 | || (access & ~access_read_write_exec) != 0) |
294 | { | |
f2de7dfd | 295 | #if (WITH_DEVICES) |
a34abff8 | 296 | device_error(client, "invalid access for core attach"); |
f2de7dfd | 297 | #else |
a34abff8 | 298 | sim_io_error (sd, "invalid access for core attach"); |
f2de7dfd | 299 | #endif |
a34abff8 AC |
300 | } |
301 | ||
f2de7dfd | 302 | /* verify the attach type */ |
a34abff8 AC |
303 | if (attach == attach_raw_memory) |
304 | { | |
305 | if (WITH_MODULO_MEMORY && modulo != 0) | |
306 | { | |
307 | unsigned mask = modulo - 1; | |
308 | if (mask < 7) /* 8 is minimum modulo */ | |
309 | mask = 0; | |
310 | while (mask > 1) /* no zero bits */ | |
1bba340a AC |
311 | { |
312 | if ((mask & 1) == 0) | |
313 | mask = 0; | |
314 | else | |
315 | mask >>= 1; | |
316 | } | |
a34abff8 AC |
317 | if (mask == 0) |
318 | { | |
319 | #if (WITH_DEVICES) | |
320 | device_error (client, "sim_core_attach - internal error - modulo not power of two"); | |
321 | #else | |
322 | sim_io_error (sd, "sim_core_attach - internal error - modulo not power of two"); | |
323 | #endif | |
324 | } | |
325 | } | |
1bba340a | 326 | else if (!WITH_MODULO_MEMORY && modulo != 0) |
a34abff8 AC |
327 | { |
328 | #if (WITH_DEVICES) | |
329 | device_error (client, "sim_core_attach - internal error - modulo memory disabled"); | |
330 | #else | |
331 | sim_io_error (sd, "sim_core_attach - internal error - modulo memory disabled"); | |
332 | #endif | |
333 | } | |
334 | if (optional_buffer == NULL) | |
335 | { | |
fd89abc2 AC |
336 | int padding = (addr % sizeof (unsigned64)); |
337 | free_buffer = zalloc ((modulo == 0 ? nr_bytes : modulo) + padding); | |
338 | buffer = (char*) free_buffer + padding; | |
a34abff8 AC |
339 | } |
340 | else | |
341 | { | |
342 | buffer = optional_buffer; | |
fd89abc2 | 343 | free_buffer = NULL; |
a34abff8 | 344 | } |
f2de7dfd | 345 | } |
a34abff8 AC |
346 | else if (attach >= attach_callback) |
347 | { | |
348 | buffer = NULL; | |
fd89abc2 | 349 | free_buffer = NULL; |
f2de7dfd | 350 | } |
a34abff8 AC |
351 | else |
352 | { | |
f2de7dfd | 353 | #if (WITH_DEVICES) |
a34abff8 | 354 | device_error (client, "sim_core_attach - internal error - conflicting buffer and attach arguments"); |
f2de7dfd | 355 | #else |
a34abff8 | 356 | sim_io_error (sd, "sim_core_attach - internal error - conflicting buffer and attach arguments"); |
f2de7dfd | 357 | #endif |
a34abff8 | 358 | buffer = NULL; |
fd89abc2 | 359 | free_buffer = NULL; |
a34abff8 AC |
360 | } |
361 | ||
f2de7dfd AC |
362 | /* attach the region to all applicable access maps */ |
363 | for (map = 0; | |
c967f187 | 364 | map < nr_sim_core_maps; |
a34abff8 AC |
365 | map++) |
366 | { | |
367 | switch (map) | |
368 | { | |
369 | case sim_core_read_map: | |
370 | if (access & access_read) | |
371 | sim_core_map_attach (sd, &memory->common.map[map], | |
372 | attach, | |
373 | space, addr, nr_bytes, modulo, | |
fd89abc2 AC |
374 | client, buffer, free_buffer); |
375 | free_buffer = NULL; | |
a34abff8 AC |
376 | break; |
377 | case sim_core_write_map: | |
378 | if (access & access_write) | |
379 | sim_core_map_attach (sd, &memory->common.map[map], | |
380 | attach, | |
381 | space, addr, nr_bytes, modulo, | |
fd89abc2 AC |
382 | client, buffer, free_buffer); |
383 | free_buffer = NULL; | |
a34abff8 AC |
384 | break; |
385 | case sim_core_execute_map: | |
386 | if (access & access_exec) | |
387 | sim_core_map_attach (sd, &memory->common.map[map], | |
388 | attach, | |
389 | space, addr, nr_bytes, modulo, | |
fd89abc2 AC |
390 | client, buffer, free_buffer); |
391 | free_buffer = NULL; | |
a34abff8 AC |
392 | break; |
393 | case nr_sim_core_maps: | |
394 | sim_io_error (sd, "sim_core_attach - internal error - bad switch"); | |
395 | break; | |
396 | } | |
f2de7dfd | 397 | } |
a34abff8 | 398 | |
7a418800 AC |
399 | /* Just copy this map to each of the processor specific data structures. |
400 | FIXME - later this will be replaced by true processor specific | |
401 | maps. */ | |
f90b720b AC |
402 | { |
403 | int i; | |
404 | for (i = 0; i < MAX_NR_PROCESSORS; i++) | |
405 | { | |
406 | CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common; | |
407 | } | |
408 | } | |
f2de7dfd AC |
409 | } |
410 | ||
411 | ||
a34abff8 AC |
412 | /* Remove any memory reference related to this address */ |
413 | STATIC_INLINE_SIM_CORE\ | |
414 | (void) | |
415 | sim_core_map_detach (SIM_DESC sd, | |
416 | sim_core_map *access_map, | |
417 | attach_type attach, | |
418 | int space, | |
419 | address_word addr) | |
420 | { | |
421 | sim_core_mapping **entry; | |
422 | for (entry = &access_map->first; | |
423 | (*entry) != NULL; | |
424 | entry = &(*entry)->next) | |
425 | { | |
426 | if ((*entry)->base == addr | |
30efae3a | 427 | && (*entry)->level == (int) attach |
a34abff8 AC |
428 | && (*entry)->space == space) |
429 | { | |
430 | sim_core_mapping *dead = (*entry); | |
431 | (*entry) = dead->next; | |
fd89abc2 AC |
432 | if (dead->free_buffer != NULL) |
433 | zfree (dead->free_buffer); | |
a34abff8 AC |
434 | zfree (dead); |
435 | return; | |
436 | } | |
437 | } | |
438 | } | |
439 | ||
440 | EXTERN_SIM_CORE\ | |
441 | (void) | |
442 | sim_core_detach (SIM_DESC sd, | |
443 | sim_cpu *cpu, | |
444 | attach_type attach, | |
445 | int address_space, | |
446 | address_word addr) | |
447 | { | |
448 | sim_core *memory = STATE_CORE (sd); | |
449 | sim_core_maps map; | |
450 | for (map = 0; map < nr_sim_core_maps; map++) | |
451 | { | |
452 | sim_core_map_detach (sd, &memory->common.map[map], | |
453 | attach, address_space, addr); | |
454 | } | |
455 | /* Just copy this update to each of the processor specific data | |
456 | structures. FIXME - later this will be replaced by true | |
457 | processor specific maps. */ | |
458 | { | |
459 | int i; | |
460 | for (i = 0; i < MAX_NR_PROCESSORS; i++) | |
461 | { | |
462 | CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common; | |
463 | } | |
464 | } | |
465 | } | |
466 | ||
467 | ||
f2de7dfd | 468 | STATIC_INLINE_SIM_CORE\ |
c967f187 | 469 | (sim_core_mapping *) |
f90b720b | 470 | sim_core_find_mapping(sim_core_common *core, |
c967f187 | 471 | sim_core_maps map, |
cd0d873d | 472 | address_word addr, |
f2de7dfd | 473 | unsigned nr_bytes, |
50a2a691 | 474 | transfer_type transfer, |
7a418800 AC |
475 | int abort, /*either 0 or 1 - hint to inline/-O */ |
476 | sim_cpu *cpu, /* abort => cpu != NULL */ | |
1fe05280 | 477 | sim_cia cia) |
f2de7dfd | 478 | { |
7a418800 AC |
479 | sim_core_mapping *mapping = core->map[map].first; |
480 | ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */ | |
481 | ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */ | |
482 | ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */ | |
483 | while (mapping != NULL) | |
484 | { | |
485 | if (addr >= mapping->base | |
486 | && (addr + (nr_bytes - 1)) <= mapping->bound) | |
487 | return mapping; | |
488 | mapping = mapping->next; | |
489 | } | |
f2de7dfd | 490 | if (abort) |
7a418800 | 491 | { |
50a2a691 AC |
492 | SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, nr_bytes, addr, transfer, |
493 | sim_core_unmapped_signal); | |
7a418800 | 494 | } |
f2de7dfd AC |
495 | return NULL; |
496 | } | |
497 | ||
498 | ||
499 | STATIC_INLINE_SIM_CORE\ | |
500 | (void *) | |
f90b720b AC |
501 | sim_core_translate (sim_core_mapping *mapping, |
502 | address_word addr) | |
f2de7dfd | 503 | { |
a34abff8 AC |
504 | if (WITH_MODULO_MEMORY) |
505 | return (void *)((unsigned8 *) mapping->buffer | |
506 | + ((addr - mapping->base) & mapping->mask)); | |
507 | else | |
508 | return (void *)((unsigned8 *) mapping->buffer | |
509 | + addr - mapping->base); | |
f2de7dfd AC |
510 | } |
511 | ||
512 | ||
cd0d873d | 513 | EXTERN_SIM_CORE\ |
f2de7dfd | 514 | (unsigned) |
f90b720b AC |
515 | sim_core_read_buffer (SIM_DESC sd, |
516 | sim_cpu *cpu, | |
517 | sim_core_maps map, | |
518 | void *buffer, | |
519 | address_word addr, | |
520 | unsigned len) | |
f2de7dfd | 521 | { |
f90b720b | 522 | sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common); |
f2de7dfd AC |
523 | unsigned count = 0; |
524 | while (count < len) { | |
525 | unsigned_word raddr = addr + count; | |
c967f187 | 526 | sim_core_mapping *mapping = |
f90b720b | 527 | sim_core_find_mapping(core, map, |
50a2a691 AC |
528 | raddr, /*nr-bytes*/1, |
529 | read_transfer, | |
f90b720b | 530 | 0 /*dont-abort*/, NULL, NULL_CIA); |
f2de7dfd AC |
531 | if (mapping == NULL) |
532 | break; | |
533 | #if (WITH_DEVICES) | |
534 | if (mapping->device != NULL) { | |
535 | int nr_bytes = len - count; | |
536 | if (raddr + nr_bytes - 1> mapping->bound) | |
537 | nr_bytes = mapping->bound - raddr + 1; | |
538 | if (device_io_read_buffer(mapping->device, | |
539 | (unsigned_1*)buffer + count, | |
540 | mapping->space, | |
541 | raddr, | |
542 | nr_bytes) != nr_bytes) | |
543 | break; | |
544 | count += nr_bytes; | |
545 | } | |
546 | else | |
547 | #endif | |
548 | { | |
549 | ((unsigned_1*)buffer)[count] = | |
c967f187 | 550 | *(unsigned_1*)sim_core_translate(mapping, raddr); |
f2de7dfd AC |
551 | count += 1; |
552 | } | |
553 | } | |
554 | return count; | |
555 | } | |
556 | ||
557 | ||
cd0d873d | 558 | EXTERN_SIM_CORE\ |
f2de7dfd | 559 | (unsigned) |
f90b720b AC |
560 | sim_core_write_buffer (SIM_DESC sd, |
561 | sim_cpu *cpu, | |
562 | sim_core_maps map, | |
563 | const void *buffer, | |
564 | address_word addr, | |
565 | unsigned len) | |
f2de7dfd | 566 | { |
f90b720b | 567 | sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common); |
f2de7dfd AC |
568 | unsigned count = 0; |
569 | while (count < len) { | |
570 | unsigned_word raddr = addr + count; | |
f90b720b AC |
571 | sim_core_mapping *mapping = |
572 | sim_core_find_mapping(core, map, | |
573 | raddr, /*nr-bytes*/1, | |
574 | write_transfer, | |
575 | 0 /*dont-abort*/, NULL, NULL_CIA); | |
f2de7dfd AC |
576 | if (mapping == NULL) |
577 | break; | |
578 | #if (WITH_DEVICES) | |
579 | if (WITH_CALLBACK_MEMORY | |
580 | && mapping->device != NULL) { | |
581 | int nr_bytes = len - count; | |
582 | if (raddr + nr_bytes - 1 > mapping->bound) | |
583 | nr_bytes = mapping->bound - raddr + 1; | |
584 | if (device_io_write_buffer(mapping->device, | |
585 | (unsigned_1*)buffer + count, | |
586 | mapping->space, | |
587 | raddr, | |
588 | nr_bytes) != nr_bytes) | |
589 | break; | |
590 | count += nr_bytes; | |
591 | } | |
592 | else | |
593 | #endif | |
594 | { | |
c967f187 | 595 | *(unsigned_1*)sim_core_translate(mapping, raddr) = |
f2de7dfd AC |
596 | ((unsigned_1*)buffer)[count]; |
597 | count += 1; | |
598 | } | |
599 | } | |
600 | return count; | |
601 | } | |
602 | ||
603 | ||
cd0d873d AC |
604 | EXTERN_SIM_CORE\ |
605 | (void) | |
f90b720b AC |
606 | sim_core_set_xor (SIM_DESC sd, |
607 | sim_cpu *cpu, | |
cd0d873d AC |
608 | int is_xor) |
609 | { | |
f90b720b | 610 | /* set up the XOR map if required. */ |
cd0d873d AC |
611 | if (WITH_XOR_ENDIAN) { |
612 | { | |
f90b720b AC |
613 | sim_core *core = STATE_CORE (sd); |
614 | sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL); | |
615 | if (cpu_core != NULL) | |
cd0d873d | 616 | { |
f90b720b AC |
617 | int i = 1; |
618 | unsigned mask; | |
619 | if (is_xor) | |
620 | mask = WITH_XOR_ENDIAN - 1; | |
621 | else | |
622 | mask = 0; | |
623 | while (i - 1 < WITH_XOR_ENDIAN) | |
624 | { | |
625 | cpu_core->xor[i-1] = mask; | |
626 | mask = (mask << 1) & (WITH_XOR_ENDIAN - 1); | |
627 | i = (i << 1); | |
628 | } | |
cd0d873d | 629 | } |
f90b720b AC |
630 | else |
631 | { | |
632 | if (is_xor) | |
633 | core->byte_xor = WITH_XOR_ENDIAN - 1; | |
634 | else | |
635 | core->byte_xor = 0; | |
636 | } | |
cd0d873d AC |
637 | } |
638 | } | |
639 | else { | |
640 | if (is_xor) | |
f90b720b | 641 | sim_engine_abort (sd, cpu, NULL_CIA, |
cd0d873d AC |
642 | "Attempted to enable xor-endian mode when permenantly disabled."); |
643 | } | |
644 | } | |
645 | ||
f90b720b AC |
646 | STATIC_INLINE_SIM_CORE\ |
647 | (void) | |
648 | reverse_n (unsigned_1 *dest, | |
649 | const unsigned_1 *src, | |
650 | int nr_bytes) | |
651 | { | |
652 | int i; | |
653 | for (i = 0; i < nr_bytes; i++) | |
654 | { | |
655 | dest [nr_bytes - i - 1] = src [i]; | |
656 | } | |
657 | } | |
658 | ||
659 | ||
660 | EXTERN_SIM_CORE\ | |
661 | (unsigned) | |
662 | sim_core_xor_read_buffer (SIM_DESC sd, | |
663 | sim_cpu *cpu, | |
664 | sim_core_maps map, | |
665 | void *buffer, | |
666 | address_word addr, | |
667 | unsigned nr_bytes) | |
668 | { | |
669 | address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]); | |
670 | if (!WITH_XOR_ENDIAN || !byte_xor) | |
671 | return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes); | |
672 | else | |
673 | /* only break up transfers when xor-endian is both selected and enabled */ | |
674 | { | |
31dda65a | 675 | unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */ |
f90b720b AC |
676 | unsigned nr_transfered = 0; |
677 | address_word start = addr; | |
678 | unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1))); | |
679 | address_word stop; | |
680 | /* initial and intermediate transfers are broken when they cross | |
681 | an XOR endian boundary */ | |
682 | while (nr_transfered + nr_this_transfer < nr_bytes) | |
683 | /* initial/intermediate transfers */ | |
684 | { | |
685 | /* since xor-endian is enabled stop^xor defines the start | |
686 | address of the transfer */ | |
687 | stop = start + nr_this_transfer - 1; | |
688 | SIM_ASSERT (start <= stop); | |
689 | SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor)); | |
690 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
691 | != nr_this_transfer) | |
692 | return nr_transfered; | |
693 | reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer); | |
694 | nr_transfered += nr_this_transfer; | |
695 | nr_this_transfer = WITH_XOR_ENDIAN; | |
696 | start = stop + 1; | |
697 | } | |
698 | /* final transfer */ | |
699 | nr_this_transfer = nr_bytes - nr_transfered; | |
700 | stop = start + nr_this_transfer - 1; | |
701 | SIM_ASSERT (stop == (addr + nr_bytes - 1)); | |
702 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
703 | != nr_this_transfer) | |
704 | return nr_transfered; | |
705 | reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer); | |
706 | return nr_bytes; | |
707 | } | |
708 | } | |
709 | ||
710 | ||
711 | EXTERN_SIM_CORE\ | |
712 | (unsigned) | |
713 | sim_core_xor_write_buffer (SIM_DESC sd, | |
714 | sim_cpu *cpu, | |
715 | sim_core_maps map, | |
716 | const void *buffer, | |
717 | address_word addr, | |
718 | unsigned nr_bytes) | |
719 | { | |
720 | address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]); | |
721 | if (!WITH_XOR_ENDIAN || !byte_xor) | |
722 | return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes); | |
723 | else | |
724 | /* only break up transfers when xor-endian is both selected and enabled */ | |
725 | { | |
fd89abc2 | 726 | unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero sized array */ |
f90b720b AC |
727 | unsigned nr_transfered = 0; |
728 | address_word start = addr; | |
729 | unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1))); | |
730 | address_word stop; | |
731 | /* initial and intermediate transfers are broken when they cross | |
732 | an XOR endian boundary */ | |
733 | while (nr_transfered + nr_this_transfer < nr_bytes) | |
734 | /* initial/intermediate transfers */ | |
735 | { | |
736 | /* since xor-endian is enabled stop^xor defines the start | |
737 | address of the transfer */ | |
738 | stop = start + nr_this_transfer - 1; | |
739 | SIM_ASSERT (start <= stop); | |
740 | SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor)); | |
741 | reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer); | |
742 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
743 | != nr_this_transfer) | |
744 | return nr_transfered; | |
745 | nr_transfered += nr_this_transfer; | |
746 | nr_this_transfer = WITH_XOR_ENDIAN; | |
747 | start = stop + 1; | |
748 | } | |
749 | /* final transfer */ | |
750 | nr_this_transfer = nr_bytes - nr_transfered; | |
751 | stop = start + nr_this_transfer - 1; | |
752 | SIM_ASSERT (stop == (addr + nr_bytes - 1)); | |
753 | reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer); | |
754 | if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer) | |
755 | != nr_this_transfer) | |
756 | return nr_transfered; | |
757 | return nr_bytes; | |
758 | } | |
759 | } | |
cd0d873d AC |
760 | |
761 | ||
762 | ||
f45dd42b | 763 | /* define the read/write 1/2/4/8/16/word functions */ |
f2de7dfd AC |
764 | |
765 | #define N 1 | |
766 | #include "sim-n-core.h" | |
767 | #undef N | |
768 | ||
769 | #define N 2 | |
770 | #include "sim-n-core.h" | |
771 | #undef N | |
772 | ||
773 | #define N 4 | |
774 | #include "sim-n-core.h" | |
775 | #undef N | |
776 | ||
777 | #define N 8 | |
778 | #include "sim-n-core.h" | |
779 | #undef N | |
780 | ||
f45dd42b AC |
781 | #define N 16 |
782 | #include "sim-n-core.h" | |
783 | #undef N | |
784 | ||
f2de7dfd AC |
785 | #define N word |
786 | #include "sim-n-core.h" | |
787 | #undef N | |
788 | ||
789 | #endif |