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b85e4829 AC |
1 | /* The common simulator framework for GDB, the GNU Debugger. |
2 | ||
3 | Copyright 2002 Free Software Foundation, Inc. | |
4 | ||
5 | Contributed by Andrew Cagney and Red Hat. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 59 Temple Place - Suite 330, | |
22 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
23 | |
24 | ||
25 | #ifndef SIM_CORE_H | |
26 | #define SIM_CORE_H | |
27 | ||
28 | ||
29 | /* core signals (error conditions) | |
30 | Define SIM_CORE_SIGNAL to catch these signals - see sim-core.c for | |
31 | details. */ | |
32 | ||
33 | typedef enum { | |
34 | sim_core_unmapped_signal, | |
35 | sim_core_unaligned_signal, | |
36 | nr_sim_core_signals, | |
37 | } sim_core_signals; | |
38 | ||
39 | /* Type of SIM_CORE_SIGNAL handler. */ | |
40 | typedef void (SIM_CORE_SIGNAL_FN) | |
41 | (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, unsigned map, int nr_bytes, | |
42 | address_word addr, transfer_type transfer, sim_core_signals sig); | |
43 | ||
44 | extern SIM_CORE_SIGNAL_FN sim_core_signal; | |
45 | ||
46 | ||
47 | /* basic types */ | |
48 | ||
49 | typedef struct _sim_core_mapping sim_core_mapping; | |
50 | struct _sim_core_mapping { | |
51 | /* common */ | |
52 | int level; | |
53 | int space; | |
54 | unsigned_word base; | |
55 | unsigned_word bound; | |
56 | unsigned_word nr_bytes; | |
57 | unsigned mask; | |
58 | /* memory map */ | |
59 | void *free_buffer; | |
60 | void *buffer; | |
61 | /* callback map */ | |
62 | #if (WITH_HW) | |
63 | struct hw *device; | |
64 | #else | |
65 | device *device; | |
66 | #endif | |
67 | /* tracing */ | |
68 | int trace; | |
69 | /* growth */ | |
70 | sim_core_mapping *next; | |
71 | }; | |
72 | ||
73 | typedef struct _sim_core_map sim_core_map; | |
74 | struct _sim_core_map { | |
75 | sim_core_mapping *first; | |
76 | }; | |
77 | ||
78 | ||
79 | typedef struct _sim_core_common { | |
80 | sim_core_map map[nr_maps]; | |
81 | } sim_core_common; | |
82 | ||
83 | ||
84 | /* Main core structure */ | |
85 | ||
86 | typedef struct _sim_core sim_core; | |
87 | struct _sim_core { | |
88 | sim_core_common common; | |
89 | address_word byte_xor; /* apply xor universally */ | |
90 | }; | |
91 | ||
92 | ||
93 | /* Per CPU distributed component of the core. At present this is | |
94 | mostly a clone of the global core data structure. */ | |
95 | ||
96 | typedef struct _sim_cpu_core { | |
97 | sim_core_common common; | |
98 | address_word xor[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */ | |
99 | } sim_cpu_core; | |
100 | ||
101 | ||
102 | /* Install the "core" module. */ | |
103 | ||
104 | extern SIM_RC sim_core_install (SIM_DESC sd); | |
105 | ||
106 | ||
107 | ||
108 | /* Create a memory region within the core. | |
109 | ||
110 | CPU - when non NULL, specifes the single processor that the memory | |
111 | space is to be attached to. (INIMPLEMENTED). | |
112 | ||
113 | LEVEL - specifies the ordering of the memory region. Lower regions | |
114 | are searched first. Within a level, memory regions can not | |
115 | overlap. | |
116 | ||
117 | MAPMASK - Bitmask specifying the memory maps that the region is to | |
118 | be attached to. Typically the enums sim-basics.h:access_* are used. | |
119 | ||
120 | ADDRESS_SPACE - For device regions, a MAP:ADDRESS pair is | |
121 | translated into ADDRESS_SPACE:OFFSET before being passed to the | |
122 | client device. | |
123 | ||
124 | MODULO - when the simulator has been configured WITH_MODULO support | |
125 | and is greater than zero, specifies that accesses to the region | |
126 | [ADDR .. ADDR+NR_BYTES) should be mapped onto the sub region [ADDR | |
127 | .. ADDR+MODULO). The modulo value must be a power of two. | |
128 | ||
129 | DEVICE - When non NULL, indicates that this is a callback memory | |
130 | space and specified device's memory callback handler should be | |
131 | called. | |
132 | ||
133 | OPTIONAL_BUFFER - when non NULL, specifies the buffer to use for | |
134 | data read & written to the region. Normally a more efficient | |
135 | internal structure is used. It is assumed that buffer is allocated | |
136 | such that the byte alignmed of OPTIONAL_BUFFER matches ADDR vis | |
137 | (OPTIONAL_BUFFER % 8) == (ADDR % 8)). It is defined to be a sub-optimal | |
138 | hook that allows clients to do nasty things that the interface doesn't | |
139 | accomodate. */ | |
140 | ||
141 | extern void sim_core_attach | |
142 | (SIM_DESC sd, | |
143 | sim_cpu *cpu, | |
144 | int level, | |
145 | unsigned mapmask, | |
146 | int address_space, | |
147 | address_word addr, | |
148 | address_word nr_bytes, | |
149 | unsigned modulo, | |
150 | #if (WITH_HW) | |
151 | struct hw *client, | |
152 | #else | |
153 | device *client, | |
154 | #endif | |
155 | void *optional_buffer); | |
156 | ||
157 | ||
158 | /* Delete a memory section within the core. | |
159 | ||
160 | */ | |
161 | ||
162 | extern void sim_core_detach | |
163 | (SIM_DESC sd, | |
164 | sim_cpu *cpu, | |
165 | int level, | |
166 | int address_space, | |
167 | address_word addr); | |
168 | ||
169 | ||
170 | /* Variable sized read/write | |
171 | ||
172 | Transfer a variable sized block of raw data between the host and | |
6439295f | 173 | target. Should any problems occur, the number of bytes |
c906108c SS |
174 | successfully transfered is returned. |
175 | ||
176 | No host/target byte endian conversion is performed. No xor-endian | |
177 | conversion is performed. | |
178 | ||
179 | If CPU argument, when non NULL, specifies the processor specific | |
180 | address map that is to be used in the transfer. */ | |
181 | ||
182 | ||
183 | extern unsigned sim_core_read_buffer | |
184 | (SIM_DESC sd, | |
185 | sim_cpu *cpu, | |
186 | unsigned map, | |
187 | void *buffer, | |
188 | address_word addr, | |
189 | unsigned nr_bytes); | |
190 | ||
191 | extern unsigned sim_core_write_buffer | |
192 | (SIM_DESC sd, | |
193 | sim_cpu *cpu, | |
194 | unsigned map, | |
195 | const void *buffer, | |
196 | address_word addr, | |
197 | unsigned nr_bytes); | |
198 | ||
199 | ||
200 | ||
201 | /* Configure the core's XOR endian transfer mode. Only applicable | |
202 | when WITH_XOR_ENDIAN is enabled. | |
203 | ||
204 | Targets suporting XOR endian, shall notify the core of any changes | |
205 | in state via this call. | |
206 | ||
207 | The CPU argument, when non NULL, specifes the single processor that | |
208 | the xor-endian configuration is to be applied to. */ | |
209 | ||
210 | extern void sim_core_set_xor | |
211 | (SIM_DESC sd, | |
212 | sim_cpu *cpu, | |
213 | int is_xor); | |
214 | ||
215 | ||
216 | /* XOR version of variable sized read/write. | |
217 | ||
218 | Transfer a variable sized block of raw data between the host and | |
6439295f | 219 | target. Should any problems occur, the number of bytes |
c906108c SS |
220 | successfully transfered is returned. |
221 | ||
222 | No host/target byte endian conversion is performed. If applicable | |
223 | (WITH_XOR_ENDIAN and xor-endian set), xor-endian conversion *is* | |
224 | performed. | |
225 | ||
226 | If CPU argument, when non NULL, specifies the processor specific | |
227 | address map that is to be used in the transfer. */ | |
228 | ||
229 | extern unsigned sim_core_xor_read_buffer | |
230 | (SIM_DESC sd, | |
231 | sim_cpu *cpu, | |
232 | unsigned map, | |
233 | void *buffer, | |
234 | address_word addr, | |
235 | unsigned nr_bytes); | |
236 | ||
237 | extern unsigned sim_core_xor_write_buffer | |
238 | (SIM_DESC sd, | |
239 | sim_cpu *cpu, | |
240 | unsigned map, | |
241 | const void *buffer, | |
242 | address_word addr, | |
243 | unsigned nr_bytes); | |
244 | ||
245 | ||
246 | ||
247 | /* Fixed sized, processor oriented, read/write. | |
248 | ||
249 | Transfer a fixed amout of memory between the host and target. The | |
250 | data transfered is translated from/to host to/from target byte | |
251 | order (including xor endian). Should the transfer fail, the | |
252 | operation shall abort (no return). | |
253 | ||
254 | ALIGNED assumes yhat the specified ADDRESS is correctly alligned | |
255 | for an N byte transfer (no alignment checks are made). Passing an | |
256 | incorrectly aligned ADDRESS is erroneous. | |
257 | ||
258 | UNALIGNED checks/modifies the ADDRESS according to the requirements | |
259 | of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being | |
260 | taken should the check fail. | |
261 | ||
262 | MISSALIGNED transfers the data regardless. | |
263 | ||
264 | Misaligned xor-endian accesses are broken into a sequence of | |
265 | transfers each <= WITH_XOR_ENDIAN bytes */ | |
266 | ||
267 | ||
268 | #define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N,M) \ | |
269 | INLINE_SIM_CORE\ | |
270 | (void) sim_core_write_##ALIGNMENT##_##N \ | |
271 | (sim_cpu *cpu, \ | |
272 | sim_cia cia, \ | |
273 | unsigned map, \ | |
274 | address_word addr, \ | |
275 | unsigned_##M val); | |
276 | ||
277 | DECLARE_SIM_CORE_WRITE_N(aligned,1,1) | |
278 | DECLARE_SIM_CORE_WRITE_N(aligned,2,2) | |
279 | DECLARE_SIM_CORE_WRITE_N(aligned,4,4) | |
280 | DECLARE_SIM_CORE_WRITE_N(aligned,8,8) | |
281 | DECLARE_SIM_CORE_WRITE_N(aligned,16,16) | |
282 | ||
283 | #define sim_core_write_unaligned_1 sim_core_write_aligned_1 | |
284 | DECLARE_SIM_CORE_WRITE_N(unaligned,2,2) | |
285 | DECLARE_SIM_CORE_WRITE_N(unaligned,4,4) | |
286 | DECLARE_SIM_CORE_WRITE_N(unaligned,8,8) | |
287 | DECLARE_SIM_CORE_WRITE_N(unaligned,16,16) | |
288 | ||
289 | DECLARE_SIM_CORE_WRITE_N(misaligned,3,4) | |
290 | DECLARE_SIM_CORE_WRITE_N(misaligned,5,8) | |
291 | DECLARE_SIM_CORE_WRITE_N(misaligned,6,8) | |
292 | DECLARE_SIM_CORE_WRITE_N(misaligned,7,8) | |
293 | ||
294 | #define sim_core_write_1 sim_core_write_aligned_1 | |
295 | #define sim_core_write_2 sim_core_write_aligned_2 | |
296 | #define sim_core_write_4 sim_core_write_aligned_4 | |
297 | #define sim_core_write_8 sim_core_write_aligned_8 | |
298 | #define sim_core_write_16 sim_core_write_aligned_16 | |
299 | ||
300 | #define sim_core_write_unaligned_word XCONCAT2(sim_core_write_unaligned_,WITH_TARGET_WORD_BITSIZE) | |
301 | #define sim_core_write_aligned_word XCONCAT2(sim_core_write_aligned_,WITH_TARGET_WORD_BITSIZE) | |
302 | #define sim_core_write_word XCONCAT2(sim_core_write_,WITH_TARGET_WORD_BITSIZE) | |
303 | ||
304 | #undef DECLARE_SIM_CORE_WRITE_N | |
305 | ||
306 | ||
307 | #define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N,M) \ | |
308 | INLINE_SIM_CORE\ | |
309 | (unsigned_##M) sim_core_read_##ALIGNMENT##_##N \ | |
310 | (sim_cpu *cpu, \ | |
311 | sim_cia cia, \ | |
312 | unsigned map, \ | |
313 | address_word addr); | |
314 | ||
315 | DECLARE_SIM_CORE_READ_N(aligned,1,1) | |
316 | DECLARE_SIM_CORE_READ_N(aligned,2,2) | |
317 | DECLARE_SIM_CORE_READ_N(aligned,4,4) | |
318 | DECLARE_SIM_CORE_READ_N(aligned,8,8) | |
319 | DECLARE_SIM_CORE_READ_N(aligned,16,16) | |
320 | ||
321 | #define sim_core_read_unaligned_1 sim_core_read_aligned_1 | |
322 | DECLARE_SIM_CORE_READ_N(unaligned,2,2) | |
323 | DECLARE_SIM_CORE_READ_N(unaligned,4,4) | |
324 | DECLARE_SIM_CORE_READ_N(unaligned,8,8) | |
325 | DECLARE_SIM_CORE_READ_N(unaligned,16,16) | |
326 | ||
327 | DECLARE_SIM_CORE_READ_N(misaligned,3,4) | |
328 | DECLARE_SIM_CORE_READ_N(misaligned,5,8) | |
329 | DECLARE_SIM_CORE_READ_N(misaligned,6,8) | |
330 | DECLARE_SIM_CORE_READ_N(misaligned,7,8) | |
331 | ||
332 | ||
333 | #define sim_core_read_1 sim_core_read_aligned_1 | |
334 | #define sim_core_read_2 sim_core_read_aligned_2 | |
335 | #define sim_core_read_4 sim_core_read_aligned_4 | |
336 | #define sim_core_read_8 sim_core_read_aligned_8 | |
337 | #define sim_core_read_16 sim_core_read_aligned_16 | |
338 | ||
339 | #define sim_core_read_unaligned_word XCONCAT2(sim_core_read_unaligned_,WITH_TARGET_WORD_BITSIZE) | |
340 | #define sim_core_read_aligned_word XCONCAT2(sim_core_read_aligned_,WITH_TARGET_WORD_BITSIZE) | |
341 | #define sim_core_read_word XCONCAT2(sim_core_read_,WITH_TARGET_WORD_BITSIZE) | |
342 | ||
343 | #undef DECLARE_SIM_CORE_READ_N | |
344 | ||
345 | ||
7a292a7a SS |
346 | #if (WITH_DEVICES) |
347 | /* TODO: create sim/common/device.h */ | |
348 | /* These are defined with each particular cpu. */ | |
349 | void device_error (device *me, char* message, ...); | |
350 | int device_io_read_buffer(device *me, void *dest, int space, address_word addr, unsigned nr_bytes, SIM_DESC sd, sim_cpu *processor, sim_cia cia); | |
351 | int device_io_write_buffer(device *me, const void *source, int space, address_word addr, unsigned nr_bytes, SIM_DESC sd, sim_cpu *processor, sim_cia cia); | |
352 | #endif | |
353 | ||
354 | ||
c906108c | 355 | #endif |