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c967f187 DE |
1 | /* This file is part of the program psim. |
2 | ||
3 | Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
17 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | ||
19 | */ | |
20 | ||
21 | ||
22 | #ifndef _SIM_CORE_H_ | |
23 | #define _SIM_CORE_H_ | |
24 | ||
25 | ||
cd0d873d AC |
26 | /* core signals (error conditions) */ |
27 | ||
28 | typedef enum { | |
29 | sim_core_unmapped_signal, | |
30 | sim_core_unaligned_signal, | |
31 | nr_sim_core_signals, | |
32 | } sim_core_signals; | |
33 | ||
a34abff8 AC |
34 | /* define SIM_CORE_SIGNAL to catch these signals - see sim-core.c for |
35 | details */ | |
cd0d873d AC |
36 | |
37 | ||
38 | ||
c967f187 DE |
39 | /* basic types */ |
40 | ||
41 | typedef struct _sim_core_mapping sim_core_mapping; | |
42 | struct _sim_core_mapping { | |
43 | /* common */ | |
44 | int level; | |
45 | int space; | |
46 | unsigned_word base; | |
47 | unsigned_word bound; | |
a34abff8 AC |
48 | unsigned_word nr_bytes; |
49 | unsigned mask; | |
c967f187 | 50 | /* memory map */ |
fd89abc2 | 51 | void *free_buffer; |
c967f187 DE |
52 | void *buffer; |
53 | /* callback map */ | |
54 | device *device; | |
7a418800 AC |
55 | /* tracing */ |
56 | int trace; | |
c967f187 DE |
57 | /* growth */ |
58 | sim_core_mapping *next; | |
59 | }; | |
60 | ||
61 | typedef struct _sim_core_map sim_core_map; | |
62 | struct _sim_core_map { | |
63 | sim_core_mapping *first; | |
64 | }; | |
65 | ||
66 | typedef enum { | |
67 | sim_core_read_map, | |
68 | sim_core_write_map, | |
69 | sim_core_execute_map, | |
70 | nr_sim_core_maps, | |
71 | } sim_core_maps; | |
72 | ||
7a418800 | 73 | |
a34abff8 AC |
74 | typedef struct _sim_core_common { |
75 | sim_core_map map[nr_sim_core_maps]; | |
76 | } sim_core_common; | |
77 | ||
78 | ||
7a418800 AC |
79 | /* Main core structure */ |
80 | ||
c967f187 DE |
81 | typedef struct _sim_core sim_core; |
82 | struct _sim_core { | |
a34abff8 AC |
83 | sim_core_common common; |
84 | address_word byte_xor; /* apply xor universally */ | |
c967f187 DE |
85 | }; |
86 | ||
87 | ||
cd0d873d AC |
88 | /* Per CPU distributed component of the core. At present this is |
89 | mostly a clone of the global core data structure. */ | |
7a418800 | 90 | |
cd0d873d | 91 | typedef struct _sim_cpu_core { |
a34abff8 | 92 | sim_core_common common; |
fd89abc2 | 93 | address_word xor[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */ |
cd0d873d | 94 | } sim_cpu_core; |
7a418800 AC |
95 | |
96 | ||
c967f187 DE |
97 | /* Install the "core" module. */ |
98 | ||
99 | EXTERN_SIM_CORE\ | |
100 | (SIM_RC) sim_core_install (SIM_DESC sd); | |
101 | ||
102 | ||
c967f187 | 103 | |
7a418800 AC |
104 | /* Create a memory space within the core. |
105 | ||
fcc86d82 AC |
106 | CPU, when non NULL, specifes the single processor that the memory |
107 | space is to be attached to. (UNIMPLEMENTED). | |
a34abff8 | 108 | |
fcc86d82 AC |
109 | LEVEL specifies the ordering of the memory region. Lower regions |
110 | are searched first. Within a level, memory regions can not | |
111 | overlap. | |
112 | ||
113 | DEVICE, when non NULL, specifies a callback memory space. | |
114 | (UNIMPLEMENTED, see the ppc simulator for an example). | |
115 | ||
116 | MODULO, when the simulator has been configured WITH_MODULO support | |
117 | and is greater than zero, specifies that accesses to the region | |
118 | [ADDR .. ADDR+NR_BYTES) should be mapped onto the sub region [ADDR | |
119 | .. ADDR+MODULO). The modulo value must be a power of two. | |
120 | ||
121 | OPTIONAL_BUFFER, when non NULL, specifies the buffer to use for | |
122 | data read & written to the region. Normally a more efficient | |
123 | internal structure is used. It is assumed that buffer is allocated | |
124 | such that the byte alignmed of OPTIONAL_BUFFER matches ADDR vis | |
2307e0ee DE |
125 | (OPTIONAL_BUFFER % 8) == (ADDR % 8)). It is defined to be a sub-optimal |
126 | hook that allows clients to do nasty things that the interface doesn't | |
127 | accomodate. ??? That seems unnecessarily restrictive. */ | |
c967f187 | 128 | |
cd0d873d | 129 | EXTERN_SIM_CORE\ |
c967f187 DE |
130 | (void) sim_core_attach |
131 | (SIM_DESC sd, | |
7a418800 | 132 | sim_cpu *cpu, |
fcc86d82 | 133 | int level, |
c967f187 DE |
134 | access_type access, |
135 | int address_space, | |
cd0d873d | 136 | address_word addr, |
a34abff8 | 137 | address_word nr_bytes, |
fcc86d82 | 138 | unsigned modulo, |
c967f187 DE |
139 | device *client, |
140 | void *optional_buffer); | |
141 | ||
fcc86d82 | 142 | |
751197f2 DE |
143 | /* Utility to return the name of a map. */ |
144 | ||
145 | EXTERN_SIM_CORE\ | |
146 | (const char *) sim_core_map_to_str | |
147 | (sim_core_maps); | |
148 | ||
149 | ||
a34abff8 AC |
150 | /* Delete a memory space within the core. |
151 | ||
152 | */ | |
153 | ||
154 | EXTERN_SIM_CORE\ | |
155 | (void) sim_core_detach | |
156 | (SIM_DESC sd, | |
157 | sim_cpu *cpu, | |
fcc86d82 | 158 | int level, |
a34abff8 AC |
159 | int address_space, |
160 | address_word addr); | |
c967f187 DE |
161 | |
162 | ||
163 | /* Variable sized read/write | |
164 | ||
7a418800 AC |
165 | Transfer a variable sized block of raw data between the host and |
166 | target. Should any problems occure, the number of bytes | |
a34abff8 AC |
167 | successfully transfered is returned. |
168 | ||
169 | No host/target byte endian conversion is performed. No xor-endian | |
170 | conversion is performed. | |
171 | ||
172 | If CPU argument, when non NULL, specifies the processor specific | |
173 | address map that is to be used in the transfer. */ | |
174 | ||
c967f187 | 175 | |
cd0d873d | 176 | EXTERN_SIM_CORE\ |
c967f187 DE |
177 | (unsigned) sim_core_read_buffer |
178 | (SIM_DESC sd, | |
a34abff8 | 179 | sim_cpu *cpu, |
c967f187 DE |
180 | sim_core_maps map, |
181 | void *buffer, | |
cd0d873d | 182 | address_word addr, |
c967f187 DE |
183 | unsigned nr_bytes); |
184 | ||
cd0d873d | 185 | EXTERN_SIM_CORE\ |
c967f187 DE |
186 | (unsigned) sim_core_write_buffer |
187 | (SIM_DESC sd, | |
a34abff8 AC |
188 | sim_cpu *cpu, |
189 | sim_core_maps map, | |
190 | const void *buffer, | |
191 | address_word addr, | |
192 | unsigned nr_bytes); | |
193 | ||
194 | ||
195 | ||
196 | /* Configure the core's XOR endian transfer mode. Only applicable | |
197 | when WITH_XOR_ENDIAN is enabled. | |
198 | ||
199 | Targets suporting XOR endian, shall notify the core of any changes | |
200 | in state via this call. | |
201 | ||
202 | The CPU argument, when non NULL, specifes the single processor that | |
203 | the xor-endian configuration is to be applied to. */ | |
204 | ||
205 | EXTERN_SIM_CORE\ | |
206 | (void) sim_core_set_xor\ | |
207 | (SIM_DESC sd, | |
208 | sim_cpu *cpu, | |
209 | int is_xor); | |
210 | ||
211 | ||
212 | /* XOR version of variable sized read/write. | |
213 | ||
214 | Transfer a variable sized block of raw data between the host and | |
215 | target. Should any problems occure, the number of bytes | |
216 | successfully transfered is returned. | |
217 | ||
218 | No host/target byte endian conversion is performed. If applicable | |
219 | (WITH_XOR_ENDIAN and xor-endian set), xor-endian conversion *is* | |
220 | performed. | |
221 | ||
222 | If CPU argument, when non NULL, specifies the processor specific | |
223 | address map that is to be used in the transfer. */ | |
224 | ||
225 | EXTERN_SIM_CORE\ | |
226 | (unsigned) sim_core_xor_read_buffer | |
227 | (SIM_DESC sd, | |
228 | sim_cpu *cpu, | |
229 | sim_core_maps map, | |
230 | void *buffer, | |
231 | address_word addr, | |
232 | unsigned nr_bytes); | |
233 | ||
234 | EXTERN_SIM_CORE\ | |
235 | (unsigned) sim_core_xor_write_buffer | |
236 | (SIM_DESC sd, | |
237 | sim_cpu *cpu, | |
c967f187 DE |
238 | sim_core_maps map, |
239 | const void *buffer, | |
cd0d873d | 240 | address_word addr, |
c967f187 DE |
241 | unsigned nr_bytes); |
242 | ||
243 | ||
a34abff8 | 244 | |
7a418800 | 245 | /* Fixed sized, processor oriented, read/write. |
c967f187 DE |
246 | |
247 | Transfer a fixed amout of memory between the host and target. The | |
7a418800 | 248 | data transfered is translated from/to host to/from target byte |
a34abff8 AC |
249 | order (including xor endian). Should the transfer fail, the |
250 | operation shall abort (no return). | |
251 | ||
751197f2 DE |
252 | ALIGNED assumes yhat the specified ADDRESS is correctly alligned |
253 | for an N byte transfer (no alignment checks are made). Passing an | |
254 | incorrectly aligned ADDRESS is erroneous. | |
a34abff8 | 255 | |
751197f2 DE |
256 | UNALIGNED checks/modifies the ADDRESS according to the requirements |
257 | of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being | |
258 | taken should the check fail. | |
259 | ||
260 | MISSALIGNED transfers the data regardless. | |
a34abff8 AC |
261 | |
262 | Misaligned xor-endian accesses are broken into a sequence of | |
263 | transfers each <= WITH_XOR_ENDIAN bytes */ | |
264 | ||
7a418800 | 265 | |
751197f2 | 266 | #define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N,M) \ |
c967f187 | 267 | INLINE_SIM_CORE\ |
7a418800 AC |
268 | (void) sim_core_write_##ALIGNMENT##_##N \ |
269 | (sim_cpu *cpu, \ | |
270 | sim_cia cia, \ | |
c967f187 | 271 | sim_core_maps map, \ |
cd0d873d | 272 | address_word addr, \ |
751197f2 | 273 | unsigned_##M val); |
c967f187 | 274 | |
751197f2 DE |
275 | DECLARE_SIM_CORE_WRITE_N(aligned,1,1) |
276 | DECLARE_SIM_CORE_WRITE_N(aligned,2,2) | |
277 | DECLARE_SIM_CORE_WRITE_N(aligned,4,4) | |
278 | DECLARE_SIM_CORE_WRITE_N(aligned,8,8) | |
279 | DECLARE_SIM_CORE_WRITE_N(aligned,16,16) | |
7a418800 | 280 | |
751197f2 DE |
281 | #define sim_core_write_unaligned_1 sim_core_write_aligned_1 |
282 | DECLARE_SIM_CORE_WRITE_N(unaligned,2,2) | |
283 | DECLARE_SIM_CORE_WRITE_N(unaligned,4,4) | |
284 | DECLARE_SIM_CORE_WRITE_N(unaligned,8,8) | |
285 | DECLARE_SIM_CORE_WRITE_N(unaligned,16,16) | |
a86809d3 | 286 | |
751197f2 DE |
287 | DECLARE_SIM_CORE_WRITE_N(misaligned,3,4) |
288 | DECLARE_SIM_CORE_WRITE_N(misaligned,5,8) | |
289 | DECLARE_SIM_CORE_WRITE_N(misaligned,6,8) | |
290 | DECLARE_SIM_CORE_WRITE_N(misaligned,7,8) | |
7a418800 AC |
291 | |
292 | #define sim_core_write_1 sim_core_write_aligned_1 | |
293 | #define sim_core_write_2 sim_core_write_aligned_2 | |
294 | #define sim_core_write_4 sim_core_write_aligned_4 | |
d048b52d | 295 | #define sim_core_write_8 sim_core_write_aligned_8 |
f45dd42b | 296 | #define sim_core_write_16 sim_core_write_aligned_16 |
c967f187 | 297 | |
a86809d3 AC |
298 | #define sim_core_write_unaligned_word XCONCAT2(sim_core_write_unaligned_,WITH_TARGET_WORD_BITSIZE) |
299 | #define sim_core_write_aligned_word XCONCAT2(sim_core_write_aligned_,WITH_TARGET_WORD_BITSIZE) | |
300 | #define sim_core_write_word XCONCAT2(sim_core_write_,WITH_TARGET_WORD_BITSIZE) | |
301 | ||
c967f187 DE |
302 | #undef DECLARE_SIM_CORE_WRITE_N |
303 | ||
304 | ||
751197f2 | 305 | #define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N,M) \ |
c967f187 | 306 | INLINE_SIM_CORE\ |
751197f2 | 307 | (unsigned_##M) sim_core_read_##ALIGNMENT##_##N \ |
7a418800 AC |
308 | (sim_cpu *cpu, \ |
309 | sim_cia cia, \ | |
c967f187 | 310 | sim_core_maps map, \ |
cd0d873d | 311 | address_word addr); |
c967f187 | 312 | |
751197f2 DE |
313 | DECLARE_SIM_CORE_READ_N(aligned,1,1) |
314 | DECLARE_SIM_CORE_READ_N(aligned,2,2) | |
315 | DECLARE_SIM_CORE_READ_N(aligned,4,4) | |
316 | DECLARE_SIM_CORE_READ_N(aligned,8,8) | |
317 | DECLARE_SIM_CORE_READ_N(aligned,16,16) | |
318 | ||
319 | #define sim_core_read_unaligned_1 sim_core_read_aligned_1 | |
320 | DECLARE_SIM_CORE_READ_N(unaligned,2,2) | |
321 | DECLARE_SIM_CORE_READ_N(unaligned,4,4) | |
322 | DECLARE_SIM_CORE_READ_N(unaligned,8,8) | |
323 | DECLARE_SIM_CORE_READ_N(unaligned,16,16) | |
324 | ||
325 | DECLARE_SIM_CORE_READ_N(misaligned,3,4) | |
326 | DECLARE_SIM_CORE_READ_N(misaligned,5,8) | |
327 | DECLARE_SIM_CORE_READ_N(misaligned,6,8) | |
328 | DECLARE_SIM_CORE_READ_N(misaligned,7,8) | |
329 | ||
7a418800 AC |
330 | |
331 | #define sim_core_read_1 sim_core_read_aligned_1 | |
332 | #define sim_core_read_2 sim_core_read_aligned_2 | |
333 | #define sim_core_read_4 sim_core_read_aligned_4 | |
334 | #define sim_core_read_8 sim_core_read_aligned_8 | |
f45dd42b | 335 | #define sim_core_read_16 sim_core_read_aligned_16 |
c967f187 | 336 | |
a86809d3 AC |
337 | #define sim_core_read_unaligned_word XCONCAT2(sim_core_read_unaligned_,WITH_TARGET_WORD_BITSIZE) |
338 | #define sim_core_read_aligned_word XCONCAT2(sim_core_read_aligned_,WITH_TARGET_WORD_BITSIZE) | |
339 | #define sim_core_read_word XCONCAT2(sim_core_read_,WITH_TARGET_WORD_BITSIZE) | |
340 | ||
c967f187 DE |
341 | #undef DECLARE_SIM_CORE_READ_N |
342 | ||
343 | #endif |