Commit | Line | Data |
---|---|---|
c906108c SS |
1 | /* This file is part of the program psim. |
2 | ||
3 | Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
17 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | ||
19 | */ | |
20 | ||
21 | ||
22 | #ifndef SIM_CORE_H | |
23 | #define SIM_CORE_H | |
24 | ||
25 | ||
26 | /* core signals (error conditions) | |
27 | Define SIM_CORE_SIGNAL to catch these signals - see sim-core.c for | |
28 | details. */ | |
29 | ||
30 | typedef enum { | |
31 | sim_core_unmapped_signal, | |
32 | sim_core_unaligned_signal, | |
33 | nr_sim_core_signals, | |
34 | } sim_core_signals; | |
35 | ||
36 | /* Type of SIM_CORE_SIGNAL handler. */ | |
37 | typedef void (SIM_CORE_SIGNAL_FN) | |
38 | (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, unsigned map, int nr_bytes, | |
39 | address_word addr, transfer_type transfer, sim_core_signals sig); | |
40 | ||
41 | extern SIM_CORE_SIGNAL_FN sim_core_signal; | |
42 | ||
43 | ||
44 | /* basic types */ | |
45 | ||
46 | typedef struct _sim_core_mapping sim_core_mapping; | |
47 | struct _sim_core_mapping { | |
48 | /* common */ | |
49 | int level; | |
50 | int space; | |
51 | unsigned_word base; | |
52 | unsigned_word bound; | |
53 | unsigned_word nr_bytes; | |
54 | unsigned mask; | |
55 | /* memory map */ | |
56 | void *free_buffer; | |
57 | void *buffer; | |
58 | /* callback map */ | |
59 | #if (WITH_HW) | |
60 | struct hw *device; | |
61 | #else | |
62 | device *device; | |
63 | #endif | |
64 | /* tracing */ | |
65 | int trace; | |
66 | /* growth */ | |
67 | sim_core_mapping *next; | |
68 | }; | |
69 | ||
70 | typedef struct _sim_core_map sim_core_map; | |
71 | struct _sim_core_map { | |
72 | sim_core_mapping *first; | |
73 | }; | |
74 | ||
75 | ||
76 | typedef struct _sim_core_common { | |
77 | sim_core_map map[nr_maps]; | |
78 | } sim_core_common; | |
79 | ||
80 | ||
81 | /* Main core structure */ | |
82 | ||
83 | typedef struct _sim_core sim_core; | |
84 | struct _sim_core { | |
85 | sim_core_common common; | |
86 | address_word byte_xor; /* apply xor universally */ | |
87 | }; | |
88 | ||
89 | ||
90 | /* Per CPU distributed component of the core. At present this is | |
91 | mostly a clone of the global core data structure. */ | |
92 | ||
93 | typedef struct _sim_cpu_core { | |
94 | sim_core_common common; | |
95 | address_word xor[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */ | |
96 | } sim_cpu_core; | |
97 | ||
98 | ||
99 | /* Install the "core" module. */ | |
100 | ||
101 | extern SIM_RC sim_core_install (SIM_DESC sd); | |
102 | ||
103 | ||
104 | ||
105 | /* Create a memory region within the core. | |
106 | ||
107 | CPU - when non NULL, specifes the single processor that the memory | |
108 | space is to be attached to. (INIMPLEMENTED). | |
109 | ||
110 | LEVEL - specifies the ordering of the memory region. Lower regions | |
111 | are searched first. Within a level, memory regions can not | |
112 | overlap. | |
113 | ||
114 | MAPMASK - Bitmask specifying the memory maps that the region is to | |
115 | be attached to. Typically the enums sim-basics.h:access_* are used. | |
116 | ||
117 | ADDRESS_SPACE - For device regions, a MAP:ADDRESS pair is | |
118 | translated into ADDRESS_SPACE:OFFSET before being passed to the | |
119 | client device. | |
120 | ||
121 | MODULO - when the simulator has been configured WITH_MODULO support | |
122 | and is greater than zero, specifies that accesses to the region | |
123 | [ADDR .. ADDR+NR_BYTES) should be mapped onto the sub region [ADDR | |
124 | .. ADDR+MODULO). The modulo value must be a power of two. | |
125 | ||
126 | DEVICE - When non NULL, indicates that this is a callback memory | |
127 | space and specified device's memory callback handler should be | |
128 | called. | |
129 | ||
130 | OPTIONAL_BUFFER - when non NULL, specifies the buffer to use for | |
131 | data read & written to the region. Normally a more efficient | |
132 | internal structure is used. It is assumed that buffer is allocated | |
133 | such that the byte alignmed of OPTIONAL_BUFFER matches ADDR vis | |
134 | (OPTIONAL_BUFFER % 8) == (ADDR % 8)). It is defined to be a sub-optimal | |
135 | hook that allows clients to do nasty things that the interface doesn't | |
136 | accomodate. */ | |
137 | ||
138 | extern void sim_core_attach | |
139 | (SIM_DESC sd, | |
140 | sim_cpu *cpu, | |
141 | int level, | |
142 | unsigned mapmask, | |
143 | int address_space, | |
144 | address_word addr, | |
145 | address_word nr_bytes, | |
146 | unsigned modulo, | |
147 | #if (WITH_HW) | |
148 | struct hw *client, | |
149 | #else | |
150 | device *client, | |
151 | #endif | |
152 | void *optional_buffer); | |
153 | ||
154 | ||
155 | /* Delete a memory section within the core. | |
156 | ||
157 | */ | |
158 | ||
159 | extern void sim_core_detach | |
160 | (SIM_DESC sd, | |
161 | sim_cpu *cpu, | |
162 | int level, | |
163 | int address_space, | |
164 | address_word addr); | |
165 | ||
166 | ||
167 | /* Variable sized read/write | |
168 | ||
169 | Transfer a variable sized block of raw data between the host and | |
6439295f | 170 | target. Should any problems occur, the number of bytes |
c906108c SS |
171 | successfully transfered is returned. |
172 | ||
173 | No host/target byte endian conversion is performed. No xor-endian | |
174 | conversion is performed. | |
175 | ||
176 | If CPU argument, when non NULL, specifies the processor specific | |
177 | address map that is to be used in the transfer. */ | |
178 | ||
179 | ||
180 | extern unsigned sim_core_read_buffer | |
181 | (SIM_DESC sd, | |
182 | sim_cpu *cpu, | |
183 | unsigned map, | |
184 | void *buffer, | |
185 | address_word addr, | |
186 | unsigned nr_bytes); | |
187 | ||
188 | extern unsigned sim_core_write_buffer | |
189 | (SIM_DESC sd, | |
190 | sim_cpu *cpu, | |
191 | unsigned map, | |
192 | const void *buffer, | |
193 | address_word addr, | |
194 | unsigned nr_bytes); | |
195 | ||
196 | ||
197 | ||
198 | /* Configure the core's XOR endian transfer mode. Only applicable | |
199 | when WITH_XOR_ENDIAN is enabled. | |
200 | ||
201 | Targets suporting XOR endian, shall notify the core of any changes | |
202 | in state via this call. | |
203 | ||
204 | The CPU argument, when non NULL, specifes the single processor that | |
205 | the xor-endian configuration is to be applied to. */ | |
206 | ||
207 | extern void sim_core_set_xor | |
208 | (SIM_DESC sd, | |
209 | sim_cpu *cpu, | |
210 | int is_xor); | |
211 | ||
212 | ||
213 | /* XOR version of variable sized read/write. | |
214 | ||
215 | Transfer a variable sized block of raw data between the host and | |
6439295f | 216 | target. Should any problems occur, the number of bytes |
c906108c SS |
217 | successfully transfered is returned. |
218 | ||
219 | No host/target byte endian conversion is performed. If applicable | |
220 | (WITH_XOR_ENDIAN and xor-endian set), xor-endian conversion *is* | |
221 | performed. | |
222 | ||
223 | If CPU argument, when non NULL, specifies the processor specific | |
224 | address map that is to be used in the transfer. */ | |
225 | ||
226 | extern unsigned sim_core_xor_read_buffer | |
227 | (SIM_DESC sd, | |
228 | sim_cpu *cpu, | |
229 | unsigned map, | |
230 | void *buffer, | |
231 | address_word addr, | |
232 | unsigned nr_bytes); | |
233 | ||
234 | extern unsigned sim_core_xor_write_buffer | |
235 | (SIM_DESC sd, | |
236 | sim_cpu *cpu, | |
237 | unsigned map, | |
238 | const void *buffer, | |
239 | address_word addr, | |
240 | unsigned nr_bytes); | |
241 | ||
242 | ||
243 | ||
244 | /* Fixed sized, processor oriented, read/write. | |
245 | ||
246 | Transfer a fixed amout of memory between the host and target. The | |
247 | data transfered is translated from/to host to/from target byte | |
248 | order (including xor endian). Should the transfer fail, the | |
249 | operation shall abort (no return). | |
250 | ||
251 | ALIGNED assumes yhat the specified ADDRESS is correctly alligned | |
252 | for an N byte transfer (no alignment checks are made). Passing an | |
253 | incorrectly aligned ADDRESS is erroneous. | |
254 | ||
255 | UNALIGNED checks/modifies the ADDRESS according to the requirements | |
256 | of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being | |
257 | taken should the check fail. | |
258 | ||
259 | MISSALIGNED transfers the data regardless. | |
260 | ||
261 | Misaligned xor-endian accesses are broken into a sequence of | |
262 | transfers each <= WITH_XOR_ENDIAN bytes */ | |
263 | ||
264 | ||
265 | #define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N,M) \ | |
266 | INLINE_SIM_CORE\ | |
267 | (void) sim_core_write_##ALIGNMENT##_##N \ | |
268 | (sim_cpu *cpu, \ | |
269 | sim_cia cia, \ | |
270 | unsigned map, \ | |
271 | address_word addr, \ | |
272 | unsigned_##M val); | |
273 | ||
274 | DECLARE_SIM_CORE_WRITE_N(aligned,1,1) | |
275 | DECLARE_SIM_CORE_WRITE_N(aligned,2,2) | |
276 | DECLARE_SIM_CORE_WRITE_N(aligned,4,4) | |
277 | DECLARE_SIM_CORE_WRITE_N(aligned,8,8) | |
278 | DECLARE_SIM_CORE_WRITE_N(aligned,16,16) | |
279 | ||
280 | #define sim_core_write_unaligned_1 sim_core_write_aligned_1 | |
281 | DECLARE_SIM_CORE_WRITE_N(unaligned,2,2) | |
282 | DECLARE_SIM_CORE_WRITE_N(unaligned,4,4) | |
283 | DECLARE_SIM_CORE_WRITE_N(unaligned,8,8) | |
284 | DECLARE_SIM_CORE_WRITE_N(unaligned,16,16) | |
285 | ||
286 | DECLARE_SIM_CORE_WRITE_N(misaligned,3,4) | |
287 | DECLARE_SIM_CORE_WRITE_N(misaligned,5,8) | |
288 | DECLARE_SIM_CORE_WRITE_N(misaligned,6,8) | |
289 | DECLARE_SIM_CORE_WRITE_N(misaligned,7,8) | |
290 | ||
291 | #define sim_core_write_1 sim_core_write_aligned_1 | |
292 | #define sim_core_write_2 sim_core_write_aligned_2 | |
293 | #define sim_core_write_4 sim_core_write_aligned_4 | |
294 | #define sim_core_write_8 sim_core_write_aligned_8 | |
295 | #define sim_core_write_16 sim_core_write_aligned_16 | |
296 | ||
297 | #define sim_core_write_unaligned_word XCONCAT2(sim_core_write_unaligned_,WITH_TARGET_WORD_BITSIZE) | |
298 | #define sim_core_write_aligned_word XCONCAT2(sim_core_write_aligned_,WITH_TARGET_WORD_BITSIZE) | |
299 | #define sim_core_write_word XCONCAT2(sim_core_write_,WITH_TARGET_WORD_BITSIZE) | |
300 | ||
301 | #undef DECLARE_SIM_CORE_WRITE_N | |
302 | ||
303 | ||
304 | #define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N,M) \ | |
305 | INLINE_SIM_CORE\ | |
306 | (unsigned_##M) sim_core_read_##ALIGNMENT##_##N \ | |
307 | (sim_cpu *cpu, \ | |
308 | sim_cia cia, \ | |
309 | unsigned map, \ | |
310 | address_word addr); | |
311 | ||
312 | DECLARE_SIM_CORE_READ_N(aligned,1,1) | |
313 | DECLARE_SIM_CORE_READ_N(aligned,2,2) | |
314 | DECLARE_SIM_CORE_READ_N(aligned,4,4) | |
315 | DECLARE_SIM_CORE_READ_N(aligned,8,8) | |
316 | DECLARE_SIM_CORE_READ_N(aligned,16,16) | |
317 | ||
318 | #define sim_core_read_unaligned_1 sim_core_read_aligned_1 | |
319 | DECLARE_SIM_CORE_READ_N(unaligned,2,2) | |
320 | DECLARE_SIM_CORE_READ_N(unaligned,4,4) | |
321 | DECLARE_SIM_CORE_READ_N(unaligned,8,8) | |
322 | DECLARE_SIM_CORE_READ_N(unaligned,16,16) | |
323 | ||
324 | DECLARE_SIM_CORE_READ_N(misaligned,3,4) | |
325 | DECLARE_SIM_CORE_READ_N(misaligned,5,8) | |
326 | DECLARE_SIM_CORE_READ_N(misaligned,6,8) | |
327 | DECLARE_SIM_CORE_READ_N(misaligned,7,8) | |
328 | ||
329 | ||
330 | #define sim_core_read_1 sim_core_read_aligned_1 | |
331 | #define sim_core_read_2 sim_core_read_aligned_2 | |
332 | #define sim_core_read_4 sim_core_read_aligned_4 | |
333 | #define sim_core_read_8 sim_core_read_aligned_8 | |
334 | #define sim_core_read_16 sim_core_read_aligned_16 | |
335 | ||
336 | #define sim_core_read_unaligned_word XCONCAT2(sim_core_read_unaligned_,WITH_TARGET_WORD_BITSIZE) | |
337 | #define sim_core_read_aligned_word XCONCAT2(sim_core_read_aligned_,WITH_TARGET_WORD_BITSIZE) | |
338 | #define sim_core_read_word XCONCAT2(sim_core_read_,WITH_TARGET_WORD_BITSIZE) | |
339 | ||
340 | #undef DECLARE_SIM_CORE_READ_N | |
341 | ||
342 | ||
7a292a7a SS |
343 | #if (WITH_DEVICES) |
344 | /* TODO: create sim/common/device.h */ | |
345 | /* These are defined with each particular cpu. */ | |
346 | void device_error (device *me, char* message, ...); | |
347 | int device_io_read_buffer(device *me, void *dest, int space, address_word addr, unsigned nr_bytes, SIM_DESC sd, sim_cpu *processor, sim_cia cia); | |
348 | int device_io_write_buffer(device *me, const void *source, int space, address_word addr, unsigned nr_bytes, SIM_DESC sd, sim_cpu *processor, sim_cia cia); | |
349 | #endif | |
350 | ||
351 | ||
c906108c | 352 | #endif |