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c967f187 DE |
1 | /* This file is part of the program psim. |
2 | ||
3 | Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
17 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | ||
19 | */ | |
20 | ||
21 | ||
22 | #ifndef _SIM_CORE_H_ | |
23 | #define _SIM_CORE_H_ | |
24 | ||
25 | ||
cd0d873d AC |
26 | /* core signals (error conditions) */ |
27 | ||
28 | typedef enum { | |
29 | sim_core_unmapped_signal, | |
30 | sim_core_unaligned_signal, | |
31 | nr_sim_core_signals, | |
32 | } sim_core_signals; | |
33 | ||
34 | /* define SIM_CORE_SIGNAL to catch these signals - see sim-core.c for details */ | |
35 | ||
36 | ||
37 | ||
c967f187 DE |
38 | /* basic types */ |
39 | ||
40 | typedef struct _sim_core_mapping sim_core_mapping; | |
41 | struct _sim_core_mapping { | |
42 | /* common */ | |
43 | int level; | |
44 | int space; | |
45 | unsigned_word base; | |
46 | unsigned_word bound; | |
47 | unsigned nr_bytes; | |
48 | /* memory map */ | |
49 | int free_buffer; | |
50 | void *buffer; | |
51 | /* callback map */ | |
52 | device *device; | |
7a418800 AC |
53 | /* tracing */ |
54 | int trace; | |
c967f187 DE |
55 | /* growth */ |
56 | sim_core_mapping *next; | |
57 | }; | |
58 | ||
59 | typedef struct _sim_core_map sim_core_map; | |
60 | struct _sim_core_map { | |
61 | sim_core_mapping *first; | |
62 | }; | |
63 | ||
64 | typedef enum { | |
65 | sim_core_read_map, | |
66 | sim_core_write_map, | |
67 | sim_core_execute_map, | |
68 | nr_sim_core_maps, | |
69 | } sim_core_maps; | |
70 | ||
7a418800 AC |
71 | |
72 | /* Main core structure */ | |
73 | ||
c967f187 DE |
74 | typedef struct _sim_core sim_core; |
75 | struct _sim_core { | |
76 | int trace; | |
77 | sim_core_map map[nr_sim_core_maps]; | |
78 | }; | |
79 | ||
80 | ||
cd0d873d AC |
81 | /* Per CPU distributed component of the core. At present this is |
82 | mostly a clone of the global core data structure. */ | |
7a418800 | 83 | |
cd0d873d AC |
84 | typedef struct _sim_cpu_core { |
85 | sim_core common; | |
86 | address_word xor[WITH_XOR_ENDIAN]; | |
87 | } sim_cpu_core; | |
7a418800 AC |
88 | |
89 | ||
c967f187 DE |
90 | /* Install the "core" module. */ |
91 | ||
92 | EXTERN_SIM_CORE\ | |
93 | (SIM_RC) sim_core_install (SIM_DESC sd); | |
94 | ||
95 | ||
c967f187 | 96 | |
cd0d873d AC |
97 | /* Configure the per-cpu core's XOR endian transfer mode. Only |
98 | applicable when WITH_XOR_ENDIAN is enabled. | |
c967f187 | 99 | |
cd0d873d AC |
100 | Targets suporting XOR endian, shall notify the core of any changes |
101 | in state via this call. | |
7a418800 | 102 | |
cd0d873d AC |
103 | FIXME - XOR endian memory transfers currently only work when made |
104 | through a correctly aligned cpu load/store. */ | |
c967f187 DE |
105 | |
106 | EXTERN_SIM_CORE\ | |
cd0d873d AC |
107 | (void) sim_core_set_xor\ |
108 | (sim_cpu *cpu, | |
109 | sim_cia cia, | |
110 | int is_xor); | |
c967f187 DE |
111 | |
112 | ||
113 | ||
7a418800 AC |
114 | /* Create a memory space within the core. |
115 | ||
116 | The CPU option (when non NULL) specifes the single processor that | |
117 | the memory space is to be attached to. (unimplemented) */ | |
c967f187 | 118 | |
cd0d873d | 119 | EXTERN_SIM_CORE\ |
c967f187 DE |
120 | (void) sim_core_attach |
121 | (SIM_DESC sd, | |
7a418800 | 122 | sim_cpu *cpu, |
c967f187 DE |
123 | attach_type attach, |
124 | access_type access, | |
125 | int address_space, | |
cd0d873d | 126 | address_word addr, |
c967f187 DE |
127 | unsigned nr_bytes, /* host limited */ |
128 | device *client, | |
129 | void *optional_buffer); | |
130 | ||
131 | ||
132 | ||
133 | /* Variable sized read/write | |
134 | ||
7a418800 AC |
135 | Transfer a variable sized block of raw data between the host and |
136 | target. Should any problems occure, the number of bytes | |
137 | successfully transfered is returned. */ | |
c967f187 | 138 | |
cd0d873d | 139 | EXTERN_SIM_CORE\ |
c967f187 DE |
140 | (unsigned) sim_core_read_buffer |
141 | (SIM_DESC sd, | |
142 | sim_core_maps map, | |
143 | void *buffer, | |
cd0d873d | 144 | address_word addr, |
c967f187 DE |
145 | unsigned nr_bytes); |
146 | ||
cd0d873d | 147 | EXTERN_SIM_CORE\ |
c967f187 DE |
148 | (unsigned) sim_core_write_buffer |
149 | (SIM_DESC sd, | |
150 | sim_core_maps map, | |
151 | const void *buffer, | |
cd0d873d | 152 | address_word addr, |
c967f187 DE |
153 | unsigned nr_bytes); |
154 | ||
155 | ||
7a418800 | 156 | /* Fixed sized, processor oriented, read/write. |
c967f187 DE |
157 | |
158 | Transfer a fixed amout of memory between the host and target. The | |
7a418800 AC |
159 | data transfered is translated from/to host to/from target byte |
160 | order. Should the transfer fail, the operation shall abort (no | |
161 | return). The aligned alternative makes the assumption that that | |
162 | the address is N byte aligned (no alignment checks are made). The | |
163 | unaligned alternative checks the address for correct byte | |
164 | alignment. Action, as defined by WITH_ALIGNMENT, being taken | |
165 | should the check fail. */ | |
166 | ||
167 | #define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N) \ | |
c967f187 | 168 | INLINE_SIM_CORE\ |
7a418800 AC |
169 | (void) sim_core_write_##ALIGNMENT##_##N \ |
170 | (sim_cpu *cpu, \ | |
171 | sim_cia cia, \ | |
c967f187 | 172 | sim_core_maps map, \ |
cd0d873d | 173 | address_word addr, \ |
c967f187 DE |
174 | unsigned_##N val); |
175 | ||
7a418800 AC |
176 | DECLARE_SIM_CORE_WRITE_N(aligned,1) |
177 | DECLARE_SIM_CORE_WRITE_N(aligned,2) | |
178 | DECLARE_SIM_CORE_WRITE_N(aligned,4) | |
179 | DECLARE_SIM_CORE_WRITE_N(aligned,8) | |
180 | DECLARE_SIM_CORE_WRITE_N(aligned,word) | |
181 | ||
182 | DECLARE_SIM_CORE_WRITE_N(unaligned,1) | |
183 | DECLARE_SIM_CORE_WRITE_N(unaligned,2) | |
184 | DECLARE_SIM_CORE_WRITE_N(unaligned,4) | |
185 | DECLARE_SIM_CORE_WRITE_N(unaligned,8) | |
186 | DECLARE_SIM_CORE_WRITE_N(unaligned,word) | |
187 | ||
188 | #define sim_core_write_1 sim_core_write_aligned_1 | |
189 | #define sim_core_write_2 sim_core_write_aligned_2 | |
190 | #define sim_core_write_4 sim_core_write_aligned_4 | |
191 | #define sim_core_write_8 sim_core_write_aligned_8 | |
c967f187 DE |
192 | |
193 | #undef DECLARE_SIM_CORE_WRITE_N | |
194 | ||
195 | ||
7a418800 | 196 | #define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N) \ |
c967f187 | 197 | INLINE_SIM_CORE\ |
7a418800 AC |
198 | (unsigned_##N) sim_core_read_##ALIGNMENT##_##N \ |
199 | (sim_cpu *cpu, \ | |
200 | sim_cia cia, \ | |
c967f187 | 201 | sim_core_maps map, \ |
cd0d873d | 202 | address_word addr); |
c967f187 | 203 | |
7a418800 AC |
204 | DECLARE_SIM_CORE_READ_N(aligned,1) |
205 | DECLARE_SIM_CORE_READ_N(aligned,2) | |
206 | DECLARE_SIM_CORE_READ_N(aligned,4) | |
207 | DECLARE_SIM_CORE_READ_N(aligned,8) | |
208 | DECLARE_SIM_CORE_READ_N(aligned,word) | |
209 | ||
210 | DECLARE_SIM_CORE_READ_N(unaligned,1) | |
211 | DECLARE_SIM_CORE_READ_N(unaligned,2) | |
212 | DECLARE_SIM_CORE_READ_N(unaligned,4) | |
213 | DECLARE_SIM_CORE_READ_N(unaligned,8) | |
214 | DECLARE_SIM_CORE_READ_N(unaligned,word) | |
215 | ||
216 | #define sim_core_read_1 sim_core_read_aligned_1 | |
217 | #define sim_core_read_2 sim_core_read_aligned_2 | |
218 | #define sim_core_read_4 sim_core_read_aligned_4 | |
219 | #define sim_core_read_8 sim_core_read_aligned_8 | |
c967f187 DE |
220 | |
221 | #undef DECLARE_SIM_CORE_READ_N | |
222 | ||
223 | #endif |