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3971886a AC |
1 | /* Simulator Floating-point support. |
2 | Copyright (C) 1997 Free Software Foundation, Inc. | |
3 | Contributed by Cygnus Support. | |
4 | ||
5 | This file is part of GDB, the GNU debugger. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License along | |
18 | with this program; if not, write to the Free Software Foundation, Inc., | |
19 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | ||
22 | ||
23 | #ifndef _SIM_FPU_C_ | |
24 | #define _SIM_FPU_C_ | |
25 | ||
26 | #include "sim-main.h" | |
27 | #include "sim-fpu.h" | |
28 | ||
29 | #include <math.h> | |
30 | ||
31 | ||
d24f06ee AC |
32 | /* register <-> sim_fpu */ |
33 | ||
34 | INLINE_SIM_FPU (sim_fpu) | |
35 | sim_fpu_32to (unsigned32 s) | |
36 | { | |
37 | sim_fpu ans; | |
38 | ans.val = *(float*) &s; | |
39 | return ans; | |
40 | } | |
41 | ||
42 | ||
43 | INLINE_SIM_FPU (sim_fpu) | |
44 | sim_fpu_64to (unsigned64 s) | |
45 | { | |
46 | sim_fpu ans; | |
47 | ans.val = *(double*) &s; | |
48 | return ans; | |
49 | } | |
50 | ||
51 | ||
52 | INLINE_SIM_FPU (unsigned32) | |
53 | sim_fpu_to32 (sim_fpu l) | |
54 | { | |
55 | float s = l.val; | |
56 | return *(unsigned32*) &s; | |
57 | } | |
58 | ||
59 | ||
60 | INLINE_SIM_FPU (unsigned64) | |
61 | sim_fpu_to64 (sim_fpu s) | |
62 | { | |
63 | return *(unsigned64*) &s.val; | |
64 | } | |
65 | ||
66 | ||
67 | /* Arithmetic ops */ | |
68 | ||
3971886a AC |
69 | INLINE_SIM_FPU (sim_fpu) |
70 | sim_fpu_add (sim_fpu l, | |
71 | sim_fpu r) | |
72 | { | |
73 | sim_fpu ans; | |
74 | ans.val = l.val + r.val; | |
75 | return ans; | |
76 | } | |
77 | ||
78 | ||
79 | INLINE_SIM_FPU (sim_fpu) | |
80 | sim_fpu_sub (sim_fpu l, | |
81 | sim_fpu r) | |
82 | { | |
83 | sim_fpu ans; | |
84 | ans.val = l.val - r.val; | |
85 | return ans; | |
86 | } | |
87 | ||
88 | ||
89 | INLINE_SIM_FPU (sim_fpu) | |
90 | sim_fpu_mul (sim_fpu l, | |
91 | sim_fpu r) | |
92 | { | |
93 | sim_fpu ans; | |
94 | ans.val = l.val * r.val; | |
95 | return ans; | |
96 | } | |
97 | ||
98 | ||
99 | INLINE_SIM_FPU (sim_fpu) | |
100 | sim_fpu_div (sim_fpu l, | |
101 | sim_fpu r) | |
102 | { | |
103 | sim_fpu ans; | |
104 | ans.val = l.val / r.val; | |
105 | return ans; | |
106 | } | |
107 | ||
108 | ||
109 | INLINE_SIM_FPU (sim_fpu) | |
110 | sim_fpu_inv (sim_fpu r) | |
111 | { | |
112 | sim_fpu ans; | |
113 | ans.val = 1 / r.val; | |
114 | return ans; | |
115 | } | |
116 | ||
117 | ||
118 | INLINE_SIM_FPU (sim_fpu) | |
119 | sim_fpu_sqrt (sim_fpu r) | |
120 | { | |
121 | sim_fpu ans; | |
122 | ans.val = sqrt (r.val); | |
123 | return ans; | |
124 | } | |
125 | ||
126 | ||
d24f06ee AC |
127 | /* int/long -> sim_fpu */ |
128 | ||
3971886a | 129 | INLINE_SIM_FPU (sim_fpu) |
d24f06ee | 130 | sim_fpu_i32to (signed32 s) |
3971886a AC |
131 | { |
132 | sim_fpu ans; | |
d24f06ee | 133 | ans.val = s; |
3971886a AC |
134 | return ans; |
135 | } | |
136 | ||
137 | ||
138 | INLINE_SIM_FPU (sim_fpu) | |
d24f06ee | 139 | sim_fpu_u32to (unsigned32 s) |
3971886a AC |
140 | { |
141 | sim_fpu ans; | |
d24f06ee | 142 | ans.val = s; |
3971886a AC |
143 | return ans; |
144 | } | |
145 | ||
146 | ||
d24f06ee AC |
147 | INLINE_SIM_FPU (sim_fpu) |
148 | sim_fpu_i64to (signed64 s) | |
3971886a | 149 | { |
d24f06ee AC |
150 | sim_fpu ans; |
151 | ans.val = s; | |
152 | return ans; | |
3971886a AC |
153 | } |
154 | ||
155 | ||
d24f06ee AC |
156 | INLINE_SIM_FPU (sim_fpu) |
157 | sim_fpu_u64to (unsigned64 s) | |
3971886a | 158 | { |
d24f06ee AC |
159 | sim_fpu ans; |
160 | ans.val = s; | |
161 | return ans; | |
3971886a AC |
162 | } |
163 | ||
164 | ||
d24f06ee AC |
165 | /* sim_fpu -> host format */ |
166 | ||
3971886a AC |
167 | INLINE_SIM_FPU (float) |
168 | sim_fpu_2f (sim_fpu f) | |
169 | { | |
170 | return f.val; | |
171 | } | |
172 | ||
173 | ||
174 | INLINE_SIM_FPU (double) | |
175 | sim_fpu_2d (sim_fpu s) | |
176 | { | |
177 | return s.val; | |
178 | } | |
179 | ||
180 | ||
d24f06ee | 181 | #if 0 |
3971886a AC |
182 | INLINE_SIM_FPU (sim_fpu) |
183 | sim_fpu_f2 (float f) | |
184 | { | |
185 | sim_fpu ans; | |
186 | ans.val = f; | |
187 | return ans; | |
188 | } | |
d24f06ee | 189 | #endif |
3971886a AC |
190 | |
191 | ||
d24f06ee | 192 | #if 0 |
3971886a AC |
193 | INLINE_SIM_FPU (sim_fpu) |
194 | sim_fpu_d2 (double d) | |
195 | { | |
196 | sim_fpu ans; | |
197 | ans.val = d; | |
198 | return ans; | |
199 | } | |
d24f06ee AC |
200 | #endif |
201 | ||
202 | ||
3971886a | 203 | |
d24f06ee | 204 | /* General */ |
3971886a AC |
205 | |
206 | INLINE_SIM_FPU (int) | |
207 | sim_fpu_is_nan (sim_fpu d) | |
208 | { | |
209 | return 0; /* FIXME - detect NaN */ | |
210 | } | |
211 | ||
212 | ||
d24f06ee AC |
213 | /* Compare operators */ |
214 | ||
3971886a | 215 | INLINE_SIM_FPU (int) |
d24f06ee AC |
216 | sim_fpu_is_lt (sim_fpu l, |
217 | sim_fpu r) | |
218 | { | |
219 | return (l.val < r.val); | |
220 | } | |
221 | ||
222 | INLINE_SIM_FPU (int) | |
223 | sim_fpu_is_le (sim_fpu l, | |
224 | sim_fpu r) | |
225 | { | |
226 | return (l.val <= r.val); | |
227 | } | |
228 | ||
229 | INLINE_SIM_FPU (int) | |
230 | sim_fpu_is_eq (sim_fpu l, | |
231 | sim_fpu r) | |
232 | { | |
233 | return (l.val == r.val); | |
234 | } | |
235 | ||
236 | INLINE_SIM_FPU (int) | |
237 | sim_fpu_is_ne (sim_fpu l, | |
238 | sim_fpu r) | |
239 | { | |
240 | return (l.val != r.val); | |
241 | } | |
242 | ||
243 | INLINE_SIM_FPU (int) | |
244 | sim_fpu_is_ge (sim_fpu l, | |
245 | sim_fpu r) | |
246 | { | |
247 | return (l.val >= r.val); | |
248 | } | |
249 | ||
250 | INLINE_SIM_FPU (int) | |
251 | sim_fpu_is_gt (sim_fpu l, | |
252 | sim_fpu r) | |
3971886a | 253 | { |
d24f06ee | 254 | return (l.val > r.val); |
3971886a AC |
255 | } |
256 | ||
257 | #endif |