* config/rs6000/tm-rs6000.h (SIG_FRAME_LR_OFFSET): Define.
[deliverable/binutils-gdb.git] / sim / common / sim-fpu.c
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1/* Simulator Floating-point support.
2 Copyright (C) 1997 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
4
5This file is part of GDB, the GNU debugger.
6
7This program is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
12This program is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License along
18with this program; if not, write to the Free Software Foundation, Inc.,
1959 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21
22
23#ifndef _SIM_FPU_C_
24#define _SIM_FPU_C_
25
26#include "sim-main.h"
27#include "sim-fpu.h"
28
29#include <math.h>
30
31
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32/* register <-> sim_fpu */
33
34INLINE_SIM_FPU (sim_fpu)
35sim_fpu_32to (unsigned32 s)
36{
37 sim_fpu ans;
38 ans.val = *(float*) &s;
39 return ans;
40}
41
42
43INLINE_SIM_FPU (sim_fpu)
44sim_fpu_64to (unsigned64 s)
45{
46 sim_fpu ans;
47 ans.val = *(double*) &s;
48 return ans;
49}
50
51
52INLINE_SIM_FPU (unsigned32)
53sim_fpu_to32 (sim_fpu l)
54{
55 float s = l.val;
56 return *(unsigned32*) &s;
57}
58
59
60INLINE_SIM_FPU (unsigned64)
61sim_fpu_to64 (sim_fpu s)
62{
63 return *(unsigned64*) &s.val;
64}
65
66
67/* Arithmetic ops */
68
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69INLINE_SIM_FPU (sim_fpu)
70sim_fpu_add (sim_fpu l,
71 sim_fpu r)
72{
73 sim_fpu ans;
74 ans.val = l.val + r.val;
75 return ans;
76}
77
78
79INLINE_SIM_FPU (sim_fpu)
80sim_fpu_sub (sim_fpu l,
81 sim_fpu r)
82{
83 sim_fpu ans;
84 ans.val = l.val - r.val;
85 return ans;
86}
87
88
89INLINE_SIM_FPU (sim_fpu)
90sim_fpu_mul (sim_fpu l,
91 sim_fpu r)
92{
93 sim_fpu ans;
94 ans.val = l.val * r.val;
95 return ans;
96}
97
98
99INLINE_SIM_FPU (sim_fpu)
100sim_fpu_div (sim_fpu l,
101 sim_fpu r)
102{
103 sim_fpu ans;
104 ans.val = l.val / r.val;
105 return ans;
106}
107
108
109INLINE_SIM_FPU (sim_fpu)
110sim_fpu_inv (sim_fpu r)
111{
112 sim_fpu ans;
113 ans.val = 1 / r.val;
114 return ans;
115}
116
117
118INLINE_SIM_FPU (sim_fpu)
119sim_fpu_sqrt (sim_fpu r)
120{
121 sim_fpu ans;
122 ans.val = sqrt (r.val);
123 return ans;
124}
125
126
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127/* int/long -> sim_fpu */
128
3971886a 129INLINE_SIM_FPU (sim_fpu)
d24f06ee 130sim_fpu_i32to (signed32 s)
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131{
132 sim_fpu ans;
d24f06ee 133 ans.val = s;
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134 return ans;
135}
136
137
138INLINE_SIM_FPU (sim_fpu)
d24f06ee 139sim_fpu_u32to (unsigned32 s)
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140{
141 sim_fpu ans;
d24f06ee 142 ans.val = s;
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143 return ans;
144}
145
146
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147INLINE_SIM_FPU (sim_fpu)
148sim_fpu_i64to (signed64 s)
3971886a 149{
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150 sim_fpu ans;
151 ans.val = s;
152 return ans;
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153}
154
155
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156INLINE_SIM_FPU (sim_fpu)
157sim_fpu_u64to (unsigned64 s)
3971886a 158{
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159 sim_fpu ans;
160 ans.val = s;
161 return ans;
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162}
163
164
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165/* sim_fpu -> host format */
166
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167INLINE_SIM_FPU (float)
168sim_fpu_2f (sim_fpu f)
169{
170 return f.val;
171}
172
173
174INLINE_SIM_FPU (double)
175sim_fpu_2d (sim_fpu s)
176{
177 return s.val;
178}
179
180
d24f06ee 181#if 0
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182INLINE_SIM_FPU (sim_fpu)
183sim_fpu_f2 (float f)
184{
185 sim_fpu ans;
186 ans.val = f;
187 return ans;
188}
d24f06ee 189#endif
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190
191
d24f06ee 192#if 0
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193INLINE_SIM_FPU (sim_fpu)
194sim_fpu_d2 (double d)
195{
196 sim_fpu ans;
197 ans.val = d;
198 return ans;
199}
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200#endif
201
202
3971886a 203
d24f06ee 204/* General */
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205
206INLINE_SIM_FPU (int)
207sim_fpu_is_nan (sim_fpu d)
208{
209 return 0; /* FIXME - detect NaN */
210}
211
212
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213/* Compare operators */
214
3971886a 215INLINE_SIM_FPU (int)
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216sim_fpu_is_lt (sim_fpu l,
217 sim_fpu r)
218{
219 return (l.val < r.val);
220}
221
222INLINE_SIM_FPU (int)
223sim_fpu_is_le (sim_fpu l,
224 sim_fpu r)
225{
226 return (l.val <= r.val);
227}
228
229INLINE_SIM_FPU (int)
230sim_fpu_is_eq (sim_fpu l,
231 sim_fpu r)
232{
233 return (l.val == r.val);
234}
235
236INLINE_SIM_FPU (int)
237sim_fpu_is_ne (sim_fpu l,
238 sim_fpu r)
239{
240 return (l.val != r.val);
241}
242
243INLINE_SIM_FPU (int)
244sim_fpu_is_ge (sim_fpu l,
245 sim_fpu r)
246{
247 return (l.val >= r.val);
248}
249
250INLINE_SIM_FPU (int)
251sim_fpu_is_gt (sim_fpu l,
252 sim_fpu r)
3971886a 253{
d24f06ee 254 return (l.val > r.val);
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255}
256
257#endif
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