[deliverable/binutils-gdb.git] / sim / common / sim-n-core.h

/*  This file is part of the program psim.

    Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 
    */


#ifndef N
#error "N must be #defined"
#endif
#ifndef M
#define M N
#endif

/* N: The number of bytes of data to transfer.
   M: The number of bytes in the type used to transfer the data */

#if (N > M)
#error "N (nr bytes of data) must be <= M (nr of bytes in data type)"
#endif


#include "symcat.h"

/* NOTE: see end of file for #undef of these macros */

#define unsigned_M XCONCAT2(unsigned_,M)

#define T2H_M XCONCAT2(T2H_,M)
#define H2T_M XCONCAT2(H2T_,M)
#define SWAP_M XCONCAT2(SWAP_,M)

#define sim_core_read_aligned_N XCONCAT2(sim_core_read_aligned_,N)
#define sim_core_read_unaligned_N XCONCAT2(sim_core_read_unaligned_,N)
#define sim_core_read_misaligned_N XCONCAT2(sim_core_read_misaligned_,N)
#define sim_core_write_aligned_N XCONCAT2(sim_core_write_aligned_,N)
#define sim_core_write_unaligned_N XCONCAT2(sim_core_write_unaligned_,N)
#define sim_core_write_misaligned_N XCONCAT2(sim_core_write_misaligned_,N)
#define sim_core_trace_M XCONCAT2(sim_core_trace_,M)
#define sim_core_dummy_M XCONCAT2(sim_core_dummy_,M)


#if (M == N && N > 1)
/* dummy variable used as a return value when nothing else is
   available and the compiler is complaining */
static unsigned_M sim_core_dummy_M;
#endif


/* TAGS: sim_core_trace_1 sim_core_trace_2 */
/* TAGS: sim_core_trace_4 sim_core_trace_8 */
/* TAGS: sim_core_trace_16 */

#if (M == N)
STATIC_SIM_CORE(void)
sim_core_trace_M (sim_cpu *cpu,
		  sim_cia cia,
		  int line_nr,
		  transfer_type type,
		  sim_core_maps map,
		  address_word addr,
		  unsigned_M val,
		  int nr_bytes)
{
  char *transfer = (type == read_transfer ? "read" : "write");
  char *direction = (type == read_transfer ? "->" : "<-");

  if (TRACE_DEBUG_P (cpu))
    trace_printf (CPU_STATE (cpu), cpu, "sim-n-core.h:%d: ", line_nr);

#if (M == 16)
  trace_printf (CPU_STATE (cpu), cpu,
		"%s-%d %s:0x%08lx %s 0x%08lx%08lx%08lx%08lx\n",
		transfer, nr_bytes,
		sim_core_map_to_str (map),
		(unsigned long) addr,
		direction,
		(unsigned long) V4_16 (val, 0),
		(unsigned long) V4_16 (val, 1),
		(unsigned long) V4_16 (val, 2),
		(unsigned long) V4_16 (val, 3));
#endif
#if (M == 8)
  trace_printf (CPU_STATE (cpu), cpu,
		"%s-%d %s:0x%08lx %s 0x%08lx%08lx\n",
		transfer, nr_bytes,
		sim_core_map_to_str (map),
		(unsigned long) addr,
		direction,
		(unsigned long) V4_8 (val, 0),
		(unsigned long) V4_8 (val, 1));
#endif
#if (M == 4)
  trace_printf (CPU_STATE (cpu), cpu,
		"%s-%d %s:0x%08lx %s 0x%08lx\n",
		transfer,
		nr_bytes,
		sim_core_map_to_str (map),
		(unsigned long) addr,
		direction,
		(unsigned long) val);
#endif
#if (M == 2)
  trace_printf (CPU_STATE (cpu), cpu,
		"%s-%d %s:0x%08lx %s 0x%04lx\n",
		transfer,
		nr_bytes,
		sim_core_map_to_str (map),
		(unsigned long) addr,
		direction,
		(unsigned long) val);
#endif
#if (M == 1)
  trace_printf (CPU_STATE (cpu), cpu,
		"%s-%d %s:0x%08lx %s 0x%02lx\n",
		transfer,
		nr_bytes,
		sim_core_map_to_str (map),
		(unsigned long) addr,
		direction,
		(unsigned long) val);
#endif
}
#endif

  
/* TAGS: sim_core_read_aligned_1 sim_core_read_aligned_2 */
/* TAGS: sim_core_read_aligned_4 sim_core_read_aligned_8 */
/* TAGS: sim_core_read_aligned_16 */

#if (M == N)
INLINE_SIM_CORE(unsigned_M)
sim_core_read_aligned_N(sim_cpu *cpu,
			sim_cia cia,
			sim_core_maps map,
			address_word xaddr)
{
  sim_cpu_core *cpu_core = CPU_CORE (cpu);
  sim_core_common *core = &cpu_core->common;
  unsigned_M val;
  sim_core_mapping *mapping;
  address_word addr;
#if WITH_XOR_ENDIAN != 0
  if (WITH_XOR_ENDIAN)
    addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN];
  else
#endif
    addr = xaddr;
  mapping = sim_core_find_mapping (core, map, addr, N, read_transfer, 1 /*abort*/, cpu, cia);
#if (WITH_DEVICES)
  if (WITH_CALLBACK_MEMORY && mapping->device != NULL) {
    unsigned_M data;
    if (device_io_read_buffer (mapping->device, &data, mapping->space, addr, N, cpu, cia) != N)
      device_error (mapping->device, "internal error - %s - io_read_buffer should not fail",
		    XSTRING (sim_core_read_aligned_N));
    val = T2H_M (data);
  }
  else
#endif
    val = T2H_M (*(unsigned_M*) sim_core_translate (mapping, addr));
  PROFILE_COUNT_CORE (cpu, addr, N, map);
  if (TRACE_P (cpu, TRACE_CORE_IDX))
    sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
  return val;
}
#endif

/* TAGS: sim_core_read_unaligned_1 sim_core_read_unaligned_2 */
/* TAGS: sim_core_read_unaligned_4 sim_core_read_unaligned_8 */
/* TAGS: sim_core_read_unaligned_16 */

#if (M == N && N > 1)
INLINE_SIM_CORE(unsigned_M)
sim_core_read_unaligned_N(sim_cpu *cpu,
			  sim_cia cia,
			  sim_core_maps map,
			  address_word addr)
{
  int alignment = N - 1;
  /* if hardwired to forced alignment just do it */
  if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
    return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
  else if ((addr & alignment) == 0)
    return sim_core_read_aligned_N (cpu, cia, map, addr);
  else
    switch (CURRENT_ALIGNMENT)
      {
      case STRICT_ALIGNMENT:
	SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
			 read_transfer, sim_core_unaligned_signal);
      case NONSTRICT_ALIGNMENT:
	{
	  unsigned_M val;
	  if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N)
	    SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
			     read_transfer, sim_core_unaligned_signal);
	  val = T2H_M(val);
	  PROFILE_COUNT_CORE (cpu, addr, N, map);
	  if (TRACE_P (cpu, TRACE_CORE_IDX))
	    sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
	  return val;
	}
      case FORCED_ALIGNMENT:
	return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
      case MIXED_ALIGNMENT:
	sim_engine_abort (CPU_STATE (cpu), cpu, cia,
			  "internal error - %s - mixed alignment",
			  XSTRING (sim_core_read_unaligned_N));
      default:
	sim_engine_abort (CPU_STATE (cpu), cpu, cia,
			  "internal error - %s - bad switch",
			  XSTRING (sim_core_read_unaligned_N));
	/* to keep some compilers happy, we return a dummy */
	return sim_core_dummy_M;
      }
}
#endif

/* TAGS: sim_core_read_misaligned_3 sim_core_read_misaligned_5 */
/* TAGS: sim_core_read_misaligned_6 sim_core_read_misaligned_7 */

#if (M != N)
INLINE_SIM_CORE(unsigned_M)
sim_core_read_misaligned_N(sim_cpu *cpu,
			  sim_cia cia,
			  sim_core_maps map,
			  address_word addr)
{
  unsigned_M val = 0;
  if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N)
    SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
		     read_transfer, sim_core_unaligned_signal);
  if (CURRENT_HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER)
    val = SWAP_M (val);
  if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
    val >>= (M - N) * 8;
  PROFILE_COUNT_CORE (cpu, addr, N, map);
  if (TRACE_P (cpu, TRACE_CORE_IDX))
    sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
  return val;
}
#endif

/* TAGS: sim_core_write_aligned_1 sim_core_write_aligned_2 */
/* TAGS: sim_core_write_aligned_4 sim_core_write_aligned_8 */
/* TAGS: sim_core_write_aligned_16 */

#if (M == N)
INLINE_SIM_CORE(void)
sim_core_write_aligned_N(sim_cpu *cpu,
			 sim_cia cia,
			 sim_core_maps map,
			 address_word xaddr,
			 unsigned_M val)
{
  sim_cpu_core *cpu_core = CPU_CORE (cpu);
  sim_core_common *core = &cpu_core->common;
  sim_core_mapping *mapping;
  address_word addr;
#if WITH_XOR_ENDIAN != 0
  if (WITH_XOR_ENDIAN)
    addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN];
  else
#endif
    addr = xaddr;
  mapping = sim_core_find_mapping (core, map, addr, N, write_transfer, 1 /*abort*/, cpu, cia);
#if (WITH_DEVICES)
  if (WITH_CALLBACK_MEMORY && mapping->device != NULL) {
    unsigned_M data = H2T_M (val);
    if (device_io_write_buffer (mapping->device, &data, mapping->space, addr, N, cpu, cia) != N)
      device_error (mapping->device, "internal error - %s - io_write_buffer should not fail",
		    XSTRING (sim_core_write_aligned_N));
  }
  else
#endif
    *(unsigned_M*) sim_core_translate (mapping, addr) = H2T_M (val);
  PROFILE_COUNT_CORE (cpu, addr, N, map);
  if (TRACE_P (cpu, TRACE_CORE_IDX))
    sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
}
#endif

/* TAGS: sim_core_write_unaligned_1 sim_core_write_unaligned_2 */
/* TAGS: sim_core_write_unaligned_4 sim_core_write_unaligned_8 */
/* TAGS: sim_core_write_unaligned_16 */

#if (M == N && N > 1)
INLINE_SIM_CORE(void)
sim_core_write_unaligned_N(sim_cpu *cpu,
			   sim_cia cia,
			   sim_core_maps map,
			   address_word addr,
			   unsigned_M val)
{
  int alignment = N - 1;
  /* if hardwired to forced alignment just do it */
  if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
    sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
  else if ((addr & alignment) == 0)
    sim_core_write_aligned_N (cpu, cia, map, addr, val);
  else
    switch (CURRENT_ALIGNMENT)
      {
      case STRICT_ALIGNMENT:
	SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
			 write_transfer, sim_core_unaligned_signal);
	break;
      case NONSTRICT_ALIGNMENT:
	{
	  unsigned_M data = H2T_M (val);
	  if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N)
	    SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
			     write_transfer, sim_core_unaligned_signal);
	  PROFILE_COUNT_CORE (cpu, addr, N, map);
	  if (TRACE_P (cpu, TRACE_CORE_IDX))
	    sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
	  break;
	}
      case FORCED_ALIGNMENT:
	sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
	break;
      case MIXED_ALIGNMENT:
	sim_engine_abort (CPU_STATE (cpu), cpu, cia,
			  "internal error - %s - mixed alignment",
			  XSTRING (sim_core_write_unaligned_N));
	break;
      default:
	sim_engine_abort (CPU_STATE (cpu), cpu, cia,
			  "internal error - %s - bad switch",
			  XSTRING (sim_core_write_unaligned_N));
	break;
      }
}
#endif

/* TAGS: sim_core_write_misaligned_3 sim_core_write_misaligned_5 */
/* TAGS: sim_core_write_misaligned_6 sim_core_write_misaligned_7 */

#if (M != N)
INLINE_SIM_CORE(void)
sim_core_write_misaligned_N(sim_cpu *cpu,
			   sim_cia cia,
			   sim_core_maps map,
			   address_word addr,
			   unsigned_M val)
{
  unsigned_M data = val;
  if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
    data <<= (M - N) * 8;
  if (CURRENT_HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER)
    data = SWAP_M (data);
  if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N)
    SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
		     write_transfer, sim_core_unaligned_signal);
  PROFILE_COUNT_CORE (cpu, addr, N, map);
  if (TRACE_P (cpu, TRACE_CORE_IDX))
    sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
}
#endif


/* NOTE: see start of file for #define of these macros */
#undef unsigned_M
#undef T2H_M
#undef H2T_M
#undef SWAP_M
#undef sim_core_read_aligned_N
#undef sim_core_read_unaligned_N
#undef sim_core_read_misaligned_N
#undef sim_core_write_aligned_N
#undef sim_core_write_unaligned_N
#undef sim_core_write_misaligned_N
#undef sim_core_trace_M
#undef sim_core_dummy_M
#undef M
#undef N
Commit	Line	Data
a1dc3945 AC	1	/* This file is part of the program psim.
	2
	3	Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
	4
	5	This program is free software; you can redistribute it and/or modify
	6	it under the terms of the GNU General Public License as published by
	7	the Free Software Foundation; either version 2 of the License, or
	8	(at your option) any later version.
	9
	10	This program is distributed in the hope that it will be useful,
	11	but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	GNU General Public License for more details.
	14
	15	You should have received a copy of the GNU General Public License
	16	along with this program; if not, write to the Free Software
	17	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	18
	19	*/
	20
	21
	22	#ifndef N
	23	#error "N must be #defined"
	24	#endif
63be8feb AC	25	#ifndef M
	26	#define M N
	27	#endif
a1dc3945	28
36dbc8bb DE	29	/* N: The number of bytes of data to transfer.
	30	M: The number of bytes in the type used to transfer the data */
	31
	32	#if (N > M)
	33	#error "N (nr bytes of data) must be <= M (nr of bytes in data type)"
	34	#endif
	35
	36
	37	#include "symcat.h"
1fe05280	38
a1dc3945	39	/* NOTE: see end of file for #undef of these macros */
63be8feb AC	40
	41	#define unsigned_M XCONCAT2(unsigned_,M)
	42
	43	#define T2H_M XCONCAT2(T2H_,M)
	44	#define H2T_M XCONCAT2(H2T_,M)
	45	#define SWAP_M XCONCAT2(SWAP_,M)
a1dc3945	46
7a418800	47	#define sim_core_read_aligned_N XCONCAT2(sim_core_read_aligned_,N)
7a418800	48	#define sim_core_read_unaligned_N XCONCAT2(sim_core_read_unaligned_,N)
63be8feb AC	49	#define sim_core_read_misaligned_N XCONCAT2(sim_core_read_misaligned_,N)
63be8feb AC	50	#define sim_core_write_aligned_N XCONCAT2(sim_core_write_aligned_,N)
7a418800	51	#define sim_core_write_unaligned_N XCONCAT2(sim_core_write_unaligned_,N)
63be8feb AC	52	#define sim_core_write_misaligned_N XCONCAT2(sim_core_write_misaligned_,N)
63be8feb AC	53	#define sim_core_trace_M XCONCAT2(sim_core_trace_,M)
36dbc8bb DE	54	#define sim_core_dummy_M XCONCAT2(sim_core_dummy_,M)
	55
	56
	57	#if (M == N && N > 1)
	58	/* dummy variable used as a return value when nothing else is
	59	available and the compiler is complaining */
	60	static unsigned_M sim_core_dummy_M;
	61	#endif
a1dc3945	62
f45dd42b AC	63
	64	/* TAGS: sim_core_trace_1 sim_core_trace_2 */
	65	/* TAGS: sim_core_trace_4 sim_core_trace_8 */
63be8feb	66	/* TAGS: sim_core_trace_16 */
f45dd42b	67
63be8feb	68	#if (M == N)
f45dd42b	69	STATIC_SIM_CORE(void)
63be8feb	70	sim_core_trace_M (sim_cpu *cpu,
f45dd42b	71	sim_cia cia,
a86809d3	72	int line_nr,
63be8feb	73	transfer_type type,
f45dd42b AC	74	sim_core_maps map,
f45dd42b AC	75	address_word addr,
63be8feb AC	76	unsigned_M val,
63be8feb AC	77	int nr_bytes)
f45dd42b	78	{
63be8feb AC	79	char *transfer = (type == read_transfer ? "read" : "write");
63be8feb AC	80	char *direction = (type == read_transfer ? "->" : "<-");
9e8a900a DE	81
	82	if (TRACE_DEBUG_P (cpu))
	83	trace_printf (CPU_STATE (cpu), cpu, "sim-n-core.h:%d: ", line_nr);
	84
63be8feb	85	#if (M == 16)
f45dd42b	86	trace_printf (CPU_STATE (cpu), cpu,
9e8a900a	87	"%s-%d %s:0x%08lx %s 0x%08lx%08lx%08lx%08lx\n",
63be8feb	88	transfer, nr_bytes,
f45dd42b AC	89	sim_core_map_to_str (map),
f45dd42b AC	90	(unsigned long) addr,
63be8feb	91	direction,
f45dd42b AC	92	(unsigned long) V4_16 (val, 0),
	93	(unsigned long) V4_16 (val, 1),
	94	(unsigned long) V4_16 (val, 2),
	95	(unsigned long) V4_16 (val, 3));
	96	#endif
63be8feb	97	#if (M == 8)
f45dd42b	98	trace_printf (CPU_STATE (cpu), cpu,
9e8a900a	99	"%s-%d %s:0x%08lx %s 0x%08lx%08lx\n",
63be8feb	100	transfer, nr_bytes,
f45dd42b AC	101	sim_core_map_to_str (map),
f45dd42b AC	102	(unsigned long) addr,
63be8feb	103	direction,
f45dd42b AC	104	(unsigned long) V4_8 (val, 0),
	105	(unsigned long) V4_8 (val, 1));
	106	#endif
63be8feb AC	107	#if (M == 4)
63be8feb AC	108	trace_printf (CPU_STATE (cpu), cpu,
9e8a900a	109	"%s-%d %s:0x%08lx %s 0x%08lx\n",
63be8feb AC	110	transfer,
	111	nr_bytes,
	112	sim_core_map_to_str (map),
	113	(unsigned long) addr,
	114	direction,
	115	(unsigned long) val);
	116	#endif
	117	#if (M == 2)
f45dd42b	118	trace_printf (CPU_STATE (cpu), cpu,
9e8a900a	119	"%s-%d %s:0x%08lx %s 0x%04lx\n",
63be8feb AC	120	transfer,
63be8feb AC	121	nr_bytes,
f45dd42b AC	122	sim_core_map_to_str (map),
f45dd42b AC	123	(unsigned long) addr,
63be8feb AC	124	direction,
	125	(unsigned long) val);
	126	#endif
	127	#if (M == 1)
	128	trace_printf (CPU_STATE (cpu), cpu,
9e8a900a	129	"%s-%d %s:0x%08lx %s 0x%02lx\n",
63be8feb AC	130	transfer,
	131	nr_bytes,
	132	sim_core_map_to_str (map),
	133	(unsigned long) addr,
	134	direction,
f45dd42b AC	135	(unsigned long) val);
	136	#endif
	137	}
63be8feb	138	#endif
f45dd42b AC	139
f45dd42b AC	140
74db699d DE	141	/* TAGS: sim_core_read_aligned_1 sim_core_read_aligned_2 */
74db699d DE	142	/* TAGS: sim_core_read_aligned_4 sim_core_read_aligned_8 */
63be8feb	143	/* TAGS: sim_core_read_aligned_16 */
a1dc3945	144
63be8feb AC	145	#if (M == N)
63be8feb AC	146	INLINE_SIM_CORE(unsigned_M)
7a418800 AC	147	sim_core_read_aligned_N(sim_cpu *cpu,
	148	sim_cia cia,
	149	sim_core_maps map,
1b217de0	150	address_word xaddr)
a1dc3945	151	{
cd0d873d	152	sim_cpu_core *cpu_core = CPU_CORE (cpu);
2f2e6c5d	153	sim_core_common *core = &cpu_core->common;
63be8feb	154	unsigned_M val;
cd0d873d AC	155	sim_core_mapping *mapping;
cd0d873d AC	156	address_word addr;
1b217de0	157	#if WITH_XOR_ENDIAN != 0
cd0d873d	158	if (WITH_XOR_ENDIAN)
63be8feb	159	addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN];
cd0d873d	160	else
1b217de0	161	#endif
cd0d873d	162	addr = xaddr;
63be8feb	163	mapping = sim_core_find_mapping (core, map, addr, N, read_transfer, 1 /abort/, cpu, cia);
a1dc3945 AC	164	#if (WITH_DEVICES)
a1dc3945 AC	165	if (WITH_CALLBACK_MEMORY && mapping->device != NULL) {
63be8feb	166	unsigned_M data;
36dbc8bb	167	if (device_io_read_buffer (mapping->device, &data, mapping->space, addr, N, cpu, cia) != N)
cd0d873d AC	168	device_error (mapping->device, "internal error - %s - io_read_buffer should not fail",
cd0d873d AC	169	XSTRING (sim_core_read_aligned_N));
63be8feb	170	val = T2H_M (data);
a1dc3945 AC	171	}
	172	else
	173	#endif
63be8feb AC	174	val = T2H_M ((unsigned_M) sim_core_translate (mapping, addr));
63be8feb AC	175	PROFILE_COUNT_CORE (cpu, addr, N, map);
7a418800	176	if (TRACE_P (cpu, TRACE_CORE_IDX))
63be8feb	177	sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
1fe05280	178	return val;
a1dc3945	179	}
63be8feb	180	#endif
a1dc3945	181
74db699d DE	182	/* TAGS: sim_core_read_unaligned_1 sim_core_read_unaligned_2 */
74db699d DE	183	/* TAGS: sim_core_read_unaligned_4 sim_core_read_unaligned_8 */
63be8feb	184	/* TAGS: sim_core_read_unaligned_16 */
a1dc3945	185
63be8feb AC	186	#if (M == N && N > 1)
63be8feb AC	187	INLINE_SIM_CORE(unsigned_M)
7a418800 AC	188	sim_core_read_unaligned_N(sim_cpu *cpu,
	189	sim_cia cia,
	190	sim_core_maps map,
cd0d873d	191	address_word addr)
7a418800	192	{
63be8feb	193	int alignment = N - 1;
7a418800 AC	194	/* if hardwired to forced alignment just do it */
	195	if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
	196	return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
	197	else if ((addr & alignment) == 0)
	198	return sim_core_read_aligned_N (cpu, cia, map, addr);
	199	else
	200	switch (CURRENT_ALIGNMENT)
	201	{
	202	case STRICT_ALIGNMENT:
63be8feb	203	SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
cd0d873d	204	read_transfer, sim_core_unaligned_signal);
7a418800 AC	205	case NONSTRICT_ALIGNMENT:
7a418800 AC	206	{
63be8feb AC	207	unsigned_M val;
	208	if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N)
	209	SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
cd0d873d	210	read_transfer, sim_core_unaligned_signal);
63be8feb AC	211	val = T2H_M(val);
	212	PROFILE_COUNT_CORE (cpu, addr, N, map);
	213	if (TRACE_P (cpu, TRACE_CORE_IDX))
	214	sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
7a418800 AC	215	return val;
	216	}
	217	case FORCED_ALIGNMENT:
	218	return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
	219	case MIXED_ALIGNMENT:
cd0d873d AC	220	sim_engine_abort (CPU_STATE (cpu), cpu, cia,
	221	"internal error - %s - mixed alignment",
	222	XSTRING (sim_core_read_unaligned_N));
7a418800	223	default:
cd0d873d AC	224	sim_engine_abort (CPU_STATE (cpu), cpu, cia,
	225	"internal error - %s - bad switch",
	226	XSTRING (sim_core_read_unaligned_N));
89d09738	227	/* to keep some compilers happy, we return a dummy */
36dbc8bb	228	return sim_core_dummy_M;
7a418800 AC	229	}
7a418800 AC	230	}
63be8feb AC	231	#endif
	232
	233	/* TAGS: sim_core_read_misaligned_3 sim_core_read_misaligned_5 */
	234	/* TAGS: sim_core_read_misaligned_6 sim_core_read_misaligned_7 */
	235
	236	#if (M != N)
	237	INLINE_SIM_CORE(unsigned_M)
	238	sim_core_read_misaligned_N(sim_cpu *cpu,
	239	sim_cia cia,
	240	sim_core_maps map,
	241	address_word addr)
	242	{
	243	unsigned_M val = 0;
	244	if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N)
	245	SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
	246	read_transfer, sim_core_unaligned_signal);
	247	if (CURRENT_HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER)
	248	val = SWAP_M (val);
	249	if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
	250	val >>= (M - N) * 8;
	251	PROFILE_COUNT_CORE (cpu, addr, N, map);
	252	if (TRACE_P (cpu, TRACE_CORE_IDX))
	253	sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
	254	return val;
	255	}
	256	#endif
7a418800	257
74db699d DE	258	/* TAGS: sim_core_write_aligned_1 sim_core_write_aligned_2 */
74db699d DE	259	/* TAGS: sim_core_write_aligned_4 sim_core_write_aligned_8 */
63be8feb	260	/* TAGS: sim_core_write_aligned_16 */
a1dc3945	261
63be8feb	262	#if (M == N)
a1dc3945	263	INLINE_SIM_CORE(void)
7a418800 AC	264	sim_core_write_aligned_N(sim_cpu *cpu,
	265	sim_cia cia,
	266	sim_core_maps map,
1b217de0	267	address_word xaddr,
63be8feb	268	unsigned_M val)
a1dc3945	269	{
cd0d873d	270	sim_cpu_core *cpu_core = CPU_CORE (cpu);
2f2e6c5d	271	sim_core_common *core = &cpu_core->common;
cd0d873d AC	272	sim_core_mapping *mapping;
cd0d873d AC	273	address_word addr;
1b217de0	274	#if WITH_XOR_ENDIAN != 0
cd0d873d	275	if (WITH_XOR_ENDIAN)
63be8feb	276	addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN];
cd0d873d	277	else
1b217de0	278	#endif
cd0d873d	279	addr = xaddr;
63be8feb	280	mapping = sim_core_find_mapping (core, map, addr, N, write_transfer, 1 /abort/, cpu, cia);
a1dc3945 AC	281	#if (WITH_DEVICES)
a1dc3945 AC	282	if (WITH_CALLBACK_MEMORY && mapping->device != NULL) {
63be8feb AC	283	unsigned_M data = H2T_M (val);
63be8feb AC	284	if (device_io_write_buffer (mapping->device, &data, mapping->space, addr, N, cpu, cia) != N)
cd0d873d AC	285	device_error (mapping->device, "internal error - %s - io_write_buffer should not fail",
cd0d873d AC	286	XSTRING (sim_core_write_aligned_N));
a1dc3945 AC	287	}
	288	else
	289	#endif
63be8feb AC	290	(unsigned_M) sim_core_translate (mapping, addr) = H2T_M (val);
63be8feb AC	291	PROFILE_COUNT_CORE (cpu, addr, N, map);
7a418800	292	if (TRACE_P (cpu, TRACE_CORE_IDX))
63be8feb	293	sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
a1dc3945	294	}
63be8feb	295	#endif
a1dc3945	296
74db699d DE	297	/* TAGS: sim_core_write_unaligned_1 sim_core_write_unaligned_2 */
74db699d DE	298	/* TAGS: sim_core_write_unaligned_4 sim_core_write_unaligned_8 */
63be8feb	299	/* TAGS: sim_core_write_unaligned_16 */
a1dc3945	300
63be8feb	301	#if (M == N && N > 1)
7a418800 AC	302	INLINE_SIM_CORE(void)
	303	sim_core_write_unaligned_N(sim_cpu *cpu,
	304	sim_cia cia,
	305	sim_core_maps map,
cd0d873d	306	address_word addr,
63be8feb	307	unsigned_M val)
7a418800	308	{
63be8feb	309	int alignment = N - 1;
7a418800 AC	310	/* if hardwired to forced alignment just do it */
	311	if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
	312	sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
	313	else if ((addr & alignment) == 0)
	314	sim_core_write_aligned_N (cpu, cia, map, addr, val);
	315	else
	316	switch (CURRENT_ALIGNMENT)
	317	{
	318	case STRICT_ALIGNMENT:
63be8feb	319	SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
cd0d873d	320	write_transfer, sim_core_unaligned_signal);
7a418800 AC	321	break;
	322	case NONSTRICT_ALIGNMENT:
	323	{
63be8feb AC	324	unsigned_M data = H2T_M (val);
	325	if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N)
	326	SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
cd0d873d	327	write_transfer, sim_core_unaligned_signal);
63be8feb AC	328	PROFILE_COUNT_CORE (cpu, addr, N, map);
	329	if (TRACE_P (cpu, TRACE_CORE_IDX))
	330	sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
7a418800 AC	331	break;
	332	}
	333	case FORCED_ALIGNMENT:
	334	sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
74db699d	335	break;
7a418800	336	case MIXED_ALIGNMENT:
cd0d873d AC	337	sim_engine_abort (CPU_STATE (cpu), cpu, cia,
	338	"internal error - %s - mixed alignment",
	339	XSTRING (sim_core_write_unaligned_N));
7a418800 AC	340	break;
7a418800 AC	341	default:
cd0d873d AC	342	sim_engine_abort (CPU_STATE (cpu), cpu, cia,
	343	"internal error - %s - bad switch",
	344	XSTRING (sim_core_write_unaligned_N));
7a418800 AC	345	break;
	346	}
	347	}
63be8feb AC	348	#endif
	349
	350	/* TAGS: sim_core_write_misaligned_3 sim_core_write_misaligned_5 */
	351	/* TAGS: sim_core_write_misaligned_6 sim_core_write_misaligned_7 */
	352
	353	#if (M != N)
	354	INLINE_SIM_CORE(void)
	355	sim_core_write_misaligned_N(sim_cpu *cpu,
	356	sim_cia cia,
	357	sim_core_maps map,
	358	address_word addr,
	359	unsigned_M val)
	360	{
	361	unsigned_M data = val;
	362	if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
	363	data <<= (M - N) * 8;
	364	if (CURRENT_HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER)
	365	data = SWAP_M (data);
	366	if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N)
	367	SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
	368	write_transfer, sim_core_unaligned_signal);
	369	PROFILE_COUNT_CORE (cpu, addr, N, map);
	370	if (TRACE_P (cpu, TRACE_CORE_IDX))
	371	sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
	372	}
	373	#endif
7a418800 AC	374
7a418800 AC	375
a1dc3945	376	/* NOTE: see start of file for #define of these macros */
63be8feb AC	377	#undef unsigned_M
	378	#undef T2H_M
	379	#undef H2T_M
	380	#undef SWAP_M
7a418800	381	#undef sim_core_read_aligned_N
7a418800	382	#undef sim_core_read_unaligned_N
63be8feb AC	383	#undef sim_core_read_misaligned_N
63be8feb AC	384	#undef sim_core_write_aligned_N
7a418800	385	#undef sim_core_write_unaligned_N
63be8feb AC	386	#undef sim_core_write_misaligned_N
63be8feb AC	387	#undef sim_core_trace_M
36dbc8bb	388	#undef sim_core_dummy_M
63be8feb AC	389	#undef M
63be8feb AC	390	#undef N