Commit | Line | Data |
---|---|---|
fee8ec00 SR |
1 | /* Simulation code for the CR16 processor. |
2 | Copyright (C) 2008 Free Software Foundation, Inc. | |
3 | Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com> | |
4 | ||
5 | This file is part of GDB, the GNU debugger. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License along | |
18 | with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | ||
21 | #include "config.h" | |
22 | ||
23 | #include <signal.h> | |
24 | #include <errno.h> | |
25 | #include <sys/types.h> | |
26 | #include <sys/stat.h> | |
27 | #ifdef HAVE_UNISTD_H | |
28 | #include <unistd.h> | |
29 | #endif | |
30 | #ifdef HAVE_STRING_H | |
31 | #include <string.h> | |
32 | #endif | |
33 | ||
34 | #include "cr16_sim.h" | |
35 | #include "simops.h" | |
36 | #include "targ-vals.h" | |
37 | ||
38 | extern char *strrchr (); | |
39 | ||
40 | enum op_types { | |
41 | OP_VOID, | |
42 | OP_CONSTANT3, | |
43 | OP_CONSTANT3_OUTPUT, | |
44 | OP_UCONSTANT3, | |
45 | OP_UCONSTANT3_OUTPUT, | |
46 | OP_UCONSTANT3_1, | |
47 | OP_UCONSTANT3_1_OUTPUT, | |
48 | OP_CONSTANT4, | |
49 | OP_CONSTANT4_OUTPUT, | |
50 | OP_CONSTANT4_1, | |
51 | OP_CONSTANT4_1_OUTPUT, | |
52 | OP_CONSTANT5, | |
53 | OP_CONSTANT5_OUTPUT, | |
54 | OP_CONSTANT6, | |
55 | OP_CONSTANT6_OUTPUT, | |
56 | OP_CONSTANT16, | |
57 | OP_CONSTANT16_OUTPUT, | |
58 | OP_UCONSTANT16, | |
59 | OP_UCONSTANT16_OUTPUT, | |
60 | OP_CONSTANT20, | |
61 | OP_CONSTANT20_OUTPUT, | |
62 | OP_UCONSTANT20, | |
63 | OP_UCONSTANT20_OUTPUT, | |
64 | OP_CONSTANT32, | |
65 | OP_UCONSTANT32_OUTPUT, | |
66 | OP_UCONSTANT32, | |
67 | OP_CONSTANT32_OUTPUT, | |
68 | OP_MEMREF, | |
69 | OP_MEMREF2, | |
70 | OP_MEMREF3, | |
71 | ||
72 | OP_DISP5, | |
73 | OP_DISP5_OUTPUT, | |
74 | OP_DISP17, | |
75 | OP_DISP17_OUTPUT, | |
76 | OP_DISP25, | |
77 | OP_DISP25_OUTPUT, | |
78 | OP_DISPE9, | |
79 | OP_DISPE9_OUTPUT, | |
80 | //OP_ABS20, | |
81 | OP_ABS20_OUTPUT, | |
82 | //OP_ABS24, | |
83 | OP_ABS24_OUTPUT, | |
84 | ||
85 | OP_R_BASE_DISPS16, | |
86 | OP_R_BASE_DISPS16_OUTPUT, | |
87 | OP_R_BASE_DISP20, | |
88 | OP_R_BASE_DISP20_OUTPUT, | |
89 | OP_R_BASE_DISPS20, | |
90 | OP_R_BASE_DISPS20_OUTPUT, | |
91 | OP_R_BASE_DISPE20, | |
92 | OP_R_BASE_DISPE20_OUTPUT, | |
93 | ||
94 | OP_RP_BASE_DISPE0, | |
95 | OP_RP_BASE_DISPE0_OUTPUT, | |
96 | OP_RP_BASE_DISP4, | |
97 | OP_RP_BASE_DISP4_OUTPUT, | |
98 | OP_RP_BASE_DISPE4, | |
99 | OP_RP_BASE_DISPE4_OUTPUT, | |
100 | OP_RP_BASE_DISP14, | |
101 | OP_RP_BASE_DISP14_OUTPUT, | |
102 | OP_RP_BASE_DISP16, | |
103 | OP_RP_BASE_DISP16_OUTPUT, | |
104 | OP_RP_BASE_DISP20, | |
105 | OP_RP_BASE_DISP20_OUTPUT, | |
106 | OP_RP_BASE_DISPS20, | |
107 | OP_RP_BASE_DISPS20_OUTPUT, | |
108 | OP_RP_BASE_DISPE20, | |
109 | OP_RP_BASE_DISPE20_OUTPUT, | |
110 | ||
111 | OP_R_INDEX7_ABS20, | |
112 | OP_R_INDEX7_ABS20_OUTPUT, | |
113 | OP_R_INDEX8_ABS20, | |
114 | OP_R_INDEX8_ABS20_OUTPUT, | |
115 | ||
116 | OP_RP_INDEX_DISP0, | |
117 | OP_RP_INDEX_DISP0_OUTPUT, | |
118 | OP_RP_INDEX_DISP14, | |
119 | OP_RP_INDEX_DISP14_OUTPUT, | |
120 | OP_RP_INDEX_DISP20, | |
121 | OP_RP_INDEX_DISP20_OUTPUT, | |
122 | OP_RP_INDEX_DISPS20, | |
123 | OP_RP_INDEX_DISPS20_OUTPUT, | |
124 | ||
125 | OP_REG, | |
126 | OP_REG_OUTPUT, | |
127 | OP_REGP, | |
128 | OP_REGP_OUTPUT, | |
129 | OP_PROC_REG, | |
130 | OP_PROC_REG_OUTPUT, | |
131 | OP_PROC_REGP, | |
132 | OP_PROC_REGP_OUTPUT, | |
133 | OP_COND, | |
134 | OP_COND_OUTPUT, | |
135 | OP_RA, | |
136 | OP_RA_OUTPUT | |
137 | }; | |
138 | ||
139 | ||
140 | enum { | |
141 | PSR_MASK = (PSR_I_BIT | |
142 | | PSR_P_BIT | |
143 | | PSR_E_BIT | |
144 | | PSR_N_BIT | |
145 | | PSR_Z_BIT | |
146 | | PSR_F_BIT | |
147 | | PSR_U_BIT | |
148 | | PSR_L_BIT | |
149 | | PSR_T_BIT | |
150 | | PSR_C_BIT), | |
151 | /* The following bits in the PSR _can't_ be set by instructions such | |
152 | as mvtc. */ | |
153 | PSR_HW_MASK = (PSR_MASK) | |
154 | }; | |
155 | ||
156 | /* cond Code Condition True State | |
157 | * EQ Equal Z flag is 1 | |
158 | * NE Not Equal Z flag is 0 | |
159 | * CS Carry Set C flag is 1 | |
160 | * CC Carry Clear C flag is 0 | |
161 | * HI Higher L flag is 1 | |
162 | * LS Lower or Same L flag is 0 | |
163 | * GT Greater Than N flag is 1 | |
164 | * LE Less Than or Equal To N flag is 0 | |
165 | * FS Flag Set F flag is 1 | |
166 | * FC Flag Clear F flag is 0 | |
167 | * LO Lower Z and L flags are 0 | |
168 | * HS Higher or Same Z or L flag is 1 | |
169 | * LT Less Than Z and N flags are 0 | |
170 | * GE Greater Than or Equal To Z or N flag is 1. */ | |
171 | ||
172 | int cond_stat(int cc) | |
173 | { | |
174 | switch (cc) | |
175 | { | |
176 | case 0: return PSR_Z; break; | |
177 | case 1: return !PSR_Z; break; | |
178 | case 2: return PSR_C; break; | |
179 | case 3: return !PSR_C; break; | |
180 | case 4: return PSR_L; break; | |
181 | case 5: return !PSR_L; break; | |
182 | case 6: return PSR_N; break; | |
183 | case 7: return !PSR_N; break; | |
184 | case 8: return PSR_F; break; | |
185 | case 9: return !PSR_F; break; | |
186 | case 10: return !PSR_Z && !PSR_L; break; | |
187 | case 11: return PSR_Z || PSR_L; break; | |
188 | case 12: return !PSR_Z && !PSR_N; break; | |
189 | case 13: return PSR_Z || PSR_N; break; | |
190 | case 14: return 1; break; /*ALWAYS. */ | |
191 | default: | |
192 | // case NEVER: return false; break; | |
193 | //case NO_COND_CODE: | |
194 | //panic("Shouldn't have NO_COND_CODE in an actual instruction!"); | |
195 | return 0; break; | |
196 | } | |
197 | return 0; | |
198 | } | |
199 | ||
200 | ||
201 | creg_t | |
202 | move_to_cr (int cr, creg_t mask, creg_t val, int psw_hw_p) | |
203 | { | |
204 | /* A MASK bit is set when the corresponding bit in the CR should | |
205 | be left alone. */ | |
206 | /* This assumes that (VAL & MASK) == 0. */ | |
207 | switch (cr) | |
208 | { | |
209 | case PSR_CR: | |
210 | if (psw_hw_p) | |
211 | val &= PSR_HW_MASK; | |
212 | #if 0 | |
213 | else | |
214 | val &= PSR_MASK; | |
215 | (*cr16_callback->printf_filtered) | |
216 | (cr16_callback, | |
217 | "ERROR at PC 0x%x: ST can only be set when FX is set.\n", PC); | |
218 | State.exception = SIGILL; | |
219 | #endif | |
220 | /* keep an up-to-date psw around for tracing. */ | |
221 | State.trace.psw = (State.trace.psw & mask) | val; | |
222 | break; | |
223 | default: | |
224 | break; | |
225 | } | |
226 | /* only issue an update if the register is being changed. */ | |
227 | if ((State.cregs[cr] & ~mask) != val) | |
228 | SLOT_PEND_MASK (State.cregs[cr], mask, val); | |
229 | return val; | |
230 | } | |
231 | ||
232 | #ifdef DEBUG | |
233 | static void trace_input_func PARAMS ((char *name, | |
234 | enum op_types in1, | |
235 | enum op_types in2, | |
236 | enum op_types in3)); | |
237 | ||
238 | #define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (name, in1, in2, in3); } while (0) | |
239 | ||
240 | #ifndef SIZE_INSTRUCTION | |
241 | #define SIZE_INSTRUCTION 8 | |
242 | #endif | |
243 | ||
244 | #ifndef SIZE_OPERANDS | |
245 | #define SIZE_OPERANDS 18 | |
246 | #endif | |
247 | ||
248 | #ifndef SIZE_VALUES | |
249 | #define SIZE_VALUES 13 | |
250 | #endif | |
251 | ||
252 | #ifndef SIZE_LOCATION | |
253 | #define SIZE_LOCATION 20 | |
254 | #endif | |
255 | ||
256 | #ifndef SIZE_PC | |
257 | #define SIZE_PC 4 | |
258 | #endif | |
259 | ||
260 | #ifndef SIZE_LINE_NUMBER | |
261 | #define SIZE_LINE_NUMBER 2 | |
262 | #endif | |
263 | ||
264 | static void | |
265 | trace_input_func (name, in1, in2, in3) | |
266 | char *name; | |
267 | enum op_types in1; | |
268 | enum op_types in2; | |
269 | enum op_types in3; | |
270 | { | |
271 | char *comma; | |
272 | enum op_types in[3]; | |
273 | int i; | |
274 | char buf[1024]; | |
275 | char *p; | |
276 | long tmp; | |
277 | char *type; | |
278 | const char *filename; | |
279 | const char *functionname; | |
280 | unsigned int linenumber; | |
281 | bfd_vma byte_pc; | |
282 | ||
283 | if ((cr16_debug & DEBUG_TRACE) == 0) | |
284 | return; | |
285 | ||
286 | switch (State.ins_type) | |
287 | { | |
288 | default: | |
289 | case INS_UNKNOWN: type = " ?"; break; | |
290 | } | |
291 | ||
292 | if ((cr16_debug & DEBUG_LINE_NUMBER) == 0) | |
293 | (*cr16_callback->printf_filtered) (cr16_callback, | |
294 | "0x%.*x %s: %-*s ", | |
295 | SIZE_PC, (unsigned)PC, | |
296 | type, | |
297 | SIZE_INSTRUCTION, name); | |
298 | ||
299 | else | |
300 | { | |
301 | buf[0] = '\0'; | |
302 | byte_pc = decode_pc (); | |
303 | if (text && byte_pc >= text_start && byte_pc < text_end) | |
304 | { | |
305 | filename = (const char *)0; | |
306 | functionname = (const char *)0; | |
307 | linenumber = 0; | |
308 | if (bfd_find_nearest_line (prog_bfd, text, (struct bfd_symbol **)0, byte_pc - text_start, | |
309 | &filename, &functionname, &linenumber)) | |
310 | { | |
311 | p = buf; | |
312 | if (linenumber) | |
313 | { | |
314 | sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber); | |
315 | p += strlen (p); | |
316 | } | |
317 | else | |
318 | { | |
319 | sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---"); | |
320 | p += SIZE_LINE_NUMBER+2; | |
321 | } | |
322 | ||
323 | if (functionname) | |
324 | { | |
325 | sprintf (p, "%s ", functionname); | |
326 | p += strlen (p); | |
327 | } | |
328 | else if (filename) | |
329 | { | |
330 | char *q = strrchr (filename, '/'); | |
331 | sprintf (p, "%s ", (q) ? q+1 : filename); | |
332 | p += strlen (p); | |
333 | } | |
334 | ||
335 | if (*p == ' ') | |
336 | *p = '\0'; | |
337 | } | |
338 | } | |
339 | ||
340 | (*cr16_callback->printf_filtered) (cr16_callback, | |
341 | "0x%.*x %s: %-*.*s %-*s ", | |
342 | SIZE_PC, (unsigned)PC, | |
343 | type, | |
344 | SIZE_LOCATION, SIZE_LOCATION, buf, | |
345 | SIZE_INSTRUCTION, name); | |
346 | } | |
347 | ||
348 | in[0] = in1; | |
349 | in[1] = in2; | |
350 | in[2] = in3; | |
351 | comma = ""; | |
352 | p = buf; | |
353 | for (i = 0; i < 3; i++) | |
354 | { | |
355 | switch (in[i]) | |
356 | { | |
357 | case OP_VOID: | |
358 | break; | |
359 | ||
360 | case OP_REG: | |
361 | case OP_REG_OUTPUT: | |
362 | case OP_REGP: | |
363 | case OP_REGP_OUTPUT: | |
364 | sprintf (p, "%sr%d", comma, OP[i]); | |
365 | p += strlen (p); | |
366 | comma = ","; | |
367 | break; | |
368 | ||
369 | case OP_PROC_REG: | |
370 | case OP_PROC_REG_OUTPUT: | |
371 | sprintf (p, "%scr%d", comma, OP[i]); | |
372 | p += strlen (p); | |
373 | comma = ","; | |
374 | break; | |
375 | ||
376 | case OP_CONSTANT16: | |
377 | sprintf (p, "%s%d", comma, OP[i]); | |
378 | p += strlen (p); | |
379 | comma = ","; | |
380 | break; | |
381 | ||
382 | case OP_CONSTANT4: | |
383 | sprintf (p, "%s%d", comma, SEXT4(OP[i])); | |
384 | p += strlen (p); | |
385 | comma = ","; | |
386 | break; | |
387 | ||
388 | case OP_CONSTANT3: | |
389 | sprintf (p, "%s%d", comma, SEXT3(OP[i])); | |
390 | p += strlen (p); | |
391 | comma = ","; | |
392 | break; | |
393 | ||
394 | case OP_MEMREF: | |
395 | sprintf (p, "%s@r%d", comma, OP[i]); | |
396 | p += strlen (p); | |
397 | comma = ","; | |
398 | break; | |
399 | ||
400 | case OP_MEMREF2: | |
401 | sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]); | |
402 | p += strlen (p); | |
403 | comma = ","; | |
404 | break; | |
405 | ||
406 | case OP_MEMREF3: | |
407 | sprintf (p, "%s@%d", comma, OP[i]); | |
408 | p += strlen (p); | |
409 | comma = ","; | |
410 | break; | |
411 | } | |
412 | } | |
413 | ||
414 | if ((cr16_debug & DEBUG_VALUES) == 0) | |
415 | { | |
416 | *p++ = '\n'; | |
417 | *p = '\0'; | |
418 | (*cr16_callback->printf_filtered) (cr16_callback, "%s", buf); | |
419 | } | |
420 | else | |
421 | { | |
422 | *p = '\0'; | |
423 | (*cr16_callback->printf_filtered) (cr16_callback, "%-*s", SIZE_OPERANDS, buf); | |
424 | ||
425 | p = buf; | |
426 | for (i = 0; i < 3; i++) | |
427 | { | |
428 | buf[0] = '\0'; | |
429 | switch (in[i]) | |
430 | { | |
431 | case OP_VOID: | |
432 | (*cr16_callback->printf_filtered) (cr16_callback, "%*s", SIZE_VALUES, ""); | |
433 | break; | |
434 | ||
435 | case OP_REG_OUTPUT: | |
436 | case OP_REGP_OUTPUT: | |
437 | case OP_PROC_REG_OUTPUT: | |
438 | (*cr16_callback->printf_filtered) (cr16_callback, "%*s", SIZE_VALUES, "---"); | |
439 | break; | |
440 | ||
441 | case OP_REG: | |
442 | (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
443 | (uint16) GPR (OP[i])); | |
444 | break; | |
445 | ||
446 | case OP_REGP: | |
447 | tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1))); | |
448 | (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp); | |
449 | break; | |
450 | ||
451 | case OP_PROC_REG: | |
452 | (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
453 | (uint16) CREG (OP[i])); | |
454 | break; | |
455 | ||
456 | case OP_CONSTANT16: | |
457 | (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
458 | (uint16)OP[i]); | |
459 | break; | |
460 | ||
461 | case OP_CONSTANT4: | |
462 | (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
463 | (uint16)SEXT4(OP[i])); | |
464 | break; | |
465 | ||
466 | case OP_CONSTANT3: | |
467 | (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
468 | (uint16)SEXT3(OP[i])); | |
469 | break; | |
470 | ||
471 | case OP_MEMREF2: | |
472 | (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
473 | (uint16)OP[i]); | |
474 | (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
475 | (uint16)GPR (OP[i + 1])); | |
476 | i++; | |
477 | break; | |
478 | } | |
479 | } | |
480 | } | |
481 | ||
482 | (*cr16_callback->flush_stdout) (cr16_callback); | |
483 | } | |
484 | ||
485 | static void | |
486 | do_trace_output_flush (void) | |
487 | { | |
488 | (*cr16_callback->flush_stdout) (cr16_callback); | |
489 | } | |
490 | ||
491 | static void | |
492 | do_trace_output_finish (void) | |
493 | { | |
494 | (*cr16_callback->printf_filtered) (cr16_callback, | |
495 | " F0=%d F1=%d C=%d\n", | |
496 | (State.trace.psw & PSR_F_BIT) != 0, | |
497 | (State.trace.psw & PSR_F_BIT) != 0, | |
498 | (State.trace.psw & PSR_C_BIT) != 0); | |
499 | (*cr16_callback->flush_stdout) (cr16_callback); | |
500 | } | |
501 | ||
502 | static void | |
503 | trace_output_40 (uint64 val) | |
504 | { | |
505 | if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) | |
506 | { | |
507 | (*cr16_callback->printf_filtered) (cr16_callback, | |
508 | " :: %*s0x%.2x%.8lx", | |
509 | SIZE_VALUES - 12, | |
510 | "", | |
511 | ((int)(val >> 32) & 0xff), | |
512 | ((unsigned long) val) & 0xffffffff); | |
513 | do_trace_output_finish (); | |
514 | } | |
515 | } | |
516 | ||
517 | static void | |
518 | trace_output_32 (uint32 val) | |
519 | { | |
520 | if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) | |
521 | { | |
522 | (*cr16_callback->printf_filtered) (cr16_callback, | |
523 | " :: %*s0x%.8x", | |
524 | SIZE_VALUES - 10, | |
525 | "", | |
526 | (int) val); | |
527 | do_trace_output_finish (); | |
528 | } | |
529 | } | |
530 | ||
531 | static void | |
532 | trace_output_16 (uint16 val) | |
533 | { | |
534 | if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) | |
535 | { | |
536 | (*cr16_callback->printf_filtered) (cr16_callback, | |
537 | " :: %*s0x%.4x", | |
538 | SIZE_VALUES - 6, | |
539 | "", | |
540 | (int) val); | |
541 | do_trace_output_finish (); | |
542 | } | |
543 | } | |
544 | ||
545 | static void | |
546 | trace_output_void () | |
547 | { | |
548 | if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) | |
549 | { | |
550 | (*cr16_callback->printf_filtered) (cr16_callback, "\n"); | |
551 | do_trace_output_flush (); | |
552 | } | |
553 | } | |
554 | ||
555 | static void | |
556 | trace_output_flag () | |
557 | { | |
558 | if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) | |
559 | { | |
560 | (*cr16_callback->printf_filtered) (cr16_callback, | |
561 | " :: %*s", | |
562 | SIZE_VALUES, | |
563 | ""); | |
564 | do_trace_output_finish (); | |
565 | } | |
566 | } | |
567 | ||
568 | ||
569 | ||
570 | ||
571 | #else | |
572 | #define trace_input(NAME, IN1, IN2, IN3) | |
573 | #define trace_output(RESULT) | |
574 | #endif | |
575 | ||
576 | /* addub. */ | |
577 | void | |
578 | OP_2C_8 () | |
579 | { | |
580 | uint8 tmp; | |
581 | uint8 a = OP[0] & 0xff; | |
582 | uint16 b = (GPR (OP[1])) & 0xff; | |
583 | trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID); | |
584 | tmp = (a + b) & 0xff; | |
585 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
586 | trace_output_16 (tmp); | |
587 | } | |
588 | ||
589 | /* addub. */ | |
590 | void | |
591 | OP_2CB_C () | |
592 | { | |
593 | uint16 tmp; | |
594 | uint8 a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff; | |
595 | trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID); | |
596 | tmp = (a + b) & 0xff; | |
597 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
598 | trace_output_16 (tmp); | |
599 | } | |
600 | ||
601 | /* addub. */ | |
602 | void | |
603 | OP_2D_8 () | |
604 | { | |
605 | uint8 a = (GPR (OP[0])) & 0xff; | |
606 | uint8 b = (GPR (OP[1])) & 0xff; | |
607 | uint16 tmp = (a + b) & 0xff; | |
608 | trace_input ("addub", OP_REG, OP_REG, OP_VOID); | |
609 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
610 | trace_output_16 (tmp); | |
611 | } | |
612 | ||
613 | /* adduw. */ | |
614 | void | |
615 | OP_2E_8 () | |
616 | { | |
617 | uint16 a = OP[0]; | |
618 | uint16 b = GPR (OP[1]); | |
619 | uint16 tmp = (a + b); | |
620 | trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID); | |
621 | SET_GPR (OP[1], tmp); | |
622 | trace_output_16 (tmp); | |
623 | } | |
624 | ||
625 | /* adduw. */ | |
626 | void | |
627 | OP_2EB_C () | |
628 | { | |
629 | uint16 a = OP[0]; | |
630 | uint16 b = GPR (OP[1]); | |
631 | uint16 tmp = (a + b); | |
632 | trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID); | |
633 | SET_GPR (OP[1], tmp); | |
634 | trace_output_16 (tmp); | |
635 | } | |
636 | ||
637 | /* adduw. */ | |
638 | void | |
639 | OP_2F_8 () | |
640 | { | |
641 | uint16 a = GPR (OP[0]); | |
642 | uint16 b = GPR (OP[1]); | |
643 | uint16 tmp = (a + b); | |
644 | trace_input ("adduw", OP_REG, OP_REG, OP_VOID); | |
645 | SET_GPR (OP[1], tmp); | |
646 | trace_output_16 (tmp); | |
647 | } | |
648 | ||
649 | /* addb. */ | |
650 | void | |
651 | OP_30_8 () | |
652 | { | |
653 | uint8 a = OP[0]; | |
654 | uint8 b = (GPR (OP[1]) & 0xff); | |
655 | trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID); | |
656 | uint16 tmp = (a + b) & 0xff; | |
657 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
658 | SET_PSR_C (tmp > 0xFF); | |
659 | SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); | |
660 | trace_output_16 (tmp); | |
661 | } | |
662 | ||
663 | /* addb. */ | |
664 | void | |
665 | OP_30B_C () | |
666 | { | |
667 | uint8 a = (OP[0]) & 0xff; | |
668 | uint8 b = (GPR (OP[1]) & 0xff); | |
669 | trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID); | |
670 | uint16 tmp = (a + b) & 0xff; | |
671 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
672 | SET_PSR_C (tmp > 0xFF); | |
673 | SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); | |
674 | trace_output_16 (tmp); | |
675 | } | |
676 | ||
677 | /* addb. */ | |
678 | void | |
679 | OP_31_8 () | |
680 | { | |
681 | uint8 a = (GPR (OP[0]) & 0xff); | |
682 | uint8 b = (GPR (OP[1]) & 0xff); | |
683 | trace_input ("addb", OP_REG, OP_REG, OP_VOID); | |
684 | uint16 tmp = (a + b) & 0xff; | |
685 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
686 | SET_PSR_C (tmp > 0xFF); | |
687 | SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); | |
688 | trace_output_16 (tmp); | |
689 | } | |
690 | ||
691 | /* addw. */ | |
692 | void | |
693 | OP_32_8 () | |
694 | { | |
695 | int16 a = OP[0]; | |
696 | uint16 tmp, b = GPR (OP[1]); | |
697 | trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID); | |
698 | tmp = (a + b); | |
699 | SET_GPR (OP[1], tmp); | |
700 | SET_PSR_C (tmp > 0xFFFF); | |
701 | SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); | |
702 | trace_output_16 (tmp); | |
703 | } | |
704 | ||
705 | /* addw. */ | |
706 | void | |
707 | OP_32B_C () | |
708 | { | |
709 | int16 a = OP[0]; | |
710 | uint16 tmp, b = GPR (OP[1]); | |
711 | tmp = (a + b); | |
712 | trace_input ("addw", OP_CONSTANT16, OP_REG, OP_VOID); | |
713 | SET_GPR (OP[1], tmp); | |
714 | SET_PSR_C (tmp > 0xFFFF); | |
715 | SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); | |
716 | trace_output_16 (tmp); | |
717 | } | |
718 | ||
719 | /* addw. */ | |
720 | void | |
721 | OP_33_8 () | |
722 | { | |
723 | uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1])); | |
724 | trace_input ("addw", OP_REG, OP_REG, OP_VOID); | |
725 | tmp = (a + b); | |
726 | SET_GPR (OP[1], tmp); | |
727 | SET_PSR_C (tmp > 0xFFFF); | |
728 | SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); | |
729 | trace_output_16 (tmp); | |
730 | } | |
731 | ||
732 | /* addcb. */ | |
733 | void | |
734 | OP_34_8 () | |
735 | { | |
736 | uint8 tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff; | |
737 | trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG); | |
738 | tmp = (a + b + PSR_C) & 0xff; | |
739 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
740 | SET_PSR_C (tmp > 0xFF); | |
741 | SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); | |
742 | trace_output_16 (tmp); | |
743 | } | |
744 | ||
745 | /* addcb. */ | |
746 | void | |
747 | OP_34B_C () | |
748 | { | |
749 | int8 a = OP[0] & 0xff; | |
750 | uint8 b = (GPR (OP[1])) & 0xff; | |
751 | trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID); | |
752 | uint8 tmp = (a + b + PSR_C) & 0xff; | |
753 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
754 | SET_PSR_C (tmp > 0xFF); | |
755 | SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); | |
756 | trace_output_16 (tmp); | |
757 | } | |
758 | ||
759 | /* addcb. */ | |
760 | void | |
761 | OP_35_8 () | |
762 | { | |
763 | uint8 a = (GPR (OP[0])) & 0xff; | |
764 | uint8 b = (GPR (OP[1])) & 0xff; | |
765 | trace_input ("addcb", OP_REG, OP_REG, OP_VOID); | |
766 | uint8 tmp = (a + b + PSR_C) & 0xff; | |
767 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
768 | SET_PSR_C (tmp > 0xFF); | |
769 | SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); | |
770 | trace_output_16 (tmp); | |
771 | } | |
772 | ||
773 | /* addcw. */ | |
774 | void | |
775 | OP_36_8 () | |
776 | { | |
777 | uint16 a = OP[0]; | |
778 | uint16 b = GPR (OP[1]); | |
779 | trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID); | |
780 | uint16 tmp = (a + b + PSR_C); | |
781 | SET_GPR (OP[1], tmp); | |
782 | SET_PSR_C (tmp > 0xFFFF); | |
783 | SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); | |
784 | trace_output_16 (tmp); | |
785 | } | |
786 | ||
787 | /* addcw. */ | |
788 | void | |
789 | OP_36B_C () | |
790 | { | |
791 | int16 a = OP[0]; | |
792 | uint16 b = GPR (OP[1]); | |
793 | trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID); | |
794 | uint16 tmp = (a + b + PSR_C); | |
795 | SET_GPR (OP[1], tmp); | |
796 | SET_PSR_C (tmp > 0xFFFF); | |
797 | SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); | |
798 | trace_output_16 (tmp); | |
799 | } | |
800 | ||
801 | /* addcw. */ | |
802 | void | |
803 | OP_37_8 () | |
804 | { | |
805 | uint16 a = GPR (OP[1]); | |
806 | uint16 b = GPR (OP[1]); | |
807 | trace_input ("addcw", OP_REG, OP_REG, OP_VOID); | |
808 | uint16 tmp = (a + b + PSR_C); | |
809 | SET_GPR (OP[1], tmp); | |
810 | SET_PSR_C (tmp > 0xFFFF); | |
811 | SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); | |
812 | trace_output_16 (tmp); | |
813 | } | |
814 | ||
815 | /* addd. */ | |
816 | void | |
817 | OP_60_8 () | |
818 | { | |
819 | int16 a = (OP[0]); | |
820 | uint32 b = GPR32 (OP[1]); | |
821 | trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID); | |
822 | uint32 tmp = (a + b); | |
823 | SET_GPR32 (OP[1], tmp); | |
824 | SET_PSR_C (tmp > 0xFFFFFFFF); | |
825 | SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); | |
826 | trace_output_32 (tmp); | |
827 | } | |
828 | ||
829 | /* addd. */ | |
830 | void | |
831 | OP_60B_C () | |
832 | { | |
833 | int32 a = (SEXT16(OP[0])); | |
834 | uint32 b = GPR32 (OP[1]); | |
835 | trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID); | |
836 | uint32 tmp = (a + b); | |
837 | SET_GPR32 (OP[1], tmp); | |
838 | SET_PSR_C (tmp > 0xFFFFFFFF); | |
839 | SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); | |
840 | trace_output_32 (tmp); | |
841 | } | |
842 | ||
843 | /* addd. */ | |
844 | void | |
845 | OP_61_8 () | |
846 | { | |
847 | uint32 a = GPR32 (OP[0]); | |
848 | uint32 b = GPR32 (OP[1]); | |
849 | trace_input ("addd", OP_REGP, OP_REGP, OP_VOID); | |
850 | uint32 tmp = (a + b); | |
851 | SET_GPR32 (OP[1], tmp); | |
852 | trace_output_32 (tmp); | |
853 | SET_PSR_C (tmp > 0xFFFFFFFF); | |
854 | SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); | |
855 | } | |
856 | ||
857 | /* addd. */ | |
858 | void | |
859 | OP_4_8 () | |
860 | { | |
861 | uint32 a = OP[0]; | |
862 | uint32 b = GPR32 (OP[1]); | |
863 | uint32 tmp; | |
864 | trace_input ("addd", OP_CONSTANT20, OP_REGP, OP_VOID); | |
865 | tmp = (a + b); | |
866 | SET_GPR32 (OP[1], tmp); | |
867 | SET_PSR_C (tmp > 0xFFFFFFFF); | |
868 | SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); | |
869 | trace_output_32 (tmp); | |
870 | } | |
871 | ||
872 | /* addd. */ | |
873 | void | |
874 | OP_2_C () | |
875 | { | |
876 | int32 a = OP[0]; | |
877 | uint32 b = GPR32 (OP[1]); | |
878 | uint32 tmp; | |
879 | trace_input ("addd", OP_CONSTANT32, OP_REGP, OP_VOID); | |
880 | tmp = (a + b); | |
881 | SET_GPR32 (OP[1], tmp); | |
882 | SET_PSR_C (tmp > 0xFFFFFFFF); | |
883 | SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); | |
884 | trace_output_32 (tmp); | |
885 | } | |
886 | ||
887 | /* andb. */ | |
888 | void | |
889 | OP_20_8 () | |
890 | { | |
891 | uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; | |
892 | trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID); | |
893 | tmp = a & b; | |
894 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
895 | trace_output_16 (tmp); | |
896 | } | |
897 | ||
898 | /* andb. */ | |
899 | void | |
900 | OP_20B_C () | |
901 | { | |
902 | uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; | |
903 | trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID); | |
904 | tmp = a & b; | |
905 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
906 | trace_output_16 (tmp); | |
907 | } | |
908 | ||
909 | /* andb. */ | |
910 | void | |
911 | OP_21_8 () | |
912 | { | |
913 | uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; | |
914 | trace_input ("andb", OP_REG, OP_REG, OP_VOID); | |
915 | tmp = a & b; | |
916 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
917 | trace_output_16 (tmp); | |
918 | } | |
919 | ||
920 | /* andw. */ | |
921 | void | |
922 | OP_22_8 () | |
923 | { | |
924 | uint16 tmp, a = OP[0], b = GPR (OP[1]); | |
925 | trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID); | |
926 | tmp = a & b; | |
927 | SET_GPR (OP[1], tmp); | |
928 | trace_output_16 (tmp); | |
929 | } | |
930 | ||
931 | /* andw. */ | |
932 | void | |
933 | OP_22B_C () | |
934 | { | |
935 | uint16 tmp, a = OP[0], b = GPR (OP[1]); | |
936 | trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID); | |
937 | tmp = a & b; | |
938 | SET_GPR (OP[1], tmp); | |
939 | trace_output_16 (tmp); | |
940 | } | |
941 | ||
942 | /* andw. */ | |
943 | void | |
944 | OP_23_8 () | |
945 | { | |
946 | uint16 tmp, a = GPR (OP[0]), b = GPR (OP[1]); | |
947 | trace_input ("andw", OP_REG, OP_REG, OP_VOID); | |
948 | tmp = a & b; | |
949 | SET_GPR (OP[1], tmp); | |
950 | trace_output_16 (tmp); | |
951 | } | |
952 | ||
953 | /* andd. */ | |
954 | void | |
955 | OP_4_C () | |
956 | { | |
957 | uint32 tmp, a = OP[0], b = GPR32 (OP[1]); | |
958 | trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID); | |
959 | tmp = a & b; | |
960 | SET_GPR32 (OP[1], tmp); | |
961 | trace_output_32 (tmp); | |
962 | } | |
963 | ||
964 | /* andd. */ | |
965 | void | |
966 | OP_14B_14 () | |
967 | { | |
968 | uint32 tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1])); | |
969 | trace_input ("andd", OP_REGP, OP_REGP, OP_VOID); | |
970 | tmp = a & b; | |
971 | SET_GPR32 (OP[1], tmp); | |
972 | trace_output_32 (tmp); | |
973 | } | |
974 | ||
975 | /* ord. */ | |
976 | void | |
977 | OP_5_C () | |
978 | { | |
979 | uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]); | |
980 | trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID); | |
981 | tmp = a | b; | |
982 | SET_GPR32 (OP[1], tmp); | |
983 | trace_output_32 (tmp); | |
984 | } | |
985 | ||
986 | /* ord. */ | |
987 | void | |
988 | OP_149_14 () | |
989 | { | |
990 | uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]); | |
991 | trace_input ("ord", OP_REGP, OP_REGP, OP_VOID); | |
992 | tmp = a | b; | |
993 | SET_GPR32 (OP[1], tmp); | |
994 | trace_output_32 (tmp); | |
995 | } | |
996 | ||
997 | /* xord. */ | |
998 | void | |
999 | OP_6_C () | |
1000 | { | |
1001 | uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]); | |
1002 | trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID); | |
1003 | tmp = a ^ b; | |
1004 | SET_GPR32 (OP[1], tmp); | |
1005 | trace_output_32 (tmp); | |
1006 | } | |
1007 | ||
1008 | /* xord. */ | |
1009 | void | |
1010 | OP_14A_14 () | |
1011 | { | |
1012 | uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]); | |
1013 | trace_input ("xord", OP_REGP, OP_REGP, OP_VOID); | |
1014 | tmp = a ^ b; | |
1015 | SET_GPR32 (OP[1], tmp); | |
1016 | trace_output_32 (tmp); | |
1017 | } | |
1018 | ||
1019 | ||
1020 | /* b. */ | |
1021 | void | |
1022 | OP_1_4 () | |
1023 | { | |
1024 | uint32 tmp, cc = cond_stat (OP[0]); | |
1025 | trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID); | |
1026 | if (cc) | |
1027 | { | |
1028 | if (sign_flag) | |
1029 | tmp = (PC - (OP[1])); | |
1030 | else | |
1031 | tmp = (PC + (OP[1])); | |
1032 | /* If the resulting PC value is less than 0x00_0000 or greater | |
1033 | than 0xFF_FFFF, this instruction causes an IAD trap.*/ | |
1034 | ||
1035 | if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) | |
1036 | { | |
1037 | State.exception = SIG_CR16_BUS; | |
1038 | State.pc_changed = 1; /* Don't increment the PC. */ | |
1039 | trace_output_void (); | |
1040 | return; | |
1041 | } | |
1042 | else | |
1043 | JMP (tmp); | |
1044 | } | |
1045 | sign_flag = 0; /* Reset sign_flag. */ | |
1046 | trace_output_32 (tmp); | |
1047 | } | |
1048 | ||
1049 | /* b. */ | |
1050 | void | |
1051 | OP_18_8 () | |
1052 | { | |
1053 | uint32 tmp, cc = cond_stat (OP[0]); | |
1054 | trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID); | |
1055 | if (cc) | |
1056 | { | |
1057 | if (sign_flag) | |
1058 | tmp = (PC - OP[1]); | |
1059 | else | |
1060 | tmp = (PC + OP[1]); | |
1061 | /* If the resulting PC value is less than 0x00_0000 or greater | |
1062 | than 0xFF_FFFF, this instruction causes an IAD trap.*/ | |
1063 | ||
1064 | if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) | |
1065 | { | |
1066 | State.exception = SIG_CR16_BUS; | |
1067 | State.pc_changed = 1; /* Don't increment the PC. */ | |
1068 | trace_output_void (); | |
1069 | return; | |
1070 | } | |
1071 | else | |
1072 | JMP (tmp); | |
1073 | } | |
1074 | sign_flag = 0; /* Reset sign_flag. */ | |
1075 | trace_output_32 (tmp); | |
1076 | } | |
1077 | ||
1078 | /* b. */ | |
1079 | void | |
1080 | OP_10_10 () | |
1081 | { | |
1082 | uint32 tmp, cc = cond_stat (OP[0]); | |
1083 | trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID); | |
1084 | if (cc) | |
1085 | { | |
1086 | if (sign_flag) | |
1087 | tmp = (PC - (OP[1])); | |
1088 | else | |
1089 | tmp = (PC + (OP[1])); | |
1090 | /* If the resulting PC value is less than 0x00_0000 or greater | |
1091 | than 0xFF_FFFF, this instruction causes an IAD trap.*/ | |
1092 | ||
1093 | if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) | |
1094 | { | |
1095 | State.exception = SIG_CR16_BUS; | |
1096 | State.pc_changed = 1; /* Don't increment the PC. */ | |
1097 | trace_output_void (); | |
1098 | return; | |
1099 | } | |
1100 | else | |
1101 | JMP (tmp); | |
1102 | } | |
1103 | sign_flag = 0; /* Reset sign_flag. */ | |
1104 | trace_output_32 (tmp); | |
1105 | } | |
1106 | ||
1107 | /* bal. */ | |
1108 | void | |
1109 | OP_C0_8 () | |
1110 | { | |
1111 | uint32 tmp; | |
1112 | trace_input ("bal", OP_REG, OP_DISP17, OP_VOID); | |
1113 | tmp = ((PC + 4) >> 1); /* Store PC in RA register. */ | |
1114 | SET_GPR32 (14, tmp); | |
1115 | if (sign_flag) | |
1116 | tmp = (PC - (OP[1])); | |
1117 | else | |
1118 | tmp = (PC + (OP[1])); | |
1119 | ||
1120 | /* If the resulting PC value is less than 0x00_0000 or greater | |
1121 | than 0xFF_FFFF, this instruction causes an IAD trap. */ | |
1122 | ||
1123 | if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) | |
1124 | { | |
1125 | State.exception = SIG_CR16_BUS; | |
1126 | State.pc_changed = 1; /* Don't increment the PC. */ | |
1127 | trace_output_void (); | |
1128 | return; | |
1129 | } | |
1130 | else | |
1131 | JMP (tmp); | |
1132 | sign_flag = 0; /* Reset sign_flag. */ | |
1133 | trace_output_32 (tmp); | |
1134 | } | |
1135 | ||
1136 | ||
1137 | /* bal. */ | |
1138 | void | |
1139 | OP_102_14 () | |
1140 | { | |
1141 | uint32 tmp; | |
1142 | trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID); | |
1143 | tmp = (((PC) + 4) >> 1); /* Store PC in reg pair. */ | |
1144 | SET_GPR32 (OP[0], tmp); | |
1145 | if (sign_flag) | |
1146 | tmp = ((PC) - (OP[1])); | |
1147 | else | |
1148 | tmp = ((PC) + (OP[1])); | |
1149 | /* If the resulting PC value is less than 0x00_0000 or greater | |
1150 | than 0xFF_FFFF, this instruction causes an IAD trap.*/ | |
1151 | ||
1152 | if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) | |
1153 | { | |
1154 | State.exception = SIG_CR16_BUS; | |
1155 | State.pc_changed = 1; /* Don't increment the PC. */ | |
1156 | trace_output_void (); | |
1157 | return; | |
1158 | } | |
1159 | else | |
1160 | JMP (tmp); | |
1161 | sign_flag = 0; /* Reset sign_flag. */ | |
1162 | trace_output_32 (tmp); | |
1163 | } | |
1164 | ||
1165 | /* jal. */ | |
1166 | void | |
1167 | OP_148_14 () | |
1168 | { | |
1169 | uint32 tmp; | |
1170 | trace_input ("jal", OP_REGP, OP_REGP, OP_VOID); | |
1171 | SET_GPR32 (OP[0], (((PC) + 4) >> 1)); /* Store next PC in RA */ | |
1172 | tmp = GPR32 (OP[1]); | |
1173 | tmp = SEXT24(tmp << 1); | |
1174 | /* If the resulting PC value is less than 0x00_0000 or greater | |
1175 | than 0xFF_FFFF, this instruction causes an IAD trap.*/ | |
1176 | ||
1177 | if ((tmp < 0x0) || (tmp > 0xFFFFFF)) | |
1178 | { | |
1179 | State.exception = SIG_CR16_BUS; | |
1180 | State.pc_changed = 1; /* Don't increment the PC. */ | |
1181 | trace_output_void (); | |
1182 | return; | |
1183 | } | |
1184 | else | |
1185 | JMP (tmp); | |
1186 | ||
1187 | trace_output_32 (tmp); | |
1188 | } | |
1189 | ||
1190 | ||
1191 | /* jal. */ | |
1192 | void | |
1193 | OP_D_C () | |
1194 | { | |
1195 | uint32 tmp; | |
1196 | trace_input ("jal", OP_REGP, OP_VOID, OP_VOID); | |
1197 | SET_GPR32 (14, (((PC) + 2) >> 1)); /* Store next PC in RA */ | |
1198 | tmp = GPR32 (OP[0]); | |
1199 | tmp = SEXT24(tmp << 1); | |
1200 | /* If the resulting PC value is less than 0x00_0000 or greater | |
1201 | than 0xFF_FFFF, this instruction causes an IAD trap.*/ | |
1202 | ||
1203 | if ((tmp < 0x0) || (tmp > 0xFFFFFF)) | |
1204 | { | |
1205 | State.exception = SIG_CR16_BUS; | |
1206 | State.pc_changed = 1; /* Don't increment the PC. */ | |
1207 | trace_output_void (); | |
1208 | return; | |
1209 | } | |
1210 | else | |
1211 | JMP (tmp); | |
1212 | ||
1213 | trace_output_32 (tmp); | |
1214 | } | |
1215 | ||
1216 | ||
1217 | /* beq0b. */ | |
1218 | void | |
1219 | OP_C_8 () | |
1220 | { | |
1221 | uint32 addr; | |
1222 | uint8 a = (GPR (OP[0]) & 0xFF); | |
1223 | trace_input ("beq0b", OP_REG, OP_DISP5, OP_VOID); | |
1224 | addr = OP[1]; | |
1225 | if (a == 0) | |
1226 | { | |
1227 | if (sign_flag) | |
1228 | addr = (PC - OP[1]); | |
1229 | else | |
1230 | addr = (PC + OP[1]); | |
1231 | ||
1232 | JMP (addr); | |
1233 | } | |
1234 | sign_flag = 0; /* Reset sign_flag. */ | |
1235 | trace_output_void (); | |
1236 | } | |
1237 | ||
1238 | /* bne0b. */ | |
1239 | void | |
1240 | OP_D_8 () | |
1241 | { | |
1242 | uint32 addr; | |
1243 | uint8 a = (GPR (OP[0]) & 0xFF); | |
1244 | trace_input ("bne0b", OP_REG, OP_DISP5, OP_VOID); | |
1245 | addr = OP[1]; | |
1246 | if (a != 0) | |
1247 | { | |
1248 | if (sign_flag) | |
1249 | addr = (PC - OP[1]); | |
1250 | else | |
1251 | addr = (PC + OP[1]); | |
1252 | ||
1253 | JMP (addr); | |
1254 | } | |
1255 | sign_flag = 0; /* Reset sign_flag. */ | |
1256 | trace_output_void (); | |
1257 | } | |
1258 | ||
1259 | /* beq0w. */ | |
1260 | void | |
1261 | OP_E_8() | |
1262 | { | |
1263 | uint32 addr; | |
1264 | uint16 a = GPR (OP[0]); | |
1265 | trace_input ("beq0w", OP_REG, OP_DISP5, OP_VOID); | |
1266 | addr = OP[1]; | |
1267 | if (a == 0) | |
1268 | { | |
1269 | if (sign_flag) | |
1270 | addr = (PC - OP[1]); | |
1271 | else | |
1272 | addr = (PC + OP[1]); | |
1273 | ||
1274 | JMP (addr); | |
1275 | } | |
1276 | sign_flag = 0; /* Reset sign_flag. */ | |
1277 | trace_output_void (); | |
1278 | } | |
1279 | ||
1280 | /* bne0w. */ | |
1281 | void | |
1282 | OP_F_8 () | |
1283 | { | |
1284 | uint32 addr; | |
1285 | uint16 a = GPR (OP[0]); | |
1286 | trace_input ("bne0w", OP_REG, OP_DISP5, OP_VOID); | |
1287 | addr = OP[1]; | |
1288 | if (a != 0) | |
1289 | { | |
1290 | if (sign_flag) | |
1291 | addr = (PC - OP[1]); | |
1292 | else | |
1293 | addr = (PC + OP[1]); | |
1294 | ||
1295 | JMP (addr); | |
1296 | } | |
1297 | sign_flag = 0; /* Reset sign_flag. */ | |
1298 | trace_output_void (); | |
1299 | } | |
1300 | ||
1301 | ||
1302 | /* jeq. */ | |
1303 | void | |
1304 | OP_A0_C () | |
1305 | { | |
1306 | uint32 tmp; | |
1307 | trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID); | |
1308 | if ((PSR_Z) == 1) | |
1309 | { | |
1310 | tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */ | |
1311 | JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */ | |
1312 | } | |
1313 | trace_output_32 (tmp); | |
1314 | } | |
1315 | ||
1316 | /* jne. */ | |
1317 | void | |
1318 | OP_A1_C () | |
1319 | { | |
1320 | uint32 tmp; | |
1321 | trace_input ("jne", OP_REGP, OP_VOID, OP_VOID); | |
1322 | if ((PSR_Z) == 0) | |
1323 | { | |
1324 | tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */ | |
1325 | JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */ | |
1326 | } | |
1327 | trace_output_32 (tmp); | |
1328 | } | |
1329 | ||
1330 | /* jcs. */ | |
1331 | void | |
1332 | OP_A2_C () | |
1333 | { | |
1334 | uint32 tmp; | |
1335 | trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID); | |
1336 | if ((PSR_C) == 1) | |
1337 | { | |
1338 | tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ | |
1339 | JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ | |
1340 | } | |
1341 | trace_output_32 (tmp); | |
1342 | } | |
1343 | ||
1344 | /* jcc. */ | |
1345 | void | |
1346 | OP_A3_C () | |
1347 | { | |
1348 | uint32 tmp; | |
1349 | trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID); | |
1350 | if ((PSR_C) == 0) | |
1351 | { | |
1352 | tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ | |
1353 | JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ | |
1354 | } | |
1355 | trace_output_32 (tmp); | |
1356 | } | |
1357 | ||
1358 | /* jhi. */ | |
1359 | void | |
1360 | OP_A4_C () | |
1361 | { | |
1362 | uint32 tmp; | |
1363 | trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID); | |
1364 | if ((PSR_L) == 1) | |
1365 | { | |
1366 | tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ | |
1367 | JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ | |
1368 | } | |
1369 | trace_output_32 (tmp); | |
1370 | } | |
1371 | ||
1372 | /* jls. */ | |
1373 | void | |
1374 | OP_A5_C () | |
1375 | { | |
1376 | uint32 tmp; | |
1377 | trace_input ("jls", OP_REGP, OP_VOID, OP_VOID); | |
1378 | if ((PSR_L) == 0) | |
1379 | { | |
1380 | tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ | |
1381 | JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ | |
1382 | } | |
1383 | trace_output_32 (tmp); | |
1384 | } | |
1385 | ||
1386 | /* jgt. */ | |
1387 | void | |
1388 | OP_A6_C () | |
1389 | { | |
1390 | uint32 tmp; | |
1391 | trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID); | |
1392 | if ((PSR_N) == 1) | |
1393 | { | |
1394 | tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ | |
1395 | JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ | |
1396 | } | |
1397 | trace_output_32 (tmp); | |
1398 | } | |
1399 | ||
1400 | /* jle. */ | |
1401 | void | |
1402 | OP_A7_C () | |
1403 | { | |
1404 | uint32 tmp; | |
1405 | trace_input ("jle", OP_REGP, OP_VOID, OP_VOID); | |
1406 | if ((PSR_N) == 0) | |
1407 | { | |
1408 | tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ | |
1409 | JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ | |
1410 | } | |
1411 | trace_output_32 (tmp); | |
1412 | } | |
1413 | ||
1414 | ||
1415 | /* jfs. */ | |
1416 | void | |
1417 | OP_A8_C () | |
1418 | { | |
1419 | uint32 tmp; | |
1420 | trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID); | |
1421 | if ((PSR_F) == 1) | |
1422 | { | |
1423 | tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ | |
1424 | JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ | |
1425 | } | |
1426 | trace_output_32 (tmp); | |
1427 | } | |
1428 | ||
1429 | /* jfc. */ | |
1430 | void | |
1431 | OP_A9_C () | |
1432 | { | |
1433 | uint32 tmp; | |
1434 | trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID); | |
1435 | if ((PSR_F) == 0) | |
1436 | { | |
1437 | tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ | |
1438 | JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ | |
1439 | } | |
1440 | trace_output_32 (tmp); | |
1441 | } | |
1442 | ||
1443 | /* jlo. */ | |
1444 | void | |
1445 | OP_AA_C () | |
1446 | { | |
1447 | uint32 tmp; | |
1448 | trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID); | |
1449 | if (((PSR_Z) == 0) & ((PSR_L) == 0)) | |
1450 | { | |
1451 | tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ | |
1452 | JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ | |
1453 | } | |
1454 | trace_output_32 (tmp); | |
1455 | } | |
1456 | ||
1457 | /* jhs. */ | |
1458 | void | |
1459 | OP_AB_C () | |
1460 | { | |
1461 | uint32 tmp; | |
1462 | trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID); | |
1463 | if (((PSR_Z) == 1) | ((PSR_L) == 1)) | |
1464 | { | |
1465 | tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ | |
1466 | JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ | |
1467 | } | |
1468 | trace_output_32 (tmp); | |
1469 | } | |
1470 | ||
1471 | /* jlt. */ | |
1472 | void | |
1473 | OP_AC_C () | |
1474 | { | |
1475 | uint32 tmp; | |
1476 | trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID); | |
1477 | if (((PSR_Z) == 0) & ((PSR_N) == 0)) | |
1478 | { | |
1479 | tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ | |
1480 | JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ | |
1481 | } | |
1482 | trace_output_32 (tmp); | |
1483 | } | |
1484 | ||
1485 | /* jge. */ | |
1486 | void | |
1487 | OP_AD_C () | |
1488 | { | |
1489 | uint32 tmp; | |
1490 | trace_input ("jge", OP_REGP, OP_VOID, OP_VOID); | |
1491 | if (((PSR_Z) == 1) | ((PSR_N) == 1)) | |
1492 | { | |
1493 | tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ | |
1494 | JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ | |
1495 | } | |
1496 | trace_output_32 (tmp); | |
1497 | } | |
1498 | ||
1499 | /* jump. */ | |
1500 | void | |
1501 | OP_AE_C () | |
1502 | { | |
1503 | uint32 tmp; | |
1504 | trace_input ("jump", OP_REGP, OP_VOID, OP_VOID); | |
1505 | tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */ | |
1506 | JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ | |
1507 | trace_output_32 (tmp); | |
1508 | } | |
1509 | ||
1510 | /* jusr. */ | |
1511 | void | |
1512 | OP_AF_C () | |
1513 | { | |
1514 | uint32 tmp; | |
1515 | trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID); | |
1516 | tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ | |
1517 | JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ | |
1518 | SET_PSR_U(1); | |
1519 | trace_output_32 (tmp); | |
1520 | } | |
1521 | ||
1522 | /* seq. */ | |
1523 | void | |
1524 | OP_80_C () | |
1525 | { | |
1526 | trace_input ("seq", OP_REG, OP_VOID, OP_VOID); | |
1527 | if ((PSR_Z) == 1) | |
1528 | SET_GPR (OP[0], 1); | |
1529 | else | |
1530 | SET_GPR (OP[0], 0); | |
1531 | trace_output_void (); | |
1532 | } | |
1533 | /* sne. */ | |
1534 | void | |
1535 | OP_81_C () | |
1536 | { | |
1537 | trace_input ("sne", OP_REG, OP_VOID, OP_VOID); | |
1538 | if ((PSR_Z) == 0) | |
1539 | SET_GPR (OP[0], 1); | |
1540 | else | |
1541 | SET_GPR (OP[0], 0); | |
1542 | trace_output_void (); | |
1543 | } | |
1544 | ||
1545 | /* scs. */ | |
1546 | void | |
1547 | OP_82_C () | |
1548 | { | |
1549 | trace_input ("scs", OP_REG, OP_VOID, OP_VOID); | |
1550 | if ((PSR_C) == 1) | |
1551 | SET_GPR (OP[0], 1); | |
1552 | else | |
1553 | SET_GPR (OP[0], 0); | |
1554 | trace_output_void (); | |
1555 | } | |
1556 | ||
1557 | /* scc. */ | |
1558 | void | |
1559 | OP_83_C () | |
1560 | { | |
1561 | trace_input ("scc", OP_REG, OP_VOID, OP_VOID); | |
1562 | if ((PSR_C) == 0) | |
1563 | SET_GPR (OP[0], 1); | |
1564 | else | |
1565 | SET_GPR (OP[0], 0); | |
1566 | trace_output_void (); | |
1567 | } | |
1568 | ||
1569 | /* shi. */ | |
1570 | void | |
1571 | OP_84_C () | |
1572 | { | |
1573 | trace_input ("shi", OP_REG, OP_VOID, OP_VOID); | |
1574 | if ((PSR_L) == 1) | |
1575 | SET_GPR (OP[0], 1); | |
1576 | else | |
1577 | SET_GPR (OP[0], 0); | |
1578 | trace_output_void (); | |
1579 | } | |
1580 | ||
1581 | /* sls. */ | |
1582 | void | |
1583 | OP_85_C () | |
1584 | { | |
1585 | trace_input ("sls", OP_REG, OP_VOID, OP_VOID); | |
1586 | if ((PSR_L) == 0) | |
1587 | SET_GPR (OP[0], 1); | |
1588 | else | |
1589 | SET_GPR (OP[0], 0); | |
1590 | trace_output_void (); | |
1591 | } | |
1592 | ||
1593 | /* sgt. */ | |
1594 | void | |
1595 | OP_86_C () | |
1596 | { | |
1597 | trace_input ("sgt", OP_REG, OP_VOID, OP_VOID); | |
1598 | if ((PSR_N) == 1) | |
1599 | SET_GPR (OP[0], 1); | |
1600 | else | |
1601 | SET_GPR (OP[0], 0); | |
1602 | trace_output_void (); | |
1603 | } | |
1604 | ||
1605 | /* sle. */ | |
1606 | void | |
1607 | OP_87_C () | |
1608 | { | |
1609 | trace_input ("sle", OP_REG, OP_VOID, OP_VOID); | |
1610 | if ((PSR_N) == 0) | |
1611 | SET_GPR (OP[0], 1); | |
1612 | else | |
1613 | SET_GPR (OP[0], 0); | |
1614 | trace_output_void (); | |
1615 | } | |
1616 | ||
1617 | /* sfs. */ | |
1618 | void | |
1619 | OP_88_C () | |
1620 | { | |
1621 | trace_input ("sfs", OP_REG, OP_VOID, OP_VOID); | |
1622 | if ((PSR_F) == 1) | |
1623 | SET_GPR (OP[0], 1); | |
1624 | else | |
1625 | SET_GPR (OP[0], 0); | |
1626 | trace_output_void (); | |
1627 | } | |
1628 | ||
1629 | /* sfc. */ | |
1630 | void | |
1631 | OP_89_C () | |
1632 | { | |
1633 | trace_input ("sfc", OP_REG, OP_VOID, OP_VOID); | |
1634 | if ((PSR_F) == 0) | |
1635 | SET_GPR (OP[0], 1); | |
1636 | else | |
1637 | SET_GPR (OP[0], 0); | |
1638 | trace_output_void (); | |
1639 | } | |
1640 | ||
1641 | ||
1642 | /* slo. */ | |
1643 | void | |
1644 | OP_8A_C () | |
1645 | { | |
1646 | trace_input ("slo", OP_REG, OP_VOID, OP_VOID); | |
1647 | if (((PSR_Z) == 0) & ((PSR_L) == 0)) | |
1648 | SET_GPR (OP[0], 1); | |
1649 | else | |
1650 | SET_GPR (OP[0], 0); | |
1651 | trace_output_void (); | |
1652 | } | |
1653 | ||
1654 | /* shs. */ | |
1655 | void | |
1656 | OP_8B_C () | |
1657 | { | |
1658 | trace_input ("shs", OP_REG, OP_VOID, OP_VOID); | |
1659 | if ( ((PSR_Z) == 1) | ((PSR_L) == 1)) | |
1660 | SET_GPR (OP[0], 1); | |
1661 | else | |
1662 | SET_GPR (OP[0], 0); | |
1663 | trace_output_void (); | |
1664 | } | |
1665 | ||
1666 | /* slt. */ | |
1667 | void | |
1668 | OP_8C_C () | |
1669 | { | |
1670 | trace_input ("slt", OP_REG, OP_VOID, OP_VOID); | |
1671 | if (((PSR_Z) == 0) & ((PSR_N) == 0)) | |
1672 | SET_GPR (OP[0], 1); | |
1673 | else | |
1674 | SET_GPR (OP[0], 0); | |
1675 | trace_output_void (); | |
1676 | } | |
1677 | ||
1678 | /* sge. */ | |
1679 | void | |
1680 | OP_8D_C () | |
1681 | { | |
1682 | trace_input ("sge", OP_REG, OP_VOID, OP_VOID); | |
1683 | if (((PSR_Z) == 1) | ((PSR_N) == 1)) | |
1684 | SET_GPR (OP[0], 1); | |
1685 | else | |
1686 | SET_GPR (OP[0], 0); | |
1687 | trace_output_void (); | |
1688 | } | |
1689 | ||
1690 | /* cbitb. */ | |
1691 | void | |
1692 | OP_D7_9 () | |
1693 | { | |
1694 | uint8 a = OP[0] & 0xff; | |
1695 | uint32 addr = OP[1], tmp; | |
1696 | trace_input ("cbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); | |
1697 | tmp = RB (addr); | |
1698 | SET_PSR_F (tmp & (1 << a)); | |
1699 | tmp = tmp & ~(1 << a); | |
1700 | SB (addr, tmp); | |
1701 | trace_output_32 (tmp); | |
1702 | } | |
1703 | ||
1704 | /* cbitb. */ | |
1705 | void | |
1706 | OP_107_14 () | |
1707 | { | |
1708 | uint8 a = OP[0] & 0xff; | |
1709 | uint32 addr = OP[1], tmp; | |
1710 | trace_input ("cbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); | |
1711 | tmp = RB (addr); | |
1712 | SET_PSR_F (tmp & (1 << a)); | |
1713 | tmp = tmp & ~(1 << a); | |
1714 | SB (addr, tmp); | |
1715 | trace_output_32 (tmp); | |
1716 | } | |
1717 | ||
1718 | /* cbitb. */ | |
1719 | void | |
1720 | OP_68_8 () | |
1721 | { | |
1722 | uint8 a = (OP[0]) & 0xff; | |
1723 | uint32 addr = (GPR (OP[2])) + OP[1], tmp; | |
1724 | trace_input ("cbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID); | |
1725 | tmp = RB (addr); | |
1726 | SET_PSR_F (tmp & (1 << a)); | |
1727 | tmp = tmp & ~(1 << a); | |
1728 | SB (addr, tmp); | |
1729 | trace_output_32 (addr); | |
1730 | } | |
1731 | ||
1732 | /* cbitb. */ | |
1733 | void | |
1734 | OP_1AA_A () | |
1735 | { | |
1736 | uint8 a = (OP[0]) & 0xff; | |
1737 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
1738 | trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); | |
1739 | tmp = RB (addr); | |
1740 | SET_PSR_F (tmp & (1 << a)); | |
1741 | tmp = tmp & ~(1 << a); | |
1742 | SB (addr, tmp); | |
1743 | trace_output_32 (addr); | |
1744 | } | |
1745 | ||
1746 | /* cbitb. */ | |
1747 | void | |
1748 | OP_104_14 () | |
1749 | { | |
1750 | uint8 a = (OP[0]) & 0xff; | |
1751 | uint32 addr = (GPR (OP[2])) + OP[1], tmp; | |
1752 | trace_input ("cbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); | |
1753 | tmp = RB (addr); | |
1754 | SET_PSR_F (tmp & (1 << a)); | |
1755 | tmp = tmp & ~(1 << a); | |
1756 | SB (addr, tmp); | |
1757 | trace_output_32 (addr); | |
1758 | } | |
1759 | ||
1760 | /* cbitb. */ | |
1761 | void | |
1762 | OP_D4_9 () | |
1763 | { | |
1764 | uint8 a = (OP[0]) & 0xff; | |
1765 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
1766 | trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); | |
1767 | tmp = RB (addr); | |
1768 | SET_PSR_F (tmp & (1 << a)); | |
1769 | tmp = tmp & ~(1 << a); | |
1770 | SB (addr, tmp); | |
1771 | trace_output_32 (addr); | |
1772 | } | |
1773 | ||
1774 | /* cbitb. */ | |
1775 | void | |
1776 | OP_D6_9 () | |
1777 | { | |
1778 | uint8 a = (OP[0]) & 0xff; | |
1779 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
1780 | trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); | |
1781 | tmp = RB (addr); | |
1782 | SET_PSR_F (tmp & (1 << a)); | |
1783 | tmp = tmp & ~(1 << a); | |
1784 | SB (addr, tmp); | |
1785 | trace_output_32 (addr); | |
1786 | ||
1787 | } | |
1788 | ||
1789 | /* cbitb. */ | |
1790 | void | |
1791 | OP_105_14 () | |
1792 | { | |
1793 | uint8 a = (OP[0]) & 0xff; | |
1794 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
1795 | trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); | |
1796 | tmp = RB (addr); | |
1797 | SET_PSR_F (tmp & (1 << a)); | |
1798 | tmp = tmp & ~(1 << a); | |
1799 | SB (addr, tmp); | |
1800 | trace_output_32 (addr); | |
1801 | } | |
1802 | ||
1803 | /* cbitb. */ | |
1804 | void | |
1805 | OP_106_14 () | |
1806 | { | |
1807 | uint8 a = (OP[0]) & 0xff; | |
1808 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
1809 | trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); | |
1810 | tmp = RB (addr); | |
1811 | SET_PSR_F (tmp & (1 << a)); | |
1812 | tmp = tmp & ~(1 << a); | |
1813 | SB (addr, tmp); | |
1814 | trace_output_32 (addr); | |
1815 | } | |
1816 | ||
1817 | ||
1818 | /* cbitw. */ | |
1819 | void | |
1820 | OP_6F_8 () | |
1821 | { | |
1822 | uint16 a = OP[0]; | |
1823 | uint32 addr = OP[1], tmp; | |
1824 | trace_input ("cbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); | |
1825 | tmp = RW (addr); | |
1826 | SET_PSR_F (tmp & (1 << a)); | |
1827 | tmp = tmp & ~(1 << a); | |
1828 | SW (addr, tmp); | |
1829 | trace_output_32 (tmp); | |
1830 | } | |
1831 | ||
1832 | /* cbitw. */ | |
1833 | void | |
1834 | OP_117_14 () | |
1835 | { | |
1836 | uint16 a = OP[0]; | |
1837 | uint32 addr = OP[1], tmp; | |
1838 | trace_input ("cbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); | |
1839 | tmp = RW (addr); | |
1840 | SET_PSR_F (tmp & (1 << a)); | |
1841 | tmp = tmp & ~(1 << a); | |
1842 | SW (addr, tmp); | |
1843 | trace_output_32 (tmp); | |
1844 | } | |
1845 | ||
1846 | /* cbitw. */ | |
1847 | void | |
1848 | OP_36_7 () | |
1849 | { | |
1850 | uint32 addr; | |
1851 | uint16 a = (OP[0]), tmp; | |
1852 | trace_input ("cbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID); | |
1853 | ||
1854 | if (OP[1] == 0) | |
1855 | addr = (GPR32 (12)) + OP[2]; | |
1856 | else | |
1857 | addr = (GPR32 (13)) + OP[2]; | |
1858 | ||
1859 | tmp = RW (addr); | |
1860 | SET_PSR_F (tmp & (1 << a)); | |
1861 | tmp = tmp & ~(1 << a); | |
1862 | SW (addr, tmp); | |
1863 | trace_output_32 (addr); | |
1864 | ||
1865 | } | |
1866 | ||
1867 | /* cbitw. */ | |
1868 | void | |
1869 | OP_1AB_A () | |
1870 | { | |
1871 | uint16 a = (OP[0]); | |
1872 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
1873 | trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); | |
1874 | tmp = RW (addr); | |
1875 | SET_PSR_F (tmp & (1 << a)); | |
1876 | tmp = tmp & ~(1 << a); | |
1877 | SW (addr, tmp); | |
1878 | trace_output_32 (addr); | |
1879 | } | |
1880 | ||
1881 | /* cbitw. */ | |
1882 | void | |
1883 | OP_114_14 () | |
1884 | { | |
1885 | uint16 a = (OP[0]); | |
1886 | uint32 addr = (GPR (OP[2])) + OP[1], tmp; | |
1887 | trace_input ("cbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); | |
1888 | tmp = RW (addr); | |
1889 | SET_PSR_F (tmp & (1 << a)); | |
1890 | tmp = tmp & ~(1 << a); | |
1891 | SW (addr, tmp); | |
1892 | trace_output_32 (addr); | |
1893 | } | |
1894 | ||
1895 | ||
1896 | /* cbitw. */ | |
1897 | void | |
1898 | OP_6E_8 () | |
1899 | { | |
1900 | uint16 a = (OP[0]); | |
1901 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
1902 | trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); | |
1903 | tmp = RW (addr); | |
1904 | SET_PSR_F (tmp & (1 << a)); | |
1905 | tmp = tmp & ~(1 << a); | |
1906 | SW (addr, tmp); | |
1907 | trace_output_32 (addr); | |
1908 | } | |
1909 | ||
1910 | /* cbitw. */ | |
1911 | void | |
1912 | OP_69_8 () | |
1913 | { | |
1914 | uint16 a = (OP[0]); | |
1915 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
1916 | trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); | |
1917 | tmp = RW (addr); | |
1918 | SET_PSR_F (tmp & (1 << a)); | |
1919 | tmp = tmp & ~(1 << a); | |
1920 | SW (addr, tmp); | |
1921 | trace_output_32 (addr); | |
1922 | } | |
1923 | ||
1924 | ||
1925 | /* cbitw. */ | |
1926 | void | |
1927 | OP_115_14 () | |
1928 | { | |
1929 | uint16 a = (OP[0]); | |
1930 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
1931 | trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); | |
1932 | tmp = RW (addr); | |
1933 | SET_PSR_F (tmp & (1 << a)); | |
1934 | tmp = tmp & ~(1 << a); | |
1935 | SW (addr, tmp); | |
1936 | trace_output_32 (addr); | |
1937 | } | |
1938 | ||
1939 | /* cbitw. */ | |
1940 | void | |
1941 | OP_116_14 () | |
1942 | { | |
1943 | uint16 a = (OP[0]); | |
1944 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
1945 | trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); | |
1946 | tmp = RW (addr); | |
1947 | SET_PSR_F (tmp & (1 << a)); | |
1948 | tmp = tmp & ~(1 << a); | |
1949 | SW (addr, tmp); | |
1950 | trace_output_32 (addr); | |
1951 | } | |
1952 | ||
1953 | /* sbitb. */ | |
1954 | void | |
1955 | OP_E7_9 () | |
1956 | { | |
1957 | uint8 a = OP[0] & 0xff; | |
1958 | uint32 addr = OP[1], tmp; | |
1959 | trace_input ("sbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); | |
1960 | tmp = RB (addr); | |
1961 | SET_PSR_F (tmp & (1 << a)); | |
1962 | tmp = tmp | (1 << a); | |
1963 | SB (addr, tmp); | |
1964 | trace_output_32 (tmp); | |
1965 | } | |
1966 | ||
1967 | /* sbitb. */ | |
1968 | void | |
1969 | OP_10B_14 () | |
1970 | { | |
1971 | uint8 a = OP[0] & 0xff; | |
1972 | uint32 addr = OP[1], tmp; | |
1973 | trace_input ("sbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); | |
1974 | tmp = RB (addr); | |
1975 | SET_PSR_F (tmp & (1 << a)); | |
1976 | tmp = tmp | (1 << a); | |
1977 | SB (addr, tmp); | |
1978 | trace_output_32 (tmp); | |
1979 | } | |
1980 | ||
1981 | /* sbitb. */ | |
1982 | void | |
1983 | OP_70_8 () | |
1984 | { | |
1985 | uint8 a = OP[0] & 0xff; | |
1986 | uint32 addr = (GPR (OP[2])) + OP[1], tmp; | |
1987 | trace_input ("sbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID); | |
1988 | tmp = RB (addr); | |
1989 | SET_PSR_F (tmp & (1 << a)); | |
1990 | tmp = tmp | (1 << a); | |
1991 | SB (addr, tmp); | |
1992 | trace_output_32 (tmp); | |
1993 | } | |
1994 | ||
1995 | /* sbitb. */ | |
1996 | void | |
1997 | OP_1CA_A () | |
1998 | { | |
1999 | uint8 a = OP[0] & 0xff; | |
2000 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2001 | trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); | |
2002 | tmp = RB (addr); | |
2003 | SET_PSR_F (tmp & (1 << a)); | |
2004 | tmp = tmp | (1 << a); | |
2005 | SB (addr, tmp); | |
2006 | trace_output_32 (tmp); | |
2007 | } | |
2008 | ||
2009 | /* sbitb. */ | |
2010 | void | |
2011 | OP_108_14 () | |
2012 | { | |
2013 | uint8 a = OP[0] & 0xff; | |
2014 | uint32 addr = (GPR (OP[2])) + OP[1], tmp; | |
2015 | trace_input ("sbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); | |
2016 | tmp = RB (addr); | |
2017 | SET_PSR_F (tmp & (1 << a)); | |
2018 | tmp = tmp | (1 << a); | |
2019 | SB (addr, tmp); | |
2020 | trace_output_32 (tmp); | |
2021 | } | |
2022 | ||
2023 | ||
2024 | /* sbitb. */ | |
2025 | void | |
2026 | OP_E4_9 () | |
2027 | { | |
2028 | uint8 a = OP[0] & 0xff; | |
2029 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2030 | trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); | |
2031 | tmp = RB (addr); | |
2032 | SET_PSR_F (tmp & (1 << a)); | |
2033 | tmp = tmp | (1 << a); | |
2034 | SB (addr, tmp); | |
2035 | trace_output_32 (tmp); | |
2036 | } | |
2037 | ||
2038 | /* sbitb. */ | |
2039 | void | |
2040 | OP_E6_9 () | |
2041 | { | |
2042 | uint8 a = OP[0] & 0xff; | |
2043 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2044 | trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); | |
2045 | tmp = RB (addr); | |
2046 | SET_PSR_F (tmp & (1 << a)); | |
2047 | tmp = tmp | (1 << a); | |
2048 | SB (addr, tmp); | |
2049 | trace_output_32 (tmp); | |
2050 | } | |
2051 | ||
2052 | ||
2053 | /* sbitb. */ | |
2054 | void | |
2055 | OP_109_14 () | |
2056 | { | |
2057 | uint8 a = OP[0] & 0xff; | |
2058 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2059 | trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); | |
2060 | tmp = RB (addr); | |
2061 | SET_PSR_F (tmp & (1 << a)); | |
2062 | tmp = tmp | (1 << a); | |
2063 | SB (addr, tmp); | |
2064 | trace_output_32 (tmp); | |
2065 | } | |
2066 | ||
2067 | ||
2068 | /* sbitb. */ | |
2069 | void | |
2070 | OP_10A_14 () | |
2071 | { | |
2072 | uint8 a = OP[0] & 0xff; | |
2073 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2074 | trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); | |
2075 | tmp = RB (addr); | |
2076 | SET_PSR_F (tmp & (1 << a)); | |
2077 | tmp = tmp | (1 << a); | |
2078 | SB (addr, tmp); | |
2079 | trace_output_32 (tmp); | |
2080 | } | |
2081 | ||
2082 | ||
2083 | /* sbitw. */ | |
2084 | void | |
2085 | OP_77_8 () | |
2086 | { | |
2087 | uint16 a = OP[0]; | |
2088 | uint32 addr = OP[1], tmp; | |
2089 | trace_input ("sbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); | |
2090 | tmp = RW (addr); | |
2091 | SET_PSR_F (tmp & (1 << a)); | |
2092 | tmp = tmp | (1 << a); | |
2093 | SW (addr, tmp); | |
2094 | trace_output_32 (tmp); | |
2095 | } | |
2096 | ||
2097 | /* sbitw. */ | |
2098 | void | |
2099 | OP_11B_14 () | |
2100 | { | |
2101 | uint16 a = OP[0]; | |
2102 | uint32 addr = OP[1], tmp; | |
2103 | trace_input ("sbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); | |
2104 | tmp = RW (addr); | |
2105 | SET_PSR_F (tmp & (1 << a)); | |
2106 | tmp = tmp | (1 << a); | |
2107 | SW (addr, tmp); | |
2108 | trace_output_32 (tmp); | |
2109 | } | |
2110 | ||
2111 | /* sbitw. */ | |
2112 | void | |
2113 | OP_3A_7 () | |
2114 | { | |
2115 | uint32 addr; | |
2116 | uint16 a = (OP[0]), tmp; | |
2117 | trace_input ("sbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID); | |
2118 | ||
2119 | if (OP[1] == 0) | |
2120 | addr = (GPR32 (12)) + OP[2]; | |
2121 | else | |
2122 | addr = (GPR32 (13)) + OP[2]; | |
2123 | ||
2124 | tmp = RW (addr); | |
2125 | SET_PSR_F (tmp & (1 << a)); | |
2126 | tmp = tmp | (1 << a); | |
2127 | SW (addr, tmp); | |
2128 | trace_output_32 (addr); | |
2129 | } | |
2130 | ||
2131 | /* sbitw. */ | |
2132 | void | |
2133 | OP_1CB_A () | |
2134 | { | |
2135 | uint16 a = (OP[0]); | |
2136 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2137 | trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); | |
2138 | tmp = RW (addr); | |
2139 | SET_PSR_F (tmp & (1 << a)); | |
2140 | tmp = tmp | (1 << a); | |
2141 | SW (addr, tmp); | |
2142 | trace_output_32 (addr); | |
2143 | } | |
2144 | ||
2145 | /* sbitw. */ | |
2146 | void | |
2147 | OP_118_14 () | |
2148 | { | |
2149 | uint16 a = (OP[0]); | |
2150 | uint32 addr = (GPR (OP[2])) + OP[1], tmp; | |
2151 | trace_input ("sbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); | |
2152 | tmp = RW (addr); | |
2153 | SET_PSR_F (tmp & (1 << a)); | |
2154 | tmp = tmp | (1 << a); | |
2155 | SW (addr, tmp); | |
2156 | trace_output_32 (addr); | |
2157 | } | |
2158 | ||
2159 | /* sbitw. */ | |
2160 | void | |
2161 | OP_76_8 () | |
2162 | { | |
2163 | uint16 a = (OP[0]); | |
2164 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2165 | trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); | |
2166 | tmp = RW (addr); | |
2167 | SET_PSR_F (tmp & (1 << a)); | |
2168 | tmp = tmp | (1 << a); | |
2169 | SW (addr, tmp); | |
2170 | trace_output_32 (addr); | |
2171 | } | |
2172 | ||
2173 | /* sbitw. */ | |
2174 | void | |
2175 | OP_71_8 () | |
2176 | { | |
2177 | uint16 a = (OP[0]); | |
2178 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2179 | trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); | |
2180 | tmp = RW (addr); | |
2181 | SET_PSR_F (tmp & (1 << a)); | |
2182 | tmp = tmp | (1 << a); | |
2183 | SW (addr, tmp); | |
2184 | trace_output_32 (addr); | |
2185 | } | |
2186 | ||
2187 | /* sbitw. */ | |
2188 | void | |
2189 | OP_119_14 () | |
2190 | { | |
2191 | uint16 a = (OP[0]); | |
2192 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2193 | trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); | |
2194 | tmp = RW (addr); | |
2195 | SET_PSR_F (tmp & (1 << a)); | |
2196 | tmp = tmp | (1 << a); | |
2197 | SW (addr, tmp); | |
2198 | trace_output_32 (addr); | |
2199 | } | |
2200 | ||
2201 | /* sbitw. */ | |
2202 | void | |
2203 | OP_11A_14 () | |
2204 | { | |
2205 | uint16 a = (OP[0]); | |
2206 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2207 | trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); | |
2208 | tmp = RW (addr); | |
2209 | SET_PSR_F (tmp & (1 << a)); | |
2210 | tmp = tmp | (1 << a); | |
2211 | SW (addr, tmp); | |
2212 | trace_output_32 (addr); | |
2213 | } | |
2214 | ||
2215 | ||
2216 | /* tbitb. */ | |
2217 | void | |
2218 | OP_F7_9 () | |
2219 | { | |
2220 | uint8 a = OP[0] & 0xff; | |
2221 | uint32 addr = OP[1], tmp; | |
2222 | trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); | |
2223 | tmp = RB (addr); | |
2224 | SET_PSR_F (tmp & (1 << a)); | |
2225 | trace_output_32 (tmp); | |
2226 | } | |
2227 | ||
2228 | /* tbitb. */ | |
2229 | void | |
2230 | OP_10F_14 () | |
2231 | { | |
2232 | uint8 a = OP[0] & 0xff; | |
2233 | uint32 addr = OP[1], tmp; | |
2234 | trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); | |
2235 | tmp = RB (addr); | |
2236 | SET_PSR_F (tmp & (1 << a)); | |
2237 | trace_output_32 (tmp); | |
2238 | } | |
2239 | ||
2240 | /* tbitb. */ | |
2241 | void | |
2242 | OP_78_8 () | |
2243 | { | |
2244 | uint8 a = (OP[0]) & 0xff; | |
2245 | uint32 addr = (GPR (OP[2])) + OP[1], tmp; | |
2246 | trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID); | |
2247 | tmp = RB (addr); | |
2248 | SET_PSR_F (tmp & (1 << a)); | |
2249 | trace_output_32 (addr); | |
2250 | } | |
2251 | ||
2252 | /* tbitb. */ | |
2253 | void | |
2254 | OP_1EA_A () | |
2255 | { | |
2256 | uint8 a = (OP[0]) & 0xff; | |
2257 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2258 | trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); | |
2259 | tmp = RB (addr); | |
2260 | SET_PSR_F (tmp & (1 << a)); | |
2261 | trace_output_32 (addr); | |
2262 | } | |
2263 | ||
2264 | /* tbitb. */ | |
2265 | void | |
2266 | OP_10C_14 () | |
2267 | { | |
2268 | uint8 a = (OP[0]) & 0xff; | |
2269 | uint32 addr = (GPR (OP[2])) + OP[1], tmp; | |
2270 | trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); | |
2271 | tmp = RB (addr); | |
2272 | SET_PSR_F (tmp & (1 << a)); | |
2273 | trace_output_32 (addr); | |
2274 | } | |
2275 | ||
2276 | /* tbitb. */ | |
2277 | void | |
2278 | OP_F4_9 () | |
2279 | { | |
2280 | uint8 a = (OP[0]) & 0xff; | |
2281 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2282 | trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); | |
2283 | tmp = RB (addr); | |
2284 | SET_PSR_F (tmp & (1 << a)); | |
2285 | trace_output_32 (addr); | |
2286 | } | |
2287 | ||
2288 | /* tbitb. */ | |
2289 | void | |
2290 | OP_F6_9 () | |
2291 | { | |
2292 | uint8 a = (OP[0]) & 0xff; | |
2293 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2294 | trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); | |
2295 | tmp = RB (addr); | |
2296 | SET_PSR_F (tmp & (1 << a)); | |
2297 | trace_output_32 (addr); | |
2298 | } | |
2299 | ||
2300 | /* tbitb. */ | |
2301 | void | |
2302 | OP_10D_14 () | |
2303 | { | |
2304 | uint8 a = (OP[0]) & 0xff; | |
2305 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2306 | trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); | |
2307 | tmp = RB (addr); | |
2308 | SET_PSR_F (tmp & (1 << a)); | |
2309 | trace_output_32 (addr); | |
2310 | } | |
2311 | ||
2312 | /* tbitb. */ | |
2313 | void | |
2314 | OP_10E_14 () | |
2315 | { | |
2316 | uint8 a = (OP[0]) & 0xff; | |
2317 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2318 | trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); | |
2319 | tmp = RB (addr); | |
2320 | SET_PSR_F (tmp & (1 << a)); | |
2321 | trace_output_32 (addr); | |
2322 | } | |
2323 | ||
2324 | ||
2325 | /* tbitw. */ | |
2326 | void | |
2327 | OP_7F_8 () | |
2328 | { | |
2329 | uint16 a = OP[0]; | |
2330 | uint32 addr = OP[1], tmp; | |
2331 | trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); | |
2332 | tmp = RW (addr); | |
2333 | SET_PSR_F (tmp & (1 << a)); | |
2334 | trace_output_32 (tmp); | |
2335 | } | |
2336 | ||
2337 | /* tbitw. */ | |
2338 | void | |
2339 | OP_11F_14 () | |
2340 | { | |
2341 | uint16 a = OP[0]; | |
2342 | uint32 addr = OP[1], tmp; | |
2343 | trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); | |
2344 | tmp = RW (addr); | |
2345 | SET_PSR_F (tmp & (1 << a)); | |
2346 | trace_output_32 (tmp); | |
2347 | } | |
2348 | ||
2349 | ||
2350 | /* tbitw. */ | |
2351 | void | |
2352 | OP_3E_7 () | |
2353 | { | |
2354 | uint32 addr; | |
2355 | uint16 a = (OP[0]), tmp; | |
2356 | trace_input ("tbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID); | |
2357 | ||
2358 | if (OP[1] == 0) | |
2359 | addr = (GPR32 (12)) + OP[2]; | |
2360 | else | |
2361 | addr = (GPR32 (13)) + OP[2]; | |
2362 | ||
2363 | tmp = RW (addr); | |
2364 | SET_PSR_F (tmp & (1 << a)); | |
2365 | trace_output_32 (addr); | |
2366 | } | |
2367 | ||
2368 | /* tbitw. */ | |
2369 | void | |
2370 | OP_1EB_A () | |
2371 | { | |
2372 | uint16 a = (OP[0]); | |
2373 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2374 | trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); | |
2375 | tmp = RW (addr); | |
2376 | SET_PSR_F (tmp & (1 << a)); | |
2377 | trace_output_32 (addr); | |
2378 | } | |
2379 | ||
2380 | /* tbitw. */ | |
2381 | void | |
2382 | OP_11C_14 () | |
2383 | { | |
2384 | uint16 a = (OP[0]); | |
2385 | uint32 addr = (GPR (OP[2])) + OP[1], tmp; | |
2386 | trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); | |
2387 | tmp = RW (addr); | |
2388 | SET_PSR_F (tmp & (1 << a)); | |
2389 | trace_output_32 (addr); | |
2390 | } | |
2391 | ||
2392 | /* tbitw. */ | |
2393 | void | |
2394 | OP_7E_8 () | |
2395 | { | |
2396 | uint16 a = (OP[0]); | |
2397 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2398 | trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); | |
2399 | tmp = RW (addr); | |
2400 | SET_PSR_F (tmp & (1 << a)); | |
2401 | trace_output_32 (addr); | |
2402 | } | |
2403 | ||
2404 | /* tbitw. */ | |
2405 | void | |
2406 | OP_79_8 () | |
2407 | { | |
2408 | uint16 a = (OP[0]); | |
2409 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2410 | trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); | |
2411 | tmp = RW (addr); | |
2412 | SET_PSR_F (tmp & (1 << a)); | |
2413 | trace_output_32 (addr); | |
2414 | } | |
2415 | ||
2416 | /* tbitw. */ | |
2417 | void | |
2418 | OP_11D_14 () | |
2419 | { | |
2420 | uint16 a = (OP[0]); | |
2421 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2422 | trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); | |
2423 | tmp = RW (addr); | |
2424 | SET_PSR_F (tmp & (1 << a)); | |
2425 | trace_output_32 (addr); | |
2426 | } | |
2427 | ||
2428 | ||
2429 | /* tbitw. */ | |
2430 | void | |
2431 | OP_11E_14 () | |
2432 | { | |
2433 | uint16 a = (OP[0]); | |
2434 | uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; | |
2435 | trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); | |
2436 | tmp = RW (addr); | |
2437 | SET_PSR_F (tmp & (1 << a)); | |
2438 | trace_output_32 (addr); | |
2439 | } | |
2440 | ||
2441 | ||
2442 | /* tbit. */ | |
2443 | void | |
2444 | OP_6_8 () | |
2445 | { | |
2446 | uint16 a = OP[0]; | |
2447 | uint32 addr = (GPR (OP[1])), tmp; | |
2448 | trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID); | |
2449 | tmp = RW (addr); | |
2450 | SET_PSR_F (tmp & (1 << a)); | |
2451 | trace_output_32 (tmp); | |
2452 | } | |
2453 | ||
2454 | /* tbit. */ | |
2455 | void | |
2456 | OP_7_8 () | |
2457 | { | |
2458 | uint16 a = GPR (OP[0]); | |
2459 | uint32 addr = (GPR (OP[1])), tmp; | |
2460 | trace_input ("tbit", OP_REG, OP_REG, OP_VOID); | |
2461 | tmp = RW (addr); | |
2462 | SET_PSR_F (tmp & (1 << a)); | |
2463 | trace_output_32 (tmp); | |
2464 | } | |
2465 | ||
2466 | ||
2467 | /* cmpb. */ | |
2468 | void | |
2469 | OP_50_8 () | |
2470 | { | |
2471 | uint8 a = (OP[0]) & 0xFF; | |
2472 | uint8 b = (GPR (OP[1])) & 0xFF; | |
2473 | trace_input ("cmpb", OP_CONSTANT4, OP_REG, OP_VOID); | |
2474 | SET_PSR_Z (a == b); | |
2475 | SET_PSR_N ((int8)a > (int8)b); | |
2476 | SET_PSR_L (a > b); | |
2477 | trace_output_flag (); | |
2478 | } | |
2479 | ||
2480 | /* cmpb. */ | |
2481 | void | |
2482 | OP_50B_C () | |
2483 | { | |
2484 | uint8 a = (OP[0]) & 0xFF; | |
2485 | uint8 b = (GPR (OP[1])) & 0xFF; | |
2486 | trace_input ("cmpb", OP_CONSTANT16, OP_REG, OP_VOID); | |
2487 | SET_PSR_Z (a == b); | |
2488 | SET_PSR_N ((int8)a > (int8)b); | |
2489 | SET_PSR_L (a > b); | |
2490 | trace_output_flag (); | |
2491 | } | |
2492 | ||
2493 | /* cmpb. */ | |
2494 | void | |
2495 | OP_51_8 () | |
2496 | { | |
2497 | uint8 a = (GPR (OP[0])) & 0xFF; | |
2498 | uint8 b = (GPR (OP[1])) & 0xFF; | |
2499 | trace_input ("cmpb", OP_REG, OP_REG, OP_VOID); | |
2500 | SET_PSR_Z (a == b); | |
2501 | SET_PSR_N ((int8)a > (int8)b); | |
2502 | SET_PSR_L (a > b); | |
2503 | trace_output_flag (); | |
2504 | } | |
2505 | ||
2506 | /* cmpw. */ | |
2507 | void | |
2508 | OP_52_8 () | |
2509 | { | |
2510 | uint16 a = (OP[0]); | |
2511 | uint16 b = GPR (OP[1]); | |
2512 | trace_input ("cmpw", OP_CONSTANT4, OP_REG, OP_VOID); | |
2513 | SET_PSR_Z (a == b); | |
2514 | SET_PSR_N ((int16)a > (int16)b); | |
2515 | SET_PSR_L (a > b); | |
2516 | trace_output_flag (); | |
2517 | } | |
2518 | ||
2519 | /* cmpw. */ | |
2520 | void | |
2521 | OP_52B_C () | |
2522 | { | |
2523 | uint16 a = (OP[0]); | |
2524 | uint16 b = GPR (OP[1]); | |
2525 | trace_input ("cmpw", OP_CONSTANT16, OP_REG, OP_VOID); | |
2526 | SET_PSR_Z (a == b); | |
2527 | SET_PSR_N ((int16)a > (int16)b); | |
2528 | SET_PSR_L (a > b); | |
2529 | trace_output_flag (); | |
2530 | } | |
2531 | ||
2532 | /* cmpw. */ | |
2533 | void | |
2534 | OP_53_8 () | |
2535 | { | |
2536 | uint16 a = GPR (OP[0]) ; | |
2537 | uint16 b = GPR (OP[1]) ; | |
2538 | trace_input ("cmpw", OP_REG, OP_REG, OP_VOID); | |
2539 | SET_PSR_Z (a == b); | |
2540 | SET_PSR_N ((int16)a > (int16)b); | |
2541 | SET_PSR_L (a > b); | |
2542 | trace_output_flag (); | |
2543 | } | |
2544 | ||
2545 | /* cmpd. */ | |
2546 | void | |
2547 | OP_56_8 () | |
2548 | { | |
2549 | uint32 a = (OP[0]); | |
2550 | uint32 b = GPR32 (OP[1]); | |
2551 | trace_input ("cmpd", OP_CONSTANT4, OP_REGP, OP_VOID); | |
2552 | SET_PSR_Z (a == b); | |
2553 | SET_PSR_N ((int32)a > (int32)b); | |
2554 | SET_PSR_L (a > b); | |
2555 | trace_output_flag (); | |
2556 | } | |
2557 | ||
2558 | /* cmpd. */ | |
2559 | void | |
2560 | OP_56B_C () | |
2561 | { | |
2562 | uint32 a = (SEXT16(OP[0])); | |
2563 | uint32 b = GPR32 (OP[1]); | |
2564 | trace_input ("cmpd", OP_CONSTANT16, OP_REGP, OP_VOID); | |
2565 | SET_PSR_Z (a == b); | |
2566 | SET_PSR_N ((int32)a > (int32)b); | |
2567 | SET_PSR_L (a > b); | |
2568 | trace_output_flag (); | |
2569 | } | |
2570 | ||
2571 | /* cmpd. */ | |
2572 | void | |
2573 | OP_57_8 () | |
2574 | { | |
2575 | uint32 a = GPR32 (OP[0]) ; | |
2576 | uint32 b = GPR32 (OP[1]) ; | |
2577 | trace_input ("cmpd", OP_REGP, OP_REGP, OP_VOID); | |
2578 | SET_PSR_Z (a == b); | |
2579 | SET_PSR_N ((int32)a > (int32)b); | |
2580 | SET_PSR_L (a > b); | |
2581 | trace_output_flag (); | |
2582 | } | |
2583 | ||
2584 | /* cmpd. */ | |
2585 | void | |
2586 | OP_9_C() | |
2587 | { | |
2588 | uint32 a = (OP[0]); | |
2589 | uint32 b = GPR32 (OP[1]); | |
2590 | trace_input ("cmpd", OP_CONSTANT32, OP_REGP, OP_VOID); | |
2591 | SET_PSR_Z (a == b); | |
2592 | SET_PSR_N ((int32)a > (int32)b); | |
2593 | SET_PSR_L (a > b); | |
2594 | trace_output_flag (); | |
2595 | } | |
2596 | ||
2597 | ||
2598 | /* movb. */ | |
2599 | void | |
2600 | OP_58_8 () | |
2601 | { | |
2602 | uint8 tmp = OP[0] & 0xFF; | |
2603 | trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID); | |
2604 | uint16 a = (GPR (OP[1])) & 0xFF00; | |
2605 | SET_GPR (OP[1], (a | tmp)); | |
2606 | trace_output_16 (tmp); | |
2607 | } | |
2608 | ||
2609 | /* movb. */ | |
2610 | void | |
2611 | OP_58B_C () | |
2612 | { | |
2613 | uint8 tmp = OP[0] & 0xFF; | |
2614 | trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID); | |
2615 | uint16 a = (GPR (OP[1])) & 0xFF00; | |
2616 | SET_GPR (OP[1], (a | tmp)); | |
2617 | trace_output_16 (tmp); | |
2618 | } | |
2619 | ||
2620 | /* movb. */ | |
2621 | void | |
2622 | OP_59_8 () | |
2623 | { | |
2624 | uint8 tmp = (GPR (OP[0])) & 0xFF; | |
2625 | trace_input ("movb", OP_REG, OP_REG, OP_VOID); | |
2626 | uint16 a = (GPR (OP[1])) & 0xFF00; | |
2627 | SET_GPR (OP[1], (a | tmp)); | |
2628 | trace_output_16 (tmp); | |
2629 | } | |
2630 | ||
2631 | /* movw. */ | |
2632 | void | |
2633 | OP_5A_8 () | |
2634 | { | |
2635 | uint16 tmp = OP[0]; | |
2636 | trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID); | |
2637 | SET_GPR (OP[1], (tmp & 0xffff)); | |
2638 | trace_output_16 (tmp); | |
2639 | } | |
2640 | ||
2641 | /* movw. */ | |
2642 | void | |
2643 | OP_5AB_C () | |
2644 | { | |
2645 | int16 tmp = OP[0]; | |
2646 | trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID); | |
2647 | SET_GPR (OP[1], (tmp & 0xffff)); | |
2648 | trace_output_16 (tmp); | |
2649 | } | |
2650 | ||
2651 | /* movw. */ | |
2652 | void | |
2653 | OP_5B_8 () | |
2654 | { | |
2655 | uint16 tmp = GPR (OP[0]); | |
2656 | trace_input ("movw", OP_REG, OP_REGP, OP_VOID); | |
2657 | uint32 a = GPR32 (OP[1]); | |
2658 | a = (a & 0xffff0000) | tmp; | |
2659 | SET_GPR32 (OP[1], a); | |
2660 | trace_output_16 (tmp); | |
2661 | } | |
2662 | ||
2663 | /* movxb. */ | |
2664 | void | |
2665 | OP_5C_8 () | |
2666 | { | |
2667 | uint8 tmp = (GPR (OP[0])) & 0xFF; | |
2668 | trace_input ("movxb", OP_REG, OP_REG, OP_VOID); | |
2669 | SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff)); | |
2670 | trace_output_16 (tmp); | |
2671 | } | |
2672 | ||
2673 | /* movzb. */ | |
2674 | void | |
2675 | OP_5D_8 () | |
2676 | { | |
2677 | uint8 tmp = (GPR (OP[0])) & 0xFF; | |
2678 | trace_input ("movzb", OP_REG, OP_REG, OP_VOID); | |
2679 | SET_GPR (OP[1], tmp); | |
2680 | trace_output_16 (tmp); | |
2681 | } | |
2682 | ||
2683 | /* movxw. */ | |
2684 | void | |
2685 | OP_5E_8 () | |
2686 | { | |
2687 | uint16 tmp = GPR (OP[0]); | |
2688 | trace_input ("movxw", OP_REG, OP_REGP, OP_VOID); | |
2689 | SET_GPR32 (OP[1], SEXT16(tmp)); | |
2690 | trace_output_16 (tmp); | |
2691 | } | |
2692 | ||
2693 | /* movzw. */ | |
2694 | void | |
2695 | OP_5F_8 () | |
2696 | { | |
2697 | uint16 tmp = GPR (OP[0]); | |
2698 | trace_input ("movzw", OP_REG, OP_REGP, OP_VOID); | |
2699 | SET_GPR32 (OP[1], (tmp & 0x0000FFFF)); | |
2700 | trace_output_16 (tmp); | |
2701 | } | |
2702 | ||
2703 | /* movd. */ | |
2704 | void | |
2705 | OP_54_8 () | |
2706 | { | |
2707 | int32 tmp = OP[0]; | |
2708 | trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID); | |
2709 | SET_GPR32 (OP[1], tmp); | |
2710 | trace_output_32 (tmp); | |
2711 | } | |
2712 | ||
2713 | /* movd. */ | |
2714 | void | |
2715 | OP_54B_C () | |
2716 | { | |
2717 | int32 tmp = SEXT16(OP[0]); | |
2718 | trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID); | |
2719 | SET_GPR32 (OP[1], tmp); | |
2720 | trace_output_32 (tmp); | |
2721 | } | |
2722 | ||
2723 | /* movd. */ | |
2724 | void | |
2725 | OP_55_8 () | |
2726 | { | |
2727 | uint32 tmp = GPR32 (OP[0]); | |
2728 | trace_input ("movd", OP_REGP, OP_REGP, OP_VOID); | |
2729 | SET_GPR32 (OP[1], tmp); | |
2730 | trace_output_32 (tmp); | |
2731 | } | |
2732 | ||
2733 | /* movd. */ | |
2734 | void | |
2735 | OP_5_8 () | |
2736 | { | |
2737 | uint32 tmp = OP[0]; | |
2738 | trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID); | |
2739 | SET_GPR32 (OP[1], tmp); | |
2740 | trace_output_32 (tmp); | |
2741 | } | |
2742 | ||
2743 | /* movd. */ | |
2744 | void | |
2745 | OP_7_C () | |
2746 | { | |
2747 | int32 tmp = OP[0]; | |
2748 | trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID); | |
2749 | SET_GPR32 (OP[1], tmp); | |
2750 | trace_output_32 (tmp); | |
2751 | } | |
2752 | ||
2753 | /* loadm. */ | |
2754 | void | |
2755 | OP_14_D () | |
2756 | { | |
2757 | uint32 addr = GPR (0); | |
2758 | uint16 count = OP[0], reg = 2, tmp; | |
2759 | trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID); | |
2760 | if ((addr & 1)) | |
2761 | { | |
2762 | State.exception = SIG_CR16_BUS; | |
2763 | State.pc_changed = 1; /* Don't increment the PC. */ | |
2764 | trace_output_void (); | |
2765 | return; | |
2766 | } | |
2767 | ||
2768 | while (count) | |
2769 | { | |
2770 | tmp = RW (addr); | |
2771 | SET_GPR (reg, tmp); | |
2772 | addr +=2; | |
2773 | --count; | |
2774 | reg++; | |
2775 | if (reg == 6) reg = 8; | |
2776 | }; | |
2777 | ||
2778 | SET_GPR (0, addr); | |
2779 | trace_output_void (); | |
2780 | } | |
2781 | ||
2782 | ||
2783 | /* loadmp. */ | |
2784 | void | |
2785 | OP_15_D () | |
2786 | { | |
2787 | uint32 addr = GPR32 (0); | |
2788 | uint16 count = OP[0], reg = 2, tmp; | |
2789 | trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID); | |
2790 | if ((addr & 1)) | |
2791 | { | |
2792 | State.exception = SIG_CR16_BUS; | |
2793 | State.pc_changed = 1; /* Don't increment the PC. */ | |
2794 | trace_output_void (); | |
2795 | return; | |
2796 | } | |
2797 | ||
2798 | while (count) | |
2799 | { | |
2800 | tmp = RW (addr); | |
2801 | SET_GPR (reg, tmp); | |
2802 | addr +=2; | |
2803 | --count; | |
2804 | reg++; | |
2805 | if (reg == 6) reg = 8; | |
2806 | }; | |
2807 | ||
2808 | SET_GPR32 (0, addr); | |
2809 | trace_output_void (); | |
2810 | } | |
2811 | ||
2812 | ||
2813 | /* loadb. */ | |
2814 | void | |
2815 | OP_88_8 () | |
2816 | { | |
2817 | /* loadb ABS20, REG | |
2818 | * ADDR = zext24(abs20) | remap (ie 0xF00000) | |
2819 | * REG = [ADDR] | |
2820 | * NOTE: remap is | |
2821 | * If (abs20 > 0xEFFFF) the resulting address is logically ORed | |
2822 | * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped | |
2823 | * by the core to 16M-64k to 16M. */ | |
2824 | ||
2825 | uint16 tmp, a = (GPR (OP[1])) & 0xFF00; | |
2826 | uint32 addr = OP[0]; | |
2827 | trace_input ("loadb", OP_ABS20, OP_REG, OP_VOID); | |
2828 | if (addr > 0xEFFFF) addr |= 0xF00000; | |
2829 | tmp = (RB (addr)); | |
2830 | SET_GPR (OP[1], (a | tmp)); | |
2831 | trace_output_16 (tmp); | |
2832 | } | |
2833 | ||
2834 | /* loadb. */ | |
2835 | void | |
2836 | OP_127_14 () | |
2837 | { | |
2838 | /* loadb ABS24, REG | |
2839 | * ADDR = abs24 | |
2840 | * REGR = [ADDR]. */ | |
2841 | ||
2842 | uint16 tmp, a = (GPR (OP[1])) & 0xFF00; | |
2843 | uint32 addr = OP[0]; | |
2844 | trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID); | |
2845 | tmp = (RB (addr)); | |
2846 | SET_GPR (OP[1], (a | tmp)); | |
2847 | trace_output_16 (tmp); | |
2848 | } | |
2849 | ||
2850 | /* loadb. */ | |
2851 | void | |
2852 | OP_45_7 () | |
2853 | { | |
2854 | /* loadb [Rindex]ABS20 REG | |
2855 | * ADDR = Rindex + zext24(disp20) | |
2856 | * REGR = [ADDR]. */ | |
2857 | ||
2858 | uint32 addr; | |
2859 | uint16 tmp, a = (GPR (OP[2])) & 0xFF00; | |
2860 | trace_input ("loadb", OP_R_INDEX8_ABS20, OP_REG, OP_VOID); | |
2861 | ||
2862 | if (OP[0] == 0) | |
2863 | addr = (GPR32 (12)) + OP[1]; | |
2864 | else | |
2865 | addr = (GPR32 (13)) + OP[1]; | |
2866 | ||
2867 | tmp = (RB (addr)); | |
2868 | SET_GPR (OP[2], (a | tmp)); | |
2869 | trace_output_16 (tmp); | |
2870 | } | |
2871 | ||
2872 | ||
2873 | /* loadb. */ | |
2874 | void | |
2875 | OP_B_4 () | |
2876 | { | |
2877 | /* loadb DIPS4(REGP) REG | |
2878 | * ADDR = RPBASE + zext24(DISP4) | |
2879 | * REG = [ADDR]. */ | |
2880 | uint16 tmp, a = (GPR (OP[2])) & 0xFF00; | |
2881 | uint32 addr = (GPR32 (OP[1])) + OP[0]; | |
2882 | trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID); | |
2883 | tmp = (RB (addr)); | |
2884 | SET_GPR (OP[2], (a | tmp)); | |
2885 | trace_output_16 (tmp); | |
2886 | } | |
2887 | ||
2888 | /* loadb. */ | |
2889 | void | |
2890 | OP_BE_8 () | |
2891 | { | |
2892 | /* loadb [Rindex]disp0(RPbasex) REG | |
2893 | * ADDR = Rpbasex + Rindex | |
2894 | * REGR = [ADDR] */ | |
2895 | ||
2896 | uint32 addr; | |
2897 | uint16 tmp, a = (GPR (OP[3])) & 0xFF00; | |
2898 | trace_input ("loadb", OP_RP_INDEX_DISP0, OP_REG, OP_VOID); | |
2899 | ||
2900 | addr = (GPR32 (OP[2])) + OP[1]; | |
2901 | ||
2902 | if (OP[0] == 0) | |
2903 | addr = (GPR32 (12)) + addr; | |
2904 | else | |
2905 | addr = (GPR32 (13)) + addr; | |
2906 | ||
2907 | tmp = (RB (addr)); | |
2908 | SET_GPR (OP[3], (a | tmp)); | |
2909 | trace_output_16 (tmp); | |
2910 | } | |
2911 | ||
2912 | /* loadb. */ | |
2913 | void | |
2914 | OP_219_A () | |
2915 | { | |
2916 | /* loadb [Rindex]disp14(RPbasex) REG | |
2917 | * ADDR = Rpbasex + Rindex + zext24(disp14) | |
2918 | * REGR = [ADDR] */ | |
2919 | ||
2920 | uint32 addr; | |
2921 | uint16 tmp, a = (GPR (OP[3])) & 0xFF00; | |
2922 | ||
2923 | addr = (GPR32 (OP[2])) + OP[1]; | |
2924 | ||
2925 | if (OP[0] == 0) | |
2926 | addr = (GPR32 (12)) + addr; | |
2927 | else | |
2928 | addr = (GPR32 (13)) + addr; | |
2929 | ||
2930 | trace_input ("loadb", OP_RP_INDEX_DISP14, OP_REG, OP_VOID); | |
2931 | tmp = (RB (addr)); | |
2932 | SET_GPR (OP[3], (a | tmp)); | |
2933 | trace_output_16 (tmp); | |
2934 | } | |
2935 | ||
2936 | ||
2937 | /* loadb. */ | |
2938 | void | |
2939 | OP_184_14 () | |
2940 | { | |
2941 | /* loadb DISPE20(REG) REG | |
2942 | * zext24(Rbase) + zext24(dispe20) | |
2943 | * REG = [ADDR] */ | |
2944 | ||
2945 | uint16 tmp,a = (GPR (OP[2])) & 0xFF00; | |
2946 | uint32 addr = OP[0] + (GPR (OP[1])); | |
2947 | trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID); | |
2948 | tmp = (RB (addr)); | |
2949 | SET_GPR (OP[2], (a | tmp)); | |
2950 | trace_output_16 (tmp); | |
2951 | } | |
2952 | ||
2953 | /* loadb. */ | |
2954 | void | |
2955 | OP_124_14 () | |
2956 | { | |
2957 | /* loadb DISP20(REG) REG | |
2958 | * ADDR = zext24(Rbase) + zext24(disp20) | |
2959 | * REG = [ADDR] */ | |
2960 | ||
2961 | uint16 tmp,a = (GPR (OP[2])) & 0xFF00; | |
2962 | uint32 addr = OP[0] + (GPR (OP[1])); | |
2963 | trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID); | |
2964 | tmp = (RB (addr)); | |
2965 | SET_GPR (OP[2], (a | tmp)); | |
2966 | trace_output_16 (tmp); | |
2967 | } | |
2968 | ||
2969 | /* loadb. */ | |
2970 | void | |
2971 | OP_BF_8 () | |
2972 | { | |
2973 | /* loadb disp16(REGP) REG | |
2974 | * ADDR = RPbase + zext24(disp16) | |
2975 | * REGR = [ADDR] */ | |
2976 | ||
2977 | uint16 tmp,a = (GPR (OP[2])) & 0xFF00; | |
2978 | uint32 addr = (GPR32 (OP[1])) + OP[0]; | |
2979 | trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID); | |
2980 | tmp = (RB (addr)); | |
2981 | SET_GPR (OP[2], (a | tmp)); | |
2982 | trace_output_16 (tmp); | |
2983 | } | |
2984 | ||
2985 | /* loadb. */ | |
2986 | void | |
2987 | OP_125_14 () | |
2988 | { | |
2989 | /* loadb disp20(REGP) REG | |
2990 | * ADDR = RPbase + zext24(disp20) | |
2991 | * REGR = [ADDR] */ | |
2992 | uint16 tmp,a = (GPR (OP[2])) & 0xFF00; | |
2993 | uint32 addr = (GPR32 (OP[1])) + OP[0]; | |
2994 | trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID); | |
2995 | tmp = (RB (addr)); | |
2996 | SET_GPR (OP[2], (a | tmp)); | |
2997 | trace_output_16 (tmp); | |
2998 | } | |
2999 | ||
3000 | ||
3001 | /* loadb. */ | |
3002 | void | |
3003 | OP_185_14 () | |
3004 | { | |
3005 | /* loadb -disp20(REGP) REG | |
3006 | * ADDR = RPbase + zext24(-disp20) | |
3007 | * REGR = [ADDR] */ | |
3008 | uint16 tmp,a = (GPR (OP[2])) & 0xFF00; | |
3009 | uint32 addr = (GPR32 (OP[1])) + OP[1]; | |
3010 | trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID); | |
3011 | tmp = (RB (addr)); | |
3012 | SET_GPR (OP[2], (a | tmp)); | |
3013 | trace_output_16 (tmp); | |
3014 | } | |
3015 | ||
3016 | /* loadb. */ | |
3017 | void | |
3018 | OP_126_14 () | |
3019 | { | |
3020 | /* loadb [Rindex]disp20(RPbasexb) REG | |
3021 | * ADDR = RPbasex + Rindex + zext24(disp20) | |
3022 | * REGR = [ADDR] */ | |
3023 | ||
3024 | uint32 addr; | |
3025 | uint16 tmp, a = (GPR (OP[3])) & 0xFF00; | |
3026 | trace_input ("loadb", OP_RP_INDEX_DISP20, OP_REG, OP_VOID); | |
3027 | ||
3028 | addr = (GPR32 (OP[2])) + OP[1]; | |
3029 | ||
3030 | if (OP[0] == 0) | |
3031 | addr = (GPR32 (12)) + addr; | |
3032 | else | |
3033 | addr = (GPR32 (13)) + addr; | |
3034 | ||
3035 | tmp = (RB (addr)); | |
3036 | SET_GPR (OP[3], (a | tmp)); | |
3037 | trace_output_16 (tmp); | |
3038 | } | |
3039 | ||
3040 | ||
3041 | /* loadw. */ | |
3042 | void | |
3043 | OP_89_8 () | |
3044 | { | |
3045 | /* loadw ABS20, REG | |
3046 | * ADDR = zext24(abs20) | remap | |
3047 | * REGR = [ADDR] | |
3048 | * NOTE: remap is | |
3049 | * If (abs20 > 0xEFFFF) the resulting address is logically ORed | |
3050 | * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped | |
3051 | * by the core to 16M-64k to 16M. */ | |
3052 | ||
3053 | uint16 tmp; | |
3054 | uint32 addr = OP[0]; | |
3055 | trace_input ("loadw", OP_ABS20, OP_REG, OP_VOID); | |
3056 | if (addr > 0xEFFFF) addr |= 0xF00000; | |
3057 | tmp = (RW (addr)); | |
3058 | SET_GPR (OP[1], tmp); | |
3059 | trace_output_16 (tmp); | |
3060 | } | |
3061 | ||
3062 | ||
3063 | /* loadw. */ | |
3064 | void | |
3065 | OP_12F_14 () | |
3066 | { | |
3067 | /* loadw ABS24, REG | |
3068 | * ADDR = abs24 | |
3069 | * REGR = [ADDR] */ | |
3070 | uint16 tmp; | |
3071 | uint32 addr = OP[0]; | |
3072 | trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID); | |
3073 | tmp = (RW (addr)); | |
3074 | SET_GPR (OP[1], tmp); | |
3075 | trace_output_16 (tmp); | |
3076 | } | |
3077 | ||
3078 | /* loadw. */ | |
3079 | void | |
3080 | OP_47_7 () | |
3081 | { | |
3082 | /* loadw [Rindex]ABS20 REG | |
3083 | * ADDR = Rindex + zext24(disp20) | |
3084 | * REGR = [ADDR] */ | |
3085 | ||
3086 | uint32 addr; | |
3087 | uint16 tmp; | |
3088 | trace_input ("loadw", OP_R_INDEX8_ABS20, OP_REG, OP_VOID); | |
3089 | ||
3090 | if (OP[0] == 0) | |
3091 | addr = (GPR32 (12)) + OP[1]; | |
3092 | else | |
3093 | addr = (GPR32 (13)) + OP[1]; | |
3094 | ||
3095 | tmp = (RW (addr)); | |
3096 | SET_GPR (OP[2], tmp); | |
3097 | trace_output_16 (tmp); | |
3098 | } | |
3099 | ||
3100 | ||
3101 | /* loadw. */ | |
3102 | void | |
3103 | OP_9_4 () | |
3104 | { | |
3105 | /* loadw DIPS4(REGP) REGP | |
3106 | * ADDR = RPBASE + zext24(DISP4) | |
3107 | * REGP = [ADDR]. */ | |
3108 | uint16 tmp; | |
3109 | uint32 addr, a; | |
3110 | trace_input ("loadw", OP_RP_BASE_DISP4, OP_REG, OP_VOID); | |
3111 | addr = (GPR32 (OP[1])) + OP[0]; | |
3112 | tmp = (RW (addr)); | |
3113 | if (OP[2] > 11) | |
3114 | { | |
3115 | a = (GPR32 (OP[2])) & 0xffff0000; | |
3116 | SET_GPR32 (OP[2], (a | tmp)); | |
3117 | } | |
3118 | else | |
3119 | SET_GPR (OP[2], tmp); | |
3120 | ||
3121 | trace_output_16 (tmp); | |
3122 | } | |
3123 | ||
3124 | ||
3125 | /* loadw. */ | |
3126 | void | |
3127 | OP_9E_8 () | |
3128 | { | |
3129 | /* loadw [Rindex]disp0(RPbasex) REG | |
3130 | * ADDR = Rpbasex + Rindex | |
3131 | * REGR = [ADDR] */ | |
3132 | ||
3133 | uint32 addr; | |
3134 | uint16 tmp; | |
3135 | trace_input ("loadw", OP_RP_INDEX_DISP0, OP_REG, OP_VOID); | |
3136 | ||
3137 | addr = (GPR32 (OP[2])) + OP[1]; | |
3138 | ||
3139 | if (OP[0] == 0) | |
3140 | addr = (GPR32 (12)) + addr; | |
3141 | else | |
3142 | addr = (GPR32 (13)) + addr; | |
3143 | ||
3144 | tmp = RW (addr); | |
3145 | SET_GPR (OP[3], tmp); | |
3146 | trace_output_16 (tmp); | |
3147 | } | |
3148 | ||
3149 | ||
3150 | /* loadw. */ | |
3151 | void | |
3152 | OP_21B_A () | |
3153 | { | |
3154 | /* loadw [Rindex]disp14(RPbasex) REG | |
3155 | * ADDR = Rpbasex + Rindex + zext24(disp14) | |
3156 | * REGR = [ADDR] */ | |
3157 | ||
3158 | uint32 addr; | |
3159 | uint16 tmp; | |
3160 | trace_input ("loadw", OP_RP_INDEX_DISP14, OP_REG, OP_VOID); | |
3161 | addr = (GPR32 (OP[2])) + OP[1]; | |
3162 | ||
3163 | if (OP[0] == 0) | |
3164 | addr = (GPR32 (12)) + addr; | |
3165 | else | |
3166 | addr = (GPR32 (13)) + addr; | |
3167 | ||
3168 | tmp = (RW (addr)); | |
3169 | SET_GPR (OP[3], tmp); | |
3170 | trace_output_16 (tmp); | |
3171 | } | |
3172 | ||
3173 | /* loadw. */ | |
3174 | void | |
3175 | OP_18C_14 () | |
3176 | { | |
3177 | /* loadw dispe20(REG) REGP | |
3178 | * REGP = [DISPE20+[REG]] */ | |
3179 | ||
3180 | uint16 tmp; | |
3181 | uint32 addr, a; | |
3182 | trace_input ("loadw", OP_R_BASE_DISPE20, OP_REGP, OP_VOID); | |
3183 | addr = OP[0] + (GPR (OP[1])); | |
3184 | tmp = (RW (addr)); | |
3185 | if (OP[2] > 11) | |
3186 | { | |
3187 | a = (GPR32 (OP[2])) & 0xffff0000; | |
3188 | SET_GPR32 (OP[2], (a | tmp)); | |
3189 | } | |
3190 | else | |
3191 | SET_GPR (OP[2], tmp); | |
3192 | ||
3193 | trace_output_16 (tmp); | |
3194 | } | |
3195 | ||
3196 | ||
3197 | /* loadw. */ | |
3198 | void | |
3199 | OP_12C_14 () | |
3200 | { | |
3201 | /* loadw DISP20(REG) REGP | |
3202 | * ADDR = zext24(Rbase) + zext24(disp20) | |
3203 | * REGP = [ADDR] */ | |
3204 | ||
3205 | uint16 tmp; | |
3206 | uint32 addr, a; | |
3207 | trace_input ("loadw", OP_R_BASE_DISP20, OP_REGP, OP_VOID); | |
3208 | addr = OP[0] + (GPR (OP[1])); | |
3209 | tmp = (RW (addr)); | |
3210 | if (OP[2] > 11) | |
3211 | { | |
3212 | a = (GPR32 (OP[2])) & 0xffff0000; | |
3213 | SET_GPR32 (OP[2], (a | tmp)); | |
3214 | } | |
3215 | else | |
3216 | SET_GPR (OP[2], tmp); | |
3217 | ||
3218 | trace_output_16 (tmp); | |
3219 | } | |
3220 | ||
3221 | /* loadw. */ | |
3222 | void | |
3223 | OP_9F_8 () | |
3224 | { | |
3225 | /* loadw disp16(REGP) REGP | |
3226 | * ADDR = RPbase + zext24(disp16) | |
3227 | * REGP = [ADDR] */ | |
3228 | uint16 tmp; | |
3229 | uint32 addr, a; | |
3230 | trace_input ("loadw", OP_RP_BASE_DISP16, OP_REGP, OP_VOID); | |
3231 | addr = (GPR32 (OP[1])) + OP[0]; | |
3232 | tmp = (RW (addr)); | |
3233 | if (OP[2] > 11) | |
3234 | { | |
3235 | a = (GPR32 (OP[2])) & 0xffff0000; | |
3236 | SET_GPR32 (OP[2], (a | tmp)); | |
3237 | } | |
3238 | else | |
3239 | SET_GPR (OP[2], tmp); | |
3240 | ||
3241 | trace_output_16 (tmp); | |
3242 | } | |
3243 | ||
3244 | /* loadw. */ | |
3245 | void | |
3246 | OP_12D_14 () | |
3247 | { | |
3248 | /* loadw disp20(REGP) REGP | |
3249 | * ADDR = RPbase + zext24(disp20) | |
3250 | * REGP = [ADDR] */ | |
3251 | uint16 tmp; | |
3252 | uint32 addr, a; | |
3253 | trace_input ("loadw", OP_RP_BASE_DISP20, OP_REG, OP_VOID); | |
3254 | addr = (GPR32 (OP[1])) + OP[0]; | |
3255 | tmp = (RW (addr)); | |
3256 | if (OP[2] > 11) | |
3257 | { | |
3258 | a = (GPR32 (OP[2])) & 0xffff0000; | |
3259 | SET_GPR32 (OP[2], (a | tmp)); | |
3260 | } | |
3261 | else | |
3262 | SET_GPR (OP[2], tmp); | |
3263 | ||
3264 | trace_output_16 (tmp); | |
3265 | } | |
3266 | ||
3267 | /* loadw. */ | |
3268 | void | |
3269 | OP_18D_14 () | |
3270 | { | |
3271 | /* loadw -disp20(REGP) REG | |
3272 | * ADDR = RPbase + zext24(-disp20) | |
3273 | * REGR = [ADDR] */ | |
3274 | ||
3275 | uint16 tmp; | |
3276 | uint32 addr, a; | |
3277 | trace_input ("loadw", OP_RP_BASE_DISPE20, OP_REG, OP_VOID); | |
3278 | addr = (GPR32 (OP[1])) + OP[0]; | |
3279 | tmp = (RB (addr)); | |
3280 | if (OP[2] > 11) | |
3281 | { | |
3282 | a = (GPR32 (OP[2])) & 0xffff0000; | |
3283 | SET_GPR32 (OP[2], (a | tmp)); | |
3284 | } | |
3285 | else | |
3286 | SET_GPR (OP[2], tmp); | |
3287 | ||
3288 | trace_output_16 (tmp); | |
3289 | } | |
3290 | ||
3291 | ||
3292 | /* loadw. */ | |
3293 | void | |
3294 | OP_12E_14 () | |
3295 | { | |
3296 | /* loadw [Rindex]disp20(RPbasexb) REG | |
3297 | * ADDR = RPbasex + Rindex + zext24(disp20) | |
3298 | * REGR = [ADDR] */ | |
3299 | ||
3300 | uint32 addr; | |
3301 | uint16 tmp; | |
3302 | trace_input ("loadw", OP_RP_INDEX_DISP20, OP_REG, OP_VOID); | |
3303 | ||
3304 | if (OP[0] == 0) | |
3305 | addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2])); | |
3306 | else | |
3307 | addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2])); | |
3308 | ||
3309 | tmp = (RW (addr)); | |
3310 | SET_GPR (OP[3], tmp); | |
3311 | trace_output_16 (tmp); | |
3312 | } | |
3313 | ||
3314 | ||
3315 | /* loadd. */ | |
3316 | void | |
3317 | OP_87_8 () | |
3318 | { | |
3319 | /* loadd ABS20, REGP | |
3320 | * ADDR = zext24(abs20) | remap | |
3321 | * REGP = [ADDR] | |
3322 | * NOTE: remap is | |
3323 | * If (abs20 > 0xEFFFF) the resulting address is logically ORed | |
3324 | * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped | |
3325 | * by the core to 16M-64k to 16M. */ | |
3326 | ||
3327 | uint32 addr, tmp; | |
3328 | addr = OP[0]; | |
3329 | trace_input ("loadd", OP_ABS20, OP_REGP, OP_VOID); | |
3330 | if (addr > 0xEFFFF) addr |= 0xF00000; | |
3331 | tmp = RLW (addr); | |
3332 | tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff); | |
3333 | SET_GPR32 (OP[1], tmp); | |
3334 | trace_output_32 (tmp); | |
3335 | } | |
3336 | ||
3337 | /* loadd. */ | |
3338 | void | |
3339 | OP_12B_14 () | |
3340 | { | |
3341 | /* loadd ABS24, REGP | |
3342 | * ADDR = abs24 | |
3343 | * REGP = [ADDR] */ | |
3344 | ||
3345 | uint32 addr = OP[0]; | |
3346 | uint32 tmp; | |
3347 | trace_input ("loadd", OP_ABS24, OP_REGP, OP_VOID); | |
3348 | tmp = RLW (addr); | |
3349 | tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); | |
3350 | SET_GPR32 (OP[1],tmp); | |
3351 | trace_output_32 (tmp); | |
3352 | } | |
3353 | ||
3354 | ||
3355 | /* loadd. */ | |
3356 | void | |
3357 | OP_46_7 () | |
3358 | { | |
3359 | /* loadd [Rindex]ABS20 REGP | |
3360 | * ADDR = Rindex + zext24(disp20) | |
3361 | * REGP = [ADDR] */ | |
3362 | ||
3363 | uint32 addr, tmp; | |
3364 | trace_input ("loadd", OP_R_INDEX8_ABS20, OP_REGP, OP_VOID); | |
3365 | ||
3366 | if (OP[0] == 0) | |
3367 | addr = (GPR32 (12)) + OP[1]; | |
3368 | else | |
3369 | addr = (GPR32 (13)) + OP[1]; | |
3370 | ||
3371 | tmp = RLW (addr); | |
3372 | tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); | |
3373 | SET_GPR32 (OP[2], tmp); | |
3374 | trace_output_32 (tmp); | |
3375 | } | |
3376 | ||
3377 | ||
3378 | /* loadd. */ | |
3379 | void | |
3380 | OP_A_4 () | |
3381 | { | |
3382 | /* loadd dips4(regp) REGP | |
3383 | * ADDR = Rpbase + zext24(disp4) | |
3384 | * REGP = [ADDR] */ | |
3385 | ||
3386 | uint32 tmp, addr = (GPR32 (OP[1])) + OP[0]; | |
3387 | trace_input ("loadd", OP_RP_BASE_DISP4, OP_REGP, OP_VOID); | |
3388 | tmp = RLW (addr); | |
3389 | tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); | |
3390 | SET_GPR32 (OP[2], tmp); | |
3391 | trace_output_32 (tmp); | |
3392 | } | |
3393 | ||
3394 | ||
3395 | /* loadd. */ | |
3396 | void | |
3397 | OP_AE_8 () | |
3398 | { | |
3399 | /* loadd [Rindex]disp0(RPbasex) REGP | |
3400 | * ADDR = Rpbasex + Rindex | |
3401 | * REGP = [ADDR] */ | |
3402 | ||
3403 | uint32 addr, tmp; | |
3404 | trace_input ("loadd", OP_RP_INDEX_DISP0, OP_REGP, OP_VOID); | |
3405 | ||
3406 | if (OP[0] == 0) | |
3407 | addr = (GPR32 (12)) + (GPR32 (OP[2])) + OP[1]; | |
3408 | else | |
3409 | addr = (GPR32 (13)) + (GPR32 (OP[2])) + OP[1]; | |
3410 | ||
3411 | tmp = RLW (addr); | |
3412 | tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); | |
3413 | SET_GPR32 (OP[3], tmp); | |
3414 | trace_output_32 (tmp); | |
3415 | } | |
3416 | ||
3417 | ||
3418 | /* loadd. */ | |
3419 | void | |
3420 | OP_21A_A () | |
3421 | { | |
3422 | /* loadd [Rindex]disp14(RPbasex) REGP | |
3423 | * ADDR = Rpbasex + Rindex + zext24(disp14) | |
3424 | * REGR = [ADDR] */ | |
3425 | ||
3426 | uint32 addr, tmp; | |
3427 | trace_input ("loadd", OP_RP_INDEX_DISP14, OP_REGP, OP_VOID); | |
3428 | ||
3429 | if (OP[0] == 0) | |
3430 | addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2])); | |
3431 | else | |
3432 | addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2])); | |
3433 | ||
3434 | tmp = RLW (addr); | |
3435 | tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); | |
3436 | SET_GPR (OP[3],tmp); | |
3437 | trace_output_32 (tmp); | |
3438 | } | |
3439 | ||
3440 | ||
3441 | /* loadd. */ | |
3442 | void | |
3443 | OP_188_14 () | |
3444 | { | |
3445 | /* loadd dispe20(REG) REG | |
3446 | * zext24(Rbase) + zext24(dispe20) | |
3447 | * REG = [ADDR] */ | |
3448 | ||
3449 | uint32 tmp, addr = OP[0] + (GPR (OP[1])); | |
3450 | trace_input ("loadd", OP_R_BASE_DISPE20, OP_REGP, OP_VOID); | |
3451 | tmp = RLW (addr); | |
3452 | tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); | |
3453 | SET_GPR32 (OP[2], tmp); | |
3454 | trace_output_32 (tmp); | |
3455 | } | |
3456 | ||
3457 | ||
3458 | /* loadd. */ | |
3459 | void | |
3460 | OP_128_14 () | |
3461 | { | |
3462 | /* loadd DISP20(REG) REG | |
3463 | * ADDR = zext24(Rbase) + zext24(disp20) | |
3464 | * REG = [ADDR] */ | |
3465 | ||
3466 | uint32 tmp, addr = OP[0] + (GPR (OP[1])); | |
3467 | trace_input ("loadd", OP_R_BASE_DISP20, OP_REGP, OP_VOID); | |
3468 | tmp = RLW (addr); | |
3469 | tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); | |
3470 | SET_GPR32 (OP[2], tmp); | |
3471 | trace_output_32 (tmp); | |
3472 | } | |
3473 | ||
3474 | /* loadd. */ | |
3475 | void | |
3476 | OP_AF_8 () | |
3477 | { | |
3478 | /* loadd disp16(REGP) REGP | |
3479 | * ADDR = RPbase + zext24(disp16) | |
3480 | * REGR = [ADDR] */ | |
3481 | uint32 tmp, addr = OP[0] + (GPR32 (OP[1])); | |
3482 | trace_input ("loadd", OP_RP_BASE_DISP16, OP_REGP, OP_VOID); | |
3483 | tmp = RLW (addr); | |
3484 | tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); | |
3485 | SET_GPR32 (OP[2], tmp); | |
3486 | trace_output_32 (tmp); | |
3487 | } | |
3488 | ||
3489 | ||
3490 | /* loadd. */ | |
3491 | void | |
3492 | OP_129_14 () | |
3493 | { | |
3494 | /* loadd disp20(REGP) REGP | |
3495 | * ADDR = RPbase + zext24(disp20) | |
3496 | * REGP = [ADDR] */ | |
3497 | uint32 tmp, addr = OP[0] + (GPR32 (OP[1])); | |
3498 | trace_input ("loadd", OP_RP_BASE_DISP20, OP_REGP, OP_VOID); | |
3499 | tmp = RLW (addr); | |
3500 | tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); | |
3501 | SET_GPR32 (OP[2], tmp); | |
3502 | trace_output_32 (tmp); | |
3503 | } | |
3504 | ||
3505 | /* loadd. */ | |
3506 | void | |
3507 | OP_189_14 () | |
3508 | { | |
3509 | /* loadd -disp20(REGP) REGP | |
3510 | * ADDR = RPbase + zext24(-disp20) | |
3511 | * REGP = [ADDR] */ | |
3512 | ||
3513 | uint32 tmp, addr = OP[0] + (GPR32 (OP[1])); | |
3514 | trace_input ("loadd", OP_RP_BASE_DISPE20, OP_REGP, OP_VOID); | |
3515 | tmp = RLW (addr); | |
3516 | tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); | |
3517 | SET_GPR32 (OP[2], tmp); | |
3518 | trace_output_32 (tmp); | |
3519 | } | |
3520 | ||
3521 | /* loadd. */ | |
3522 | void | |
3523 | OP_12A_14 () | |
3524 | { | |
3525 | /* loadd [Rindex]disp20(RPbasexb) REGP | |
3526 | * ADDR = RPbasex + Rindex + zext24(disp20) | |
3527 | * REGP = [ADDR] */ | |
3528 | ||
3529 | uint32 addr, tmp; | |
3530 | trace_input ("loadd", OP_RP_INDEX_DISP20, OP_REGP, OP_VOID); | |
3531 | ||
3532 | if (OP[0] == 0) | |
3533 | addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2])); | |
3534 | else | |
3535 | addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2])); | |
3536 | ||
3537 | tmp = RLW (addr); | |
3538 | tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff); | |
3539 | SET_GPR32 (OP[3], tmp); | |
3540 | trace_output_32 (tmp); | |
3541 | } | |
3542 | ||
3543 | ||
3544 | /* storb. */ | |
3545 | void | |
3546 | OP_C8_8 () | |
3547 | { | |
3548 | /* storb REG, ABS20 | |
3549 | * ADDR = zext24(abs20) | remap | |
3550 | * [ADDR] = REGR | |
3551 | * NOTE: remap is | |
3552 | * If (abs20 > 0xEFFFF) the resulting address is logically ORed | |
3553 | * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped | |
3554 | * by the core to 16M-64k to 16M. */ | |
3555 | ||
3556 | uint8 a = ((GPR (OP[0])) & 0xff); | |
3557 | uint32 addr = OP[1]; | |
3558 | trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID); | |
3559 | SB (addr, a); | |
3560 | trace_output_32 (addr); | |
3561 | } | |
3562 | ||
3563 | /* storb. */ | |
3564 | void | |
3565 | OP_137_14 () | |
3566 | { | |
3567 | /* storb REG, ABS24 | |
3568 | * ADDR = abs24 | |
3569 | * [ADDR] = REGR. */ | |
3570 | ||
3571 | uint8 a = ((GPR (OP[0])) & 0xff); | |
3572 | uint32 addr = OP[1]; | |
3573 | trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID); | |
3574 | SB (addr, a); | |
3575 | trace_output_32 (addr); | |
3576 | } | |
3577 | ||
3578 | /* storb. */ | |
3579 | void | |
3580 | OP_65_7 () | |
3581 | { | |
3582 | /* storb REG, [Rindex]ABS20 | |
3583 | * ADDR = Rindex + zext24(disp20) | |
3584 | * [ADDR] = REGR */ | |
3585 | ||
3586 | uint32 addr; | |
3587 | uint8 a = ((GPR (OP[0])) & 0xff); | |
3588 | trace_input ("storb", OP_REG, OP_R_INDEX8_ABS20, OP_VOID); | |
3589 | ||
3590 | if (OP[1] == 0) | |
3591 | addr = (GPR32 (12)) + OP[2]; | |
3592 | else | |
3593 | addr = (GPR32 (13)) + OP[2]; | |
3594 | ||
3595 | SB (addr, a); | |
3596 | trace_output_32 (addr); | |
3597 | } | |
3598 | ||
3599 | /* storb. */ | |
3600 | void | |
3601 | OP_F_4 () | |
3602 | { | |
3603 | /* storb REG, DIPS4(REGP) | |
3604 | * ADDR = RPBASE + zext24(DISP4) | |
3605 | * [ADDR] = REG. */ | |
3606 | ||
3607 | uint16 a = ((GPR (OP[0])) & 0xff); | |
3608 | trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID); | |
3609 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3610 | SB (addr, a); | |
3611 | trace_output_32 (addr); | |
3612 | } | |
3613 | ||
3614 | /* storb. */ | |
3615 | void | |
3616 | OP_FE_8 () | |
3617 | { | |
3618 | /* storb [Rindex]disp0(RPbasex) REG | |
3619 | * ADDR = Rpbasex + Rindex | |
3620 | * [ADDR] = REGR */ | |
3621 | ||
3622 | uint32 addr; | |
3623 | uint8 a = ((GPR (OP[0])) & 0xff); | |
3624 | trace_input ("storb", OP_REG, OP_RP_INDEX_DISP0, OP_VOID); | |
3625 | ||
3626 | if (OP[1] == 0) | |
3627 | addr = (GPR32 (12)) + (GPR32 (OP[3])) + OP[2]; | |
3628 | else | |
3629 | addr = (GPR32 (13)) + (GPR32 (OP[3])) + OP[2]; | |
3630 | ||
3631 | SB (addr, a); | |
3632 | trace_output_32 (addr); | |
3633 | } | |
3634 | ||
3635 | /* storb. */ | |
3636 | void | |
3637 | OP_319_A () | |
3638 | { | |
3639 | /* storb REG, [Rindex]disp14(RPbasex) | |
3640 | * ADDR = Rpbasex + Rindex + zext24(disp14) | |
3641 | * [ADDR] = REGR */ | |
3642 | ||
3643 | uint8 a = ((GPR (OP[0])) & 0xff); | |
3644 | trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID); | |
3645 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3646 | SB (addr, a); | |
3647 | trace_output_32 (addr); | |
3648 | } | |
3649 | ||
3650 | /* storb. */ | |
3651 | void | |
3652 | OP_194_14 () | |
3653 | { | |
3654 | /* storb REG, DISPE20(REG) | |
3655 | * zext24(Rbase) + zext24(dispe20) | |
3656 | * [ADDR] = REG */ | |
3657 | ||
3658 | uint8 a = ((GPR (OP[0])) & 0xff); | |
3659 | trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID); | |
3660 | uint32 addr = OP[1] + (GPR (OP[2])); | |
3661 | SB (addr, a); | |
3662 | trace_output_32 (addr); | |
3663 | } | |
3664 | ||
3665 | /* storb. */ | |
3666 | void | |
3667 | OP_134_14 () | |
3668 | { | |
3669 | /* storb REG, DISP20(REG) | |
3670 | * ADDR = zext24(Rbase) + zext24(disp20) | |
3671 | * [ADDR] = REG */ | |
3672 | ||
3673 | uint8 a = (GPR (OP[0]) & 0xff); | |
3674 | trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID); | |
3675 | uint32 addr = OP[1] + (GPR (OP[2])); | |
3676 | SB (addr, a); | |
3677 | trace_output_32 (addr); | |
3678 | } | |
3679 | ||
3680 | /* storb. */ | |
3681 | void | |
3682 | OP_FF_8 () | |
3683 | { | |
3684 | /* storb REG, disp16(REGP) | |
3685 | * ADDR = RPbase + zext24(disp16) | |
3686 | * [ADDR] = REGP */ | |
3687 | ||
3688 | uint8 a = ((GPR (OP[0])) & 0xff); | |
3689 | trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID); | |
3690 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3691 | SB (addr, a); | |
3692 | trace_output_32 (addr); | |
3693 | } | |
3694 | ||
3695 | /* storb. */ | |
3696 | void | |
3697 | OP_135_14 () | |
3698 | { | |
3699 | /* storb REG, disp20(REGP) | |
3700 | * ADDR = RPbase + zext24(disp20) | |
3701 | * [ADDR] = REGP */ | |
3702 | ||
3703 | uint8 a = ((GPR (OP[0])) & 0xff); | |
3704 | trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID); | |
3705 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3706 | SB (addr, a); | |
3707 | trace_output_32 (addr); | |
3708 | } | |
3709 | ||
3710 | /* storb. */ | |
3711 | void | |
3712 | OP_195_14 () | |
3713 | { | |
3714 | /* storb REG, -disp20(REGP) | |
3715 | * ADDR = RPbase + zext24(-disp20) | |
3716 | * [ADDR] = REGP */ | |
3717 | ||
3718 | uint8 a = (GPR (OP[0]) & 0xff); | |
3719 | trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID); | |
3720 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3721 | SB (addr, a); | |
3722 | trace_output_32 (addr); | |
3723 | } | |
3724 | ||
3725 | /* storb. */ | |
3726 | void | |
3727 | OP_136_14 () | |
3728 | { | |
3729 | /* storb REG, [Rindex]disp20(RPbase) | |
3730 | * ADDR = RPbasex + Rindex + zext24(disp20) | |
3731 | * [ADDR] = REGP */ | |
3732 | ||
3733 | uint8 a = (GPR (OP[0])) & 0xff; | |
3734 | trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID); | |
3735 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3736 | SB (addr, a); | |
3737 | trace_output_32 (addr); | |
3738 | } | |
3739 | ||
3740 | /* STR_IMM instructions. */ | |
3741 | /* storb . */ | |
3742 | void | |
3743 | OP_81_8 () | |
3744 | { | |
3745 | uint8 a = (OP[0]) & 0xff; | |
3746 | trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); | |
3747 | uint32 addr = OP[1]; | |
3748 | SB (addr, a); | |
3749 | trace_output_32 (addr); | |
3750 | } | |
3751 | ||
3752 | /* storb. */ | |
3753 | void | |
3754 | OP_123_14 () | |
3755 | { | |
3756 | uint8 a = (OP[0]) & 0xff; | |
3757 | trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); | |
3758 | uint32 addr = OP[1]; | |
3759 | SB (addr, a); | |
3760 | trace_output_32 (addr); | |
3761 | } | |
3762 | ||
3763 | /* storb. */ | |
3764 | void | |
3765 | OP_42_7 () | |
3766 | { | |
3767 | uint32 addr; | |
3768 | uint8 a = (OP[0]) & 0xff; | |
3769 | trace_input ("storb", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID); | |
3770 | ||
3771 | if (OP[1] == 0) | |
3772 | addr = (GPR32 (12)) + OP[2]; | |
3773 | else | |
3774 | addr = (GPR32 (13)) + OP[2]; | |
3775 | ||
3776 | SB (addr, a); | |
3777 | trace_output_32 (addr); | |
3778 | } | |
3779 | ||
3780 | /* storb. */ | |
3781 | void | |
3782 | OP_218_A () | |
3783 | { | |
3784 | uint8 a = (OP[0]) & 0xff; | |
3785 | trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID); | |
3786 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3787 | SB (addr, a); | |
3788 | trace_output_32 (addr); | |
3789 | } | |
3790 | ||
3791 | /* storb. */ | |
3792 | void | |
3793 | OP_82_8 () | |
3794 | { | |
3795 | uint8 a = (OP[0]) & 0xff; | |
3796 | trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); | |
3797 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3798 | SB (addr, a); | |
3799 | trace_output_32 (addr); | |
3800 | } | |
3801 | ||
3802 | /* storb. */ | |
3803 | void | |
3804 | OP_120_14 () | |
3805 | { | |
3806 | uint8 a = (OP[0]) & 0xff; | |
3807 | trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); | |
3808 | uint32 addr = (GPR (OP[2])) + OP[1]; | |
3809 | SB (addr, a); | |
3810 | trace_output_32 (addr); | |
3811 | } | |
3812 | ||
3813 | /* storb. */ | |
3814 | void | |
3815 | OP_83_8 () | |
3816 | { | |
3817 | uint8 a = (OP[0]) & 0xff; | |
3818 | trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); | |
3819 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3820 | SB (addr, a); | |
3821 | trace_output_32 (addr); | |
3822 | } | |
3823 | ||
3824 | /* storb. */ | |
3825 | void | |
3826 | OP_121_14 () | |
3827 | { | |
3828 | uint8 a = (OP[0]) & 0xff; | |
3829 | trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); | |
3830 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3831 | SB (addr, a); | |
3832 | trace_output_32 (addr); | |
3833 | } | |
3834 | ||
3835 | /* storb. */ | |
3836 | void | |
3837 | OP_122_14 () | |
3838 | { | |
3839 | uint8 a = (OP[0]) & 0xff; | |
3840 | trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); | |
3841 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3842 | SB (addr, a); | |
3843 | trace_output_32 (addr); | |
3844 | } | |
3845 | /* endif for STR_IMM. */ | |
3846 | ||
3847 | /* storw . */ | |
3848 | void | |
3849 | OP_C9_8 () | |
3850 | { | |
3851 | uint16 a = GPR (OP[0]); | |
3852 | trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID); | |
3853 | uint32 addr = OP[1]; | |
3854 | SW (addr, a); | |
3855 | trace_output_32 (addr); | |
3856 | } | |
3857 | ||
3858 | /* storw. */ | |
3859 | void | |
3860 | OP_13F_14 () | |
3861 | { | |
3862 | uint16 a = GPR (OP[0]); | |
3863 | trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID); | |
3864 | uint32 addr = OP[1]; | |
3865 | SW (addr, a); | |
3866 | trace_output_32 (addr); | |
3867 | } | |
3868 | ||
3869 | /* storw. */ | |
3870 | void | |
3871 | OP_67_7 () | |
3872 | { | |
3873 | uint32 addr; | |
3874 | uint16 a = GPR (OP[0]); | |
3875 | trace_input ("storw", OP_REG, OP_R_INDEX8_ABS20, OP_VOID); | |
3876 | ||
3877 | if (OP[1] == 0) | |
3878 | addr = (GPR32 (12)) + OP[2]; | |
3879 | else | |
3880 | addr = (GPR32 (13)) + OP[2]; | |
3881 | ||
3882 | SW (addr, a); | |
3883 | trace_output_32 (addr); | |
3884 | } | |
3885 | ||
3886 | ||
3887 | /* storw. */ | |
3888 | void | |
3889 | OP_D_4 () | |
3890 | { | |
3891 | uint16 a = (GPR (OP[0])); | |
3892 | trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID); | |
3893 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3894 | SW (addr, a); | |
3895 | trace_output_32 (addr); | |
3896 | } | |
3897 | ||
3898 | /* storw. */ | |
3899 | void | |
3900 | OP_DE_8 () | |
3901 | { | |
3902 | uint16 a = GPR (OP[0]); | |
3903 | trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID); | |
3904 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3905 | SW (addr, a); | |
3906 | trace_output_32 (addr); | |
3907 | } | |
3908 | ||
3909 | /* storw. */ | |
3910 | void | |
3911 | OP_31B_A () | |
3912 | { | |
3913 | uint16 a = GPR (OP[0]); | |
3914 | trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID); | |
3915 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3916 | SW (addr, a); | |
3917 | trace_output_32 (addr); | |
3918 | } | |
3919 | ||
3920 | /* storw. */ | |
3921 | void | |
3922 | OP_19C_14 () | |
3923 | { | |
3924 | uint16 a = (GPR (OP[0])); | |
3925 | trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID); | |
3926 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3927 | SW (addr, a); | |
3928 | trace_output_32 (addr); | |
3929 | } | |
3930 | ||
3931 | /* storw. */ | |
3932 | void | |
3933 | OP_13C_14 () | |
3934 | { | |
3935 | uint16 a = (GPR (OP[0])); | |
3936 | trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID); | |
3937 | uint32 addr = (GPR (OP[2])) + OP[1]; | |
3938 | SW (addr, a); | |
3939 | trace_output_32 (addr); | |
3940 | } | |
3941 | ||
3942 | /* storw. */ | |
3943 | void | |
3944 | OP_DF_8 () | |
3945 | { | |
3946 | uint16 a = (GPR (OP[0])); | |
3947 | trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID); | |
3948 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3949 | SW (addr, a); | |
3950 | trace_output_32 (addr); | |
3951 | } | |
3952 | ||
3953 | /* storw. */ | |
3954 | void | |
3955 | OP_13D_14 () | |
3956 | { | |
3957 | uint16 a = (GPR (OP[0])); | |
3958 | trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID); | |
3959 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3960 | SW (addr, a); | |
3961 | trace_output_32 (addr); | |
3962 | } | |
3963 | ||
3964 | /* storw. */ | |
3965 | void | |
3966 | OP_19D_14 () | |
3967 | { | |
3968 | uint16 a = (GPR (OP[0])); | |
3969 | trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID); | |
3970 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3971 | SW (addr, a); | |
3972 | trace_output_32 (addr); | |
3973 | } | |
3974 | ||
3975 | /* storw. */ | |
3976 | void | |
3977 | OP_13E_14 () | |
3978 | { | |
3979 | uint16 a = (GPR (OP[0])); | |
3980 | trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID); | |
3981 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
3982 | SW (addr, a); | |
3983 | trace_output_32 (addr); | |
3984 | } | |
3985 | ||
3986 | /* STORE-w IMM instruction *****/ | |
3987 | /* storw . */ | |
3988 | void | |
3989 | OP_C1_8 () | |
3990 | { | |
3991 | uint16 a = OP[0]; | |
3992 | trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); | |
3993 | uint32 addr = OP[1]; | |
3994 | SW (addr, a); | |
3995 | trace_output_32 (addr); | |
3996 | } | |
3997 | ||
3998 | /* storw. */ | |
3999 | void | |
4000 | OP_133_14 () | |
4001 | { | |
4002 | uint16 a = OP[0]; | |
4003 | trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); | |
4004 | uint32 addr = OP[1]; | |
4005 | SW (addr, a); | |
4006 | trace_output_32 (addr); | |
4007 | } | |
4008 | ||
4009 | /* storw. */ | |
4010 | void | |
4011 | OP_62_7 () | |
4012 | { | |
4013 | uint32 addr; | |
4014 | uint16 a = OP[0]; | |
4015 | trace_input ("storw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID); | |
4016 | ||
4017 | if (OP[1] == 0) | |
4018 | addr = (GPR32 (12)) + OP[2]; | |
4019 | else | |
4020 | addr = (GPR32 (13)) + OP[2]; | |
4021 | ||
4022 | SW (addr, a); | |
4023 | trace_output_32 (addr); | |
4024 | } | |
4025 | ||
4026 | /* storw. */ | |
4027 | void | |
4028 | OP_318_A () | |
4029 | { | |
4030 | uint16 a = OP[0]; | |
4031 | trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID); | |
4032 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
4033 | SW (addr, a); | |
4034 | trace_output_32 (addr); | |
4035 | } | |
4036 | ||
4037 | /* storw. */ | |
4038 | void | |
4039 | OP_C2_8 () | |
4040 | { | |
4041 | uint16 a = OP[0]; | |
4042 | trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); | |
4043 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
4044 | SW (addr, a); | |
4045 | trace_output_32 (addr); | |
4046 | } | |
4047 | ||
4048 | /* storw. */ | |
4049 | void | |
4050 | OP_130_14 () | |
4051 | { | |
4052 | uint16 a = OP[0]; | |
4053 | trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); | |
4054 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
4055 | SW (addr, a); | |
4056 | trace_output_32 (addr); | |
4057 | } | |
4058 | ||
4059 | /* storw. */ | |
4060 | void | |
4061 | OP_C3_8 () | |
4062 | { | |
4063 | uint16 a = OP[0]; | |
4064 | trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); | |
4065 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
4066 | SW (addr, a); | |
4067 | trace_output_32 (addr); | |
4068 | } | |
4069 | ||
4070 | ||
4071 | /* storw. */ | |
4072 | void | |
4073 | OP_131_14 () | |
4074 | { | |
4075 | uint16 a = OP[0]; | |
4076 | trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); | |
4077 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
4078 | SW (addr, a); | |
4079 | trace_output_32 (addr); | |
4080 | } | |
4081 | ||
4082 | /* storw. */ | |
4083 | void | |
4084 | OP_132_14 () | |
4085 | { | |
4086 | uint16 a = OP[0]; | |
4087 | trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); | |
4088 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
4089 | SW (addr, a); | |
4090 | trace_output_32 (addr); | |
4091 | } | |
4092 | ||
4093 | ||
4094 | /* stord. */ | |
4095 | void | |
4096 | OP_C7_8 () | |
4097 | { | |
4098 | uint32 a = GPR32 (OP[0]); | |
4099 | trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID); | |
4100 | uint32 addr = OP[1]; | |
4101 | SLW (addr, a); | |
4102 | trace_output_32 (addr); | |
4103 | } | |
4104 | ||
4105 | /* stord. */ | |
4106 | void | |
4107 | OP_13B_14 () | |
4108 | { | |
4109 | uint32 a = GPR32 (OP[0]); | |
4110 | trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID); | |
4111 | uint32 addr = OP[1]; | |
4112 | SLW (addr, a); | |
4113 | trace_output_32 (addr); | |
4114 | } | |
4115 | ||
4116 | /* stord. */ | |
4117 | void | |
4118 | OP_66_7 () | |
4119 | { | |
4120 | uint32 addr, a = GPR32 (OP[0]); | |
4121 | trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID); | |
4122 | ||
4123 | if (OP[1] == 0) | |
4124 | addr = (GPR32 (12)) + OP[2]; | |
4125 | else | |
4126 | addr = (GPR32 (13)) + OP[2]; | |
4127 | ||
4128 | SLW (addr, a); | |
4129 | trace_output_32 (addr); | |
4130 | } | |
4131 | ||
4132 | /* stord. */ | |
4133 | void | |
4134 | OP_E_4 () | |
4135 | { | |
4136 | uint32 a = GPR32 (OP[0]); | |
4137 | trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID); | |
4138 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
4139 | SLW (addr, a); | |
4140 | trace_output_32 (addr); | |
4141 | } | |
4142 | ||
4143 | /* stord. */ | |
4144 | void | |
4145 | OP_EE_8 () | |
4146 | { | |
4147 | uint32 a = GPR32 (OP[0]); | |
4148 | trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID); | |
4149 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
4150 | SLW (addr, a); | |
4151 | trace_output_32 (addr); | |
4152 | } | |
4153 | ||
4154 | /* stord. */ | |
4155 | void | |
4156 | OP_31A_A () | |
4157 | { | |
4158 | uint32 a = GPR32 (OP[0]); | |
4159 | trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID); | |
4160 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
4161 | SLW (addr, a); | |
4162 | trace_output_32 (addr); | |
4163 | } | |
4164 | ||
4165 | /* stord. */ | |
4166 | void | |
4167 | OP_198_14 () | |
4168 | { | |
4169 | uint32 a = GPR32 (OP[0]); | |
4170 | trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID); | |
4171 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
4172 | SLW (addr, a); | |
4173 | trace_output_32 (addr); | |
4174 | } | |
4175 | ||
4176 | /* stord. */ | |
4177 | void | |
4178 | OP_138_14 () | |
4179 | { | |
4180 | uint32 a = GPR32 (OP[0]); | |
4181 | trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID); | |
4182 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
4183 | SLW (addr, a); | |
4184 | trace_output_32 (addr); | |
4185 | } | |
4186 | ||
4187 | /* stord. */ | |
4188 | void | |
4189 | OP_EF_8 () | |
4190 | { | |
4191 | uint32 a = GPR32 (OP[0]); | |
4192 | trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID); | |
4193 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
4194 | SLW (addr, a); | |
4195 | trace_output_32 (addr); | |
4196 | } | |
4197 | ||
4198 | /* stord. */ | |
4199 | void | |
4200 | OP_139_14 () | |
4201 | { | |
4202 | uint32 a = GPR32 (OP[0]); | |
4203 | trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID); | |
4204 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
4205 | SLW (addr, a); | |
4206 | trace_output_32 (addr); | |
4207 | } | |
4208 | ||
4209 | /* stord. */ | |
4210 | void | |
4211 | OP_199_14 () | |
4212 | { | |
4213 | uint32 a = GPR32 (OP[0]); | |
4214 | trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID); | |
4215 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
4216 | SLW (addr, a); | |
4217 | trace_output_32 (addr); | |
4218 | } | |
4219 | ||
4220 | /* stord. */ | |
4221 | void | |
4222 | OP_13A_14 () | |
4223 | { | |
4224 | uint32 a = GPR32 (OP[0]); | |
4225 | trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID); | |
4226 | uint32 addr = (GPR32 (OP[2])) + OP[1]; | |
4227 | SLW (addr, a); | |
4228 | trace_output_32 (addr); | |
4229 | } | |
4230 | ||
4231 | /* macqu. */ | |
4232 | void | |
4233 | OP_14D_14 () | |
4234 | { | |
4235 | int32 tmp; | |
4236 | int16 src1, src2; | |
4237 | trace_input ("macuw", OP_REG, OP_REG, OP_REGP); | |
4238 | src1 = GPR (OP[0]); | |
4239 | src2 = GPR (OP[1]); | |
4240 | tmp = src1 * src2; | |
4241 | /*REVISIT FOR SATURATION and Q FORMAT. */ | |
4242 | SET_GPR32 (OP[2], tmp); | |
4243 | trace_output_32 (tmp); | |
4244 | } | |
4245 | ||
4246 | /* macuw. */ | |
4247 | void | |
4248 | OP_14E_14 () | |
4249 | { | |
4250 | uint32 tmp; | |
4251 | uint16 src1, src2; | |
4252 | trace_input ("macuw", OP_REG, OP_REG, OP_REGP); | |
4253 | src1 = GPR (OP[0]); | |
4254 | src2 = GPR (OP[1]); | |
4255 | tmp = src1 * src2; | |
4256 | /*REVISIT FOR SATURATION. */ | |
4257 | SET_GPR32 (OP[2], tmp); | |
4258 | trace_output_32 (tmp); | |
4259 | } | |
4260 | ||
4261 | /* macsw. */ | |
4262 | void | |
4263 | OP_14F_14 () | |
4264 | { | |
4265 | int32 tmp; | |
4266 | int16 src1, src2; | |
4267 | trace_input ("macsw", OP_REG, OP_REG, OP_REGP); | |
4268 | src1 = GPR (OP[0]); | |
4269 | src2 = GPR (OP[1]); | |
4270 | tmp = src1 * src2; | |
4271 | /*REVISIT FOR SATURATION. */ | |
4272 | SET_GPR32 (OP[2], tmp); | |
4273 | trace_output_32 (tmp); | |
4274 | } | |
4275 | ||
4276 | ||
4277 | /* mulb. */ | |
4278 | void | |
4279 | OP_64_8 () | |
4280 | { | |
4281 | int16 tmp; | |
4282 | int8 a = (OP[0]) & 0xff; | |
4283 | int8 b = (GPR (OP[1])) & 0xff; | |
4284 | trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID); | |
4285 | tmp = (a * b) & 0xff; | |
4286 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
4287 | trace_output_16 (tmp); | |
4288 | } | |
4289 | ||
4290 | /* mulb. */ | |
4291 | void | |
4292 | OP_64B_C () | |
4293 | { | |
4294 | int16 tmp; | |
4295 | int8 a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; | |
4296 | trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID); | |
4297 | tmp = (a * b) & 0xff; | |
4298 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
4299 | trace_output_16 (tmp); | |
4300 | } | |
4301 | ||
4302 | ||
4303 | /* mulb. */ | |
4304 | void | |
4305 | OP_65_8 () | |
4306 | { | |
4307 | int16 tmp; | |
4308 | int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; | |
4309 | trace_input ("mulb", OP_REG, OP_REG, OP_VOID); | |
4310 | tmp = (a * b) & 0xff; | |
4311 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
4312 | trace_output_16 (tmp); | |
4313 | } | |
4314 | ||
4315 | ||
4316 | /* mulw. */ | |
4317 | void | |
4318 | OP_66_8 () | |
4319 | { | |
4320 | int32 tmp; | |
4321 | uint16 a = OP[0]; | |
4322 | int16 b = (GPR (OP[1])); | |
4323 | trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID); | |
4324 | tmp = (a * b) & 0xffff; | |
4325 | SET_GPR (OP[1], tmp); | |
4326 | trace_output_32 (tmp); | |
4327 | } | |
4328 | ||
4329 | /* mulw. */ | |
4330 | void | |
4331 | OP_66B_C () | |
4332 | { | |
4333 | int32 tmp; | |
4334 | int16 a = OP[0], b = (GPR (OP[1])); | |
4335 | trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID); | |
4336 | tmp = (a * b) & 0xffff; | |
4337 | SET_GPR (OP[1], tmp); | |
4338 | trace_output_32 (tmp); | |
4339 | } | |
4340 | ||
4341 | ||
4342 | /* mulw. */ | |
4343 | void | |
4344 | OP_67_8 () | |
4345 | { | |
4346 | int32 tmp; | |
4347 | int16 a = (GPR (OP[0])), b = (GPR (OP[1])); | |
4348 | trace_input ("mulw", OP_REG, OP_REG, OP_VOID); | |
4349 | tmp = (a * b) & 0xffff; | |
4350 | SET_GPR (OP[1], tmp); | |
4351 | trace_output_32 (tmp); | |
4352 | } | |
4353 | ||
4354 | ||
4355 | /* mulsb. */ | |
4356 | void | |
4357 | OP_B_8 () | |
4358 | { | |
4359 | int16 tmp; | |
4360 | int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; | |
4361 | trace_input ("mulsb", OP_REG, OP_REG, OP_VOID); | |
4362 | tmp = a * b; | |
4363 | SET_GPR (OP[1], tmp); | |
4364 | trace_output_32 (tmp); | |
4365 | } | |
4366 | ||
4367 | /* mulsw. */ | |
4368 | void | |
4369 | OP_62_8 () | |
4370 | { | |
4371 | int32 tmp, b = (GPR32 (OP[1])); | |
4372 | int16 a = (GPR (OP[0])); | |
4373 | trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID); | |
4374 | tmp = a * b; | |
4375 | SET_GPR32 (OP[1], tmp); | |
4376 | trace_output_32 (tmp); | |
4377 | } | |
4378 | ||
4379 | /* muluw. */ | |
4380 | void | |
4381 | OP_63_8 () | |
4382 | { | |
4383 | uint32 tmp, b = (GPR32 (OP[1])); | |
4384 | uint16 a = (GPR (OP[0])); | |
4385 | trace_input ("muluw", OP_REG, OP_REGP, OP_VOID); | |
4386 | tmp = a * b; | |
4387 | SET_GPR32 (OP[1], tmp); | |
4388 | trace_output_32 (tmp); | |
4389 | } | |
4390 | ||
4391 | ||
4392 | /* nop. */ | |
4393 | void | |
4394 | OP_2C00_10 () | |
4395 | { | |
4396 | trace_input ("nop", OP_VOID, OP_VOID, OP_VOID); | |
4397 | ||
4398 | #if 0 | |
4399 | State.exception = SIGTRAP; | |
4400 | ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */ | |
4401 | switch (State.ins_type) | |
4402 | { | |
4403 | default: | |
4404 | ins_type_counters[ (int)INS_UNKNOWN ]++; | |
4405 | break; | |
4406 | ||
4407 | } | |
4408 | ||
4409 | #endif | |
4410 | trace_output_void (); | |
4411 | } | |
4412 | ||
4413 | ||
4414 | /* orb. */ | |
4415 | void | |
4416 | OP_24_8 () | |
4417 | { | |
4418 | uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; | |
4419 | trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID); | |
4420 | tmp = a | b; | |
4421 | SET_GPR (OP[1], ((GPR (OP[1]) | tmp))); | |
4422 | trace_output_16 (tmp); | |
4423 | } | |
4424 | ||
4425 | /* orb. */ | |
4426 | void | |
4427 | OP_24B_C () | |
4428 | { | |
4429 | uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; | |
4430 | trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID); | |
4431 | tmp = a | b; | |
4432 | SET_GPR (OP[1], ((GPR (OP[1]) | tmp))); | |
4433 | trace_output_16 (tmp); | |
4434 | } | |
4435 | ||
4436 | /* orb. */ | |
4437 | void | |
4438 | OP_25_8 () | |
4439 | { | |
4440 | uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; | |
4441 | trace_input ("orb", OP_REG, OP_REG, OP_VOID); | |
4442 | tmp = a | b; | |
4443 | SET_GPR (OP[1], ((GPR (OP[1]) | tmp))); | |
4444 | trace_output_16 (tmp); | |
4445 | } | |
4446 | ||
4447 | /* orw. */ | |
4448 | void | |
4449 | OP_26_8 () | |
4450 | { | |
4451 | uint16 tmp, a = (OP[0]), b = (GPR (OP[1])); | |
4452 | trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID); | |
4453 | tmp = a | b; | |
4454 | SET_GPR (OP[1], tmp); | |
4455 | trace_output_16 (tmp); | |
4456 | } | |
4457 | ||
4458 | ||
4459 | /* orw. */ | |
4460 | void | |
4461 | OP_26B_C () | |
4462 | { | |
4463 | uint16 tmp, a = (OP[0]), b = (GPR (OP[1])); | |
4464 | trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID); | |
4465 | tmp = a | b; | |
4466 | SET_GPR (OP[1], tmp); | |
4467 | trace_output_16 (tmp); | |
4468 | } | |
4469 | ||
4470 | /* orw. */ | |
4471 | void | |
4472 | OP_27_8 () | |
4473 | { | |
4474 | uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1])); | |
4475 | trace_input ("orw", OP_REG, OP_REG, OP_VOID); | |
4476 | tmp = a | b; | |
4477 | SET_GPR (OP[1], tmp); | |
4478 | trace_output_16 (tmp); | |
4479 | } | |
4480 | ||
4481 | ||
4482 | /* lshb. */ | |
4483 | void | |
4484 | OP_13_9 () | |
4485 | { | |
4486 | uint16 a = OP[0]; | |
4487 | uint16 tmp, b = (GPR (OP[1])) & 0xFF; | |
4488 | trace_input ("lshb", OP_CONSTANT4, OP_REG, OP_VOID); | |
4489 | /* A positive count specifies a shift to the left; | |
4490 | * A negative count specifies a shift to the right. */ | |
4491 | if (sign_flag) | |
4492 | tmp = b >> a; | |
4493 | else | |
4494 | tmp = b << a; | |
4495 | ||
4496 | sign_flag = 0; /* Reset sign_flag. */ | |
4497 | ||
4498 | SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); | |
4499 | trace_output_16 (tmp); | |
4500 | } | |
4501 | ||
4502 | /* lshb. */ | |
4503 | void | |
4504 | OP_44_8 () | |
4505 | { | |
4506 | uint16 a = (GPR (OP[0])) & 0xff; | |
4507 | uint16 tmp, b = (GPR (OP[1])) & 0xFF; | |
4508 | trace_input ("lshb", OP_REG, OP_REG, OP_VOID); | |
4509 | if (a & ((long)1 << 3)) | |
4510 | { | |
4511 | sign_flag = 1; | |
4512 | a = ~(a) + 1; | |
4513 | } | |
4514 | a = (unsigned int) (a & 0x7); | |
4515 | ||
4516 | /* A positive count specifies a shift to the left; | |
4517 | * A negative count specifies a shift to the right. */ | |
4518 | if (sign_flag) | |
4519 | tmp = b >> a; | |
4520 | else | |
4521 | tmp = b << a; | |
4522 | ||
4523 | sign_flag = 0; /* Reset sign_flag. */ | |
4524 | SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); | |
4525 | trace_output_16 (tmp); | |
4526 | } | |
4527 | ||
4528 | /* lshw. */ | |
4529 | void | |
4530 | OP_46_8 () | |
4531 | { | |
4532 | uint16 tmp, b = GPR (OP[1]); | |
4533 | int16 a = GPR (OP[0]); | |
4534 | trace_input ("lshw", OP_REG, OP_REG, OP_VOID); | |
4535 | if (a & ((long)1 << 4)) | |
4536 | { | |
4537 | sign_flag = 1; | |
4538 | a = ~(a) + 1; | |
4539 | } | |
4540 | a = (unsigned int) (a & 0xf); | |
4541 | ||
4542 | /* A positive count specifies a shift to the left; | |
4543 | * A negative count specifies a shift to the right. */ | |
4544 | if (sign_flag) | |
4545 | tmp = b >> a; | |
4546 | else | |
4547 | tmp = b << a; | |
4548 | ||
4549 | sign_flag = 0; /* Reset sign_flag. */ | |
4550 | SET_GPR (OP[1], (tmp & 0xffff)); | |
4551 | trace_output_16 (tmp); | |
4552 | } | |
4553 | ||
4554 | /* lshw. */ | |
4555 | void | |
4556 | OP_49_8 () | |
4557 | { | |
4558 | uint16 tmp, b = GPR (OP[1]); | |
4559 | uint16 a = OP[0]; | |
4560 | trace_input ("lshw", OP_CONSTANT5, OP_REG, OP_VOID); | |
4561 | /* A positive count specifies a shift to the left; | |
4562 | * A negative count specifies a shift to the right. */ | |
4563 | if (sign_flag) | |
4564 | tmp = b >> a; | |
4565 | else | |
4566 | tmp = b << a; | |
4567 | ||
4568 | sign_flag = 0; /* Reset sign_flag. */ | |
4569 | SET_GPR (OP[1], (tmp & 0xffff)); | |
4570 | trace_output_16 (tmp); | |
4571 | } | |
4572 | ||
4573 | /* lshd. */ | |
4574 | void | |
4575 | OP_25_7 () | |
4576 | { | |
4577 | uint32 tmp, b = GPR32 (OP[1]); | |
4578 | uint16 a = OP[0]; | |
4579 | trace_input ("lshd", OP_CONSTANT6, OP_REGP, OP_VOID); | |
4580 | /* A positive count specifies a shift to the left; | |
4581 | * A negative count specifies a shift to the right. */ | |
4582 | if (sign_flag) | |
4583 | tmp = b >> a; | |
4584 | else | |
4585 | tmp = b << a; | |
4586 | ||
4587 | sign_flag = 0; /* Reset sign flag. */ | |
4588 | ||
4589 | SET_GPR32 (OP[1], tmp); | |
4590 | trace_output_32 (tmp); | |
4591 | } | |
4592 | ||
4593 | /* lshd. */ | |
4594 | void | |
4595 | OP_47_8 () | |
4596 | { | |
4597 | uint32 tmp, b = GPR32 (OP[1]); | |
4598 | uint16 a = GPR (OP[0]); | |
4599 | trace_input ("lshd", OP_REG, OP_REGP, OP_VOID); | |
4600 | if (a & ((long)1 << 5)) | |
4601 | { | |
4602 | sign_flag = 1; | |
4603 | a = ~(a) + 1; | |
4604 | } | |
4605 | a = (unsigned int) (a & 0x1f); | |
4606 | /* A positive count specifies a shift to the left; | |
4607 | * A negative count specifies a shift to the right. */ | |
4608 | if (sign_flag) | |
4609 | tmp = b >> a; | |
4610 | else | |
4611 | tmp = b << a; | |
4612 | ||
4613 | sign_flag = 0; /* Reset sign flag. */ | |
4614 | ||
4615 | SET_GPR32 (OP[1], tmp); | |
4616 | trace_output_32 (tmp); | |
4617 | } | |
4618 | ||
4619 | /* ashub. */ | |
4620 | void | |
4621 | OP_80_9 () | |
4622 | { | |
4623 | uint16 a = OP[0]; | |
4624 | int8 tmp, b = (GPR (OP[1])) & 0xFF; | |
4625 | trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID); | |
4626 | /* A positive count specifies a shift to the left; | |
4627 | * A negative count specifies a shift to the right. */ | |
4628 | if (sign_flag) | |
4629 | tmp = b >> a; | |
4630 | else | |
4631 | tmp = b << a; | |
4632 | ||
4633 | sign_flag = 0; /* Reset sign flag. */ | |
4634 | ||
4635 | SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xff00))); | |
4636 | trace_output_16 (tmp); | |
4637 | } | |
4638 | ||
4639 | /* ashub. */ | |
4640 | void | |
4641 | OP_81_9 () | |
4642 | { | |
4643 | uint16 a = OP[0]; | |
4644 | int8 tmp, b = (GPR (OP[1])) & 0xFF; | |
4645 | trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID); | |
4646 | /* A positive count specifies a shift to the left; | |
4647 | * A negative count specifies a shift to the right. */ | |
4648 | if (sign_flag) | |
4649 | tmp = b >> a; | |
4650 | else | |
4651 | tmp = b << a; | |
4652 | ||
4653 | sign_flag = 0; /* Reset sign flag. */ | |
4654 | ||
4655 | SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); | |
4656 | trace_output_16 (tmp); | |
4657 | } | |
4658 | ||
4659 | ||
4660 | /* ashub. */ | |
4661 | void | |
4662 | OP_41_8 () | |
4663 | { | |
4664 | int16 a = (GPR (OP[0])); | |
4665 | int8 tmp, b = (GPR (OP[1])) & 0xFF; | |
4666 | trace_input ("ashub", OP_REG, OP_REG, OP_VOID); | |
4667 | ||
4668 | if (a & ((long)1 << 3)) | |
4669 | { | |
4670 | sign_flag = 1; | |
4671 | a = ~(a) + 1; | |
4672 | } | |
4673 | a = (unsigned int) (a & 0x7); | |
4674 | ||
4675 | /* A positive count specifies a shift to the left; | |
4676 | * A negative count specifies a shift to the right. */ | |
4677 | if (sign_flag) | |
4678 | tmp = b >> a; | |
4679 | else | |
4680 | tmp = b << a; | |
4681 | ||
4682 | sign_flag = 0; /* Reset sign flag. */ | |
4683 | ||
4684 | SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); | |
4685 | trace_output_16 (tmp); | |
4686 | } | |
4687 | ||
4688 | ||
4689 | /* ashuw. */ | |
4690 | void | |
4691 | OP_42_8 () | |
4692 | { | |
4693 | int16 tmp, b = GPR (OP[1]); | |
4694 | uint16 a = OP[0]; | |
4695 | trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID); | |
4696 | /* A positive count specifies a shift to the left; | |
4697 | * A negative count specifies a shift to the right. */ | |
4698 | if (sign_flag) | |
4699 | tmp = b >> a; | |
4700 | else | |
4701 | tmp = b << a; | |
4702 | ||
4703 | sign_flag = 0; /* Reset sign flag. */ | |
4704 | ||
4705 | SET_GPR (OP[1], (tmp & 0xffff)); | |
4706 | trace_output_16 (tmp); | |
4707 | } | |
4708 | ||
4709 | /* ashuw. */ | |
4710 | void | |
4711 | OP_43_8 () | |
4712 | { | |
4713 | int16 tmp, b = GPR (OP[1]); | |
4714 | uint16 a = OP[0]; | |
4715 | trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID); | |
4716 | /* A positive count specifies a shift to the left; | |
4717 | * A negative count specifies a shift to the right. */ | |
4718 | if (sign_flag) | |
4719 | tmp = b >> a; | |
4720 | else | |
4721 | tmp = b << a; | |
4722 | ||
4723 | sign_flag = 0; /* Reset sign flag. */ | |
4724 | SET_GPR (OP[1], (tmp & 0xffff)); | |
4725 | trace_output_16 (tmp); | |
4726 | } | |
4727 | ||
4728 | /* ashuw. */ | |
4729 | void | |
4730 | OP_45_8 () | |
4731 | { | |
4732 | int16 tmp; | |
4733 | int16 a = GPR (OP[0]), b = GPR (OP[1]); | |
4734 | trace_input ("ashuw", OP_REG, OP_REG, OP_VOID); | |
4735 | ||
4736 | if (a & ((long)1 << 4)) | |
4737 | { | |
4738 | sign_flag = 1; | |
4739 | a = ~(a) + 1; | |
4740 | } | |
4741 | a = (unsigned int) (a & 0xf); | |
4742 | /* A positive count specifies a shift to the left; | |
4743 | * A negative count specifies a shift to the right. */ | |
4744 | ||
4745 | if (sign_flag) | |
4746 | tmp = b >> a; | |
4747 | else | |
4748 | tmp = b << a; | |
4749 | ||
4750 | sign_flag = 0; /* Reset sign flag. */ | |
4751 | SET_GPR (OP[1], (tmp & 0xffff)); | |
4752 | trace_output_16 (tmp); | |
4753 | } | |
4754 | ||
4755 | /* ashud. */ | |
4756 | void | |
4757 | OP_26_7 () | |
4758 | { | |
4759 | int32 tmp,b = GPR32 (OP[1]); | |
4760 | uint32 a = OP[0]; | |
4761 | trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID); | |
4762 | /* A positive count specifies a shift to the left; | |
4763 | * A negative count specifies a shift to the right. */ | |
4764 | if (sign_flag) | |
4765 | tmp = b >> a; | |
4766 | else | |
4767 | tmp = b << a; | |
4768 | ||
4769 | sign_flag = 0; /* Reset sign flag. */ | |
4770 | SET_GPR32 (OP[1], tmp); | |
4771 | trace_output_32 (tmp); | |
4772 | } | |
4773 | ||
4774 | /* ashud. */ | |
4775 | void | |
4776 | OP_27_7 () | |
4777 | { | |
4778 | int32 tmp; | |
4779 | int32 a = OP[0], b = GPR32 (OP[1]); | |
4780 | trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID); | |
4781 | /* A positive count specifies a shift to the left; | |
4782 | * A negative count specifies a shift to the right. */ | |
4783 | if (sign_flag) | |
4784 | tmp = b >> a; | |
4785 | else | |
4786 | tmp = b << a; | |
4787 | ||
4788 | sign_flag = 0; /* Reset sign flag. */ | |
4789 | SET_GPR32 (OP[1], tmp); | |
4790 | trace_output_32 (tmp); | |
4791 | } | |
4792 | ||
4793 | /* ashud. */ | |
4794 | void | |
4795 | OP_48_8 () | |
4796 | { | |
4797 | int32 tmp; | |
4798 | int32 a = GPR32 (OP[0]), b = GPR32 (OP[1]); | |
4799 | trace_input ("ashud", OP_REGP, OP_REGP, OP_VOID); | |
4800 | ||
4801 | if (a & ((long)1 << 5)) | |
4802 | { | |
4803 | sign_flag = 1; | |
4804 | a = ~(a) + 1; | |
4805 | } | |
4806 | a = (unsigned int) (a & 0x1f); | |
4807 | /* A positive count specifies a shift to the left; | |
4808 | * A negative count specifies a shift to the right. */ | |
4809 | if (sign_flag) | |
4810 | tmp = b >> a; | |
4811 | else | |
4812 | tmp = b << a; | |
4813 | ||
4814 | sign_flag = 0; /* Reset sign flag. */ | |
4815 | SET_GPR32 (OP[1], tmp); | |
4816 | trace_output_32 (tmp); | |
4817 | } | |
4818 | ||
4819 | ||
4820 | /* storm. */ | |
4821 | void | |
4822 | OP_16_D () | |
4823 | { | |
4824 | uint32 addr = GPR (1); | |
4825 | uint16 count = OP[0], reg = 2; | |
4826 | trace_input ("storm", OP_CONSTANT4, OP_VOID, OP_VOID); | |
4827 | if ((addr & 1)) | |
4828 | { | |
4829 | State.exception = SIG_CR16_BUS; | |
4830 | State.pc_changed = 1; /* Don't increment the PC. */ | |
4831 | trace_output_void (); | |
4832 | return; | |
4833 | } | |
4834 | ||
4835 | while (count) | |
4836 | { | |
4837 | SW (addr, (GPR (reg))); | |
4838 | addr +=2; | |
4839 | --count; | |
4840 | reg++; | |
4841 | if (reg == 6) reg = 8; | |
4842 | }; | |
4843 | ||
4844 | SET_GPR (1, addr); | |
4845 | ||
4846 | trace_output_void (); | |
4847 | } | |
4848 | ||
4849 | ||
4850 | /* stormp. */ | |
4851 | void | |
4852 | OP_17_D () | |
4853 | { | |
4854 | uint32 addr = GPR32 (6); | |
4855 | uint16 count = OP[0], reg = 2; | |
4856 | trace_input ("stormp", OP_CONSTANT4, OP_VOID, OP_VOID); | |
4857 | if ((addr & 1)) | |
4858 | { | |
4859 | State.exception = SIG_CR16_BUS; | |
4860 | State.pc_changed = 1; /* Don't increment the PC. */ | |
4861 | trace_output_void (); | |
4862 | return; | |
4863 | } | |
4864 | ||
4865 | while (count) | |
4866 | { | |
4867 | SW (addr, (GPR (reg))); | |
4868 | addr +=2; | |
4869 | --count; | |
4870 | reg++; | |
4871 | if (reg == 6) reg = 8; | |
4872 | }; | |
4873 | ||
4874 | SET_GPR32 (6, addr); | |
4875 | trace_output_void (); | |
4876 | } | |
4877 | ||
4878 | /* subb. */ | |
4879 | void | |
4880 | OP_38_8 () | |
4881 | { | |
4882 | uint8 a = OP[0]; | |
4883 | uint8 b = (GPR (OP[1])) & 0xff; | |
4884 | uint16 tmp = (~a + 1 + b) & 0xff; | |
4885 | trace_input ("subb", OP_CONSTANT4, OP_REG, OP_VOID); | |
4886 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
4887 | compute the carry/overflow bits. */ | |
4888 | SET_PSR_C (tmp > 0xff); | |
4889 | SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); | |
4890 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
4891 | trace_output_16 (tmp); | |
4892 | } | |
4893 | ||
4894 | /* subb. */ | |
4895 | void | |
4896 | OP_38B_C () | |
4897 | { | |
4898 | uint8 a = OP[0] & 0xFF; | |
4899 | uint8 b = (GPR (OP[1])) & 0xFF; | |
4900 | uint16 tmp = (~a + 1 + b) & 0xFF; | |
4901 | trace_input ("subb", OP_CONSTANT16, OP_REG, OP_VOID); | |
4902 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
4903 | compute the carry/overflow bits. */ | |
4904 | SET_PSR_C (tmp > 0xff); | |
4905 | SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); | |
4906 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
4907 | trace_output_16 (tmp); | |
4908 | } | |
4909 | ||
4910 | /* subb. */ | |
4911 | void | |
4912 | OP_39_8 () | |
4913 | { | |
4914 | uint8 a = (GPR (OP[0])) & 0xFF; | |
4915 | uint8 b = (GPR (OP[1])) & 0xFF; | |
4916 | uint16 tmp = (~a + 1 + b) & 0xff; | |
4917 | trace_input ("subb", OP_REG, OP_REG, OP_VOID); | |
4918 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
4919 | compute the carry/overflow bits. */ | |
4920 | SET_PSR_C (tmp > 0xff); | |
4921 | SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); | |
4922 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
4923 | trace_output_16 (tmp); | |
4924 | } | |
4925 | ||
4926 | /* subw. */ | |
4927 | void | |
4928 | OP_3A_8 () | |
4929 | { | |
4930 | uint16 a = OP[0]; | |
4931 | uint16 b = GPR (OP[1]); | |
4932 | uint16 tmp = (~a + 1 + b); | |
4933 | trace_input ("subw", OP_CONSTANT4, OP_REG, OP_VOID); | |
4934 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
4935 | compute the carry/overflow bits. */ | |
4936 | SET_PSR_C (tmp > 0xffff); | |
4937 | SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); | |
4938 | SET_GPR (OP[1], tmp); | |
4939 | trace_output_16 (tmp); | |
4940 | } | |
4941 | ||
4942 | /* subw. */ | |
4943 | void | |
4944 | OP_3AB_C () | |
4945 | { | |
4946 | uint16 a = OP[0]; | |
4947 | uint16 b = GPR (OP[1]); | |
4948 | uint32 tmp = (~a + 1 + b); | |
4949 | trace_input ("subw", OP_CONSTANT16, OP_REG, OP_VOID); | |
4950 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
4951 | compute the carry/overflow bits. */ | |
4952 | SET_PSR_C (tmp > 0xffff); | |
4953 | SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); | |
4954 | SET_GPR (OP[1], tmp & 0xffff); | |
4955 | trace_output_16 (tmp); | |
4956 | } | |
4957 | ||
4958 | /* subw. */ | |
4959 | void | |
4960 | OP_3B_8 () | |
4961 | { | |
4962 | uint16 a = GPR (OP[0]); | |
4963 | uint16 b = GPR (OP[1]); | |
4964 | uint32 tmp = (~a + 1 + b); | |
4965 | trace_input ("subw", OP_REG, OP_REG, OP_VOID); | |
4966 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
4967 | compute the carry/overflow bits. */ | |
4968 | SET_PSR_C (tmp > 0xffff); | |
4969 | SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); | |
4970 | SET_GPR (OP[1], tmp & 0xffff); | |
4971 | trace_output_16 (tmp); | |
4972 | } | |
4973 | ||
4974 | /* subcb. */ | |
4975 | void | |
4976 | OP_3C_8 () | |
4977 | { | |
4978 | uint8 a = OP[0]; | |
4979 | uint8 b = (GPR (OP[1])) & 0xff; | |
4980 | //uint16 tmp1 = a + 1; | |
4981 | uint16 tmp1 = a + (PSR_C); | |
4982 | uint16 tmp = (~tmp1 + 1 + b); | |
4983 | trace_input ("subcb", OP_CONSTANT4, OP_REG, OP_VOID); | |
4984 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
4985 | compute the carry/overflow bits. */ | |
4986 | SET_PSR_C (tmp > 0xff); | |
4987 | SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); | |
4988 | SET_GPR (OP[1], tmp); | |
4989 | trace_output_16 (tmp); | |
4990 | } | |
4991 | ||
4992 | /* subcb. */ | |
4993 | void | |
4994 | OP_3CB_C () | |
4995 | { | |
4996 | uint16 a = OP[0]; | |
4997 | uint16 b = (GPR (OP[1])) & 0xff; | |
4998 | //uint16 tmp1 = a + 1; | |
4999 | uint16 tmp1 = a + (PSR_C); | |
5000 | uint16 tmp = (~tmp1 + 1 + b); | |
5001 | trace_input ("subcb", OP_CONSTANT16, OP_REG, OP_VOID); | |
5002 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
5003 | compute the carry/overflow bits. */ | |
5004 | SET_PSR_C (tmp > 0xff); | |
5005 | SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); | |
5006 | SET_GPR (OP[1], tmp); | |
5007 | trace_output_16 (tmp); | |
5008 | } | |
5009 | ||
5010 | /* subcb. */ | |
5011 | void | |
5012 | OP_3D_8 () | |
5013 | { | |
5014 | uint16 a = (GPR (OP[0])) & 0xff; | |
5015 | uint16 b = (GPR (OP[1])) & 0xff; | |
5016 | uint16 tmp1 = a + (PSR_C); | |
5017 | uint16 tmp = (~tmp1 + 1 + b); | |
5018 | trace_input ("subcb", OP_REG, OP_REG, OP_VOID); | |
5019 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
5020 | compute the carry/overflow bits. */ | |
5021 | SET_PSR_C (tmp > 0xff); | |
5022 | SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); | |
5023 | SET_GPR (OP[1], tmp); | |
5024 | trace_output_16 (tmp); | |
5025 | } | |
5026 | ||
5027 | /* subcw. */ | |
5028 | void | |
5029 | OP_3E_8 () | |
5030 | { | |
5031 | uint16 a = OP[0], b = (GPR (OP[1])); | |
5032 | uint16 tmp1 = a + (PSR_C); | |
5033 | uint16 tmp = (~tmp1 + 1 + b); | |
5034 | trace_input ("subcw", OP_CONSTANT4, OP_REG, OP_VOID); | |
5035 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
5036 | compute the carry/overflow bits. */ | |
5037 | SET_PSR_C (tmp > 0xffff); | |
5038 | SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); | |
5039 | SET_GPR (OP[1], tmp); | |
5040 | trace_output_16 (tmp); | |
5041 | } | |
5042 | ||
5043 | /* subcw. */ | |
5044 | void | |
5045 | OP_3EB_C () | |
5046 | { | |
5047 | int16 a = OP[0]; | |
5048 | uint16 b = GPR (OP[1]); | |
5049 | uint16 tmp1 = a + (PSR_C); | |
5050 | uint16 tmp = (~tmp1 + 1 + b); | |
5051 | trace_input ("subcw", OP_CONSTANT16, OP_REG, OP_VOID); | |
5052 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
5053 | compute the carry/overflow bits. */ | |
5054 | SET_PSR_C (tmp > 0xffff); | |
5055 | SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); | |
5056 | SET_GPR (OP[1], tmp); | |
5057 | trace_output_16 (tmp); | |
5058 | } | |
5059 | ||
5060 | /* subcw. */ | |
5061 | void | |
5062 | OP_3F_8 () | |
5063 | { | |
5064 | uint16 a = (GPR (OP[0])), b = (GPR (OP[1])); | |
5065 | uint16 tmp1 = a + (PSR_C); | |
5066 | uint16 tmp = (~tmp1 + 1 + b); | |
5067 | trace_input ("subcw", OP_REG, OP_REG, OP_VOID); | |
5068 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
5069 | compute the carry/overflow bits. */ | |
5070 | SET_PSR_C (tmp > 0xffff); | |
5071 | SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); | |
5072 | SET_GPR (OP[1], tmp); | |
5073 | trace_output_16 (tmp); | |
5074 | } | |
5075 | ||
5076 | /* subd. */ | |
5077 | void | |
5078 | OP_3_C () | |
5079 | { | |
5080 | int32 a = OP[0]; | |
5081 | uint32 b = GPR32 (OP[1]); | |
5082 | uint32 tmp = (~a + 1 + b); | |
5083 | trace_input ("subd", OP_CONSTANT32, OP_REGP, OP_VOID); | |
5084 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
5085 | compute the carry/overflow bits. */ | |
5086 | SET_PSR_C (tmp > 0xffffffff); | |
5087 | SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) && | |
5088 | ((b & 0x80000000) != (tmp & 0x80000000))); | |
5089 | SET_GPR32 (OP[1], tmp); | |
5090 | trace_output_32 (tmp); | |
5091 | } | |
5092 | ||
5093 | /* subd. */ | |
5094 | void | |
5095 | OP_14C_14 () | |
5096 | { | |
5097 | uint32 a = GPR32 (OP[0]); | |
5098 | uint32 b = GPR32 (OP[1]); | |
5099 | uint32 tmp = (~a + 1 + b); | |
5100 | trace_input ("subd", OP_REGP, OP_REGP, OP_VOID); | |
5101 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
5102 | compute the carry/overflow bits. */ | |
5103 | SET_PSR_C (tmp > 0xffffffff); | |
5104 | SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) && | |
5105 | ((b & 0x80000000) != (tmp & 0x80000000))); | |
5106 | SET_GPR32 (OP[1], tmp); | |
5107 | trace_output_32 (tmp); | |
5108 | } | |
5109 | ||
5110 | /* excp. */ | |
5111 | void | |
5112 | OP_C_C () | |
5113 | { | |
5114 | trace_input ("excp", OP_CONSTANT4, OP_VOID, OP_VOID); | |
5115 | switch (OP[0]) | |
5116 | { | |
5117 | default: | |
5118 | #if (DEBUG & DEBUG_TRAP) == 0 | |
5119 | { | |
5120 | #if 0 | |
5121 | uint16 vec = OP[0] + TRAP_VECTOR_START; | |
5122 | SET_BPC (PC + 1); | |
5123 | SET_BPSR (PSR); | |
5124 | SET_PSR (PSR & PSR_SM_BIT); | |
5125 | JMP (vec); | |
5126 | break; | |
5127 | #endif | |
5128 | } | |
5129 | #else /* if debugging use trap to print registers */ | |
5130 | { | |
5131 | int i; | |
5132 | static int first_time = 1; | |
5133 | ||
5134 | if (first_time) | |
5135 | { | |
5136 | first_time = 0; | |
5137 | (*cr16_callback->printf_filtered) (cr16_callback, "Trap # PC "); | |
5138 | for (i = 0; i < 16; i++) | |
5139 | (*cr16_callback->printf_filtered) (cr16_callback, " %sr%d", (i > 9) ? "" : " ", i); | |
5140 | (*cr16_callback->printf_filtered) (cr16_callback, " a0 a1 f0 f1 c\n"); | |
5141 | } | |
5142 | ||
5143 | (*cr16_callback->printf_filtered) (cr16_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC); | |
5144 | ||
5145 | for (i = 0; i < 16; i++) | |
5146 | (*cr16_callback->printf_filtered) (cr16_callback, " %.4x", (int) GPR (i)); | |
5147 | ||
5148 | for (i = 0; i < 2; i++) | |
5149 | (*cr16_callback->printf_filtered) (cr16_callback, " %.2x%.8lx", | |
5150 | ((int)(ACC (i) >> 32) & 0xff), | |
5151 | ((unsigned long) ACC (i)) & 0xffffffff); | |
5152 | ||
5153 | (*cr16_callback->printf_filtered) (cr16_callback, " %d %d %d\n", | |
5154 | PSR_F != 0, PSR_F != 0, PSR_C != 0); | |
5155 | (*cr16_callback->flush_stdout) (cr16_callback); | |
5156 | break; | |
5157 | } | |
5158 | #endif | |
5159 | case 8: /* new system call trap */ | |
5160 | /* Trap 8 is used for simulating low-level I/O */ | |
5161 | { | |
5162 | unsigned32 result = 0; | |
5163 | errno = 0; | |
5164 | ||
5165 | /* Registers passed to trap 0. */ | |
5166 | ||
5167 | #define FUNC GPR (0) /* function number. */ | |
5168 | #define PARM1 GPR (2) /* optional parm 1. */ | |
5169 | #define PARM2 GPR (3) /* optional parm 2. */ | |
5170 | #define PARM3 GPR (4) /* optional parm 3. */ | |
5171 | #define PARM4 GPR (5) /* optional parm 4. */ | |
5172 | ||
5173 | /* Registers set by trap 0 */ | |
5174 | ||
5175 | #define RETVAL(X) do { result = (0xffff & (X));SET_GPR (0, result);} while (0) | |
5176 | #define RETVAL32(X) do { result = (X); SET_GPR32 (0, result);} while (0) | |
5177 | #define RETERR(X) SET_GPR (4, (X)) /* return error code. */ | |
5178 | ||
5179 | /* Turn a pointer in a register into a pointer into real memory. */ | |
5180 | ||
5181 | #define MEMPTR(x) ((char *)(dmem_addr(x))) | |
5182 | ||
5183 | switch (FUNC) | |
5184 | { | |
5185 | #if !defined(__GO32__) && !defined(_WIN32) | |
5186 | case TARGET_SYS_fork: | |
5187 | trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID); | |
5188 | RETVAL (fork ()); | |
5189 | trace_output_16 (result); | |
5190 | break; | |
5191 | ||
5192 | #define getpid() 47 | |
5193 | case TARGET_SYS_getpid: | |
5194 | trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); | |
5195 | RETVAL (getpid ()); | |
5196 | trace_output_16 (result); | |
5197 | break; | |
5198 | ||
5199 | case TARGET_SYS_kill: | |
5200 | trace_input ("<kill>", OP_REG, OP_REG, OP_VOID); | |
5201 | if (PARM1 == getpid ()) | |
5202 | { | |
5203 | trace_output_void (); | |
5204 | State.exception = PARM2; | |
5205 | } | |
5206 | else | |
5207 | { | |
5208 | int os_sig = -1; | |
5209 | switch (PARM2) | |
5210 | { | |
5211 | #ifdef SIGHUP | |
5212 | case 1: os_sig = SIGHUP; break; | |
5213 | #endif | |
5214 | #ifdef SIGINT | |
5215 | case 2: os_sig = SIGINT; break; | |
5216 | #endif | |
5217 | #ifdef SIGQUIT | |
5218 | case 3: os_sig = SIGQUIT; break; | |
5219 | #endif | |
5220 | #ifdef SIGILL | |
5221 | case 4: os_sig = SIGILL; break; | |
5222 | #endif | |
5223 | #ifdef SIGTRAP | |
5224 | case 5: os_sig = SIGTRAP; break; | |
5225 | #endif | |
5226 | #ifdef SIGABRT | |
5227 | case 6: os_sig = SIGABRT; break; | |
5228 | #elif defined(SIGIOT) | |
5229 | case 6: os_sig = SIGIOT; break; | |
5230 | #endif | |
5231 | #ifdef SIGEMT | |
5232 | case 7: os_sig = SIGEMT; break; | |
5233 | #endif | |
5234 | #ifdef SIGFPE | |
5235 | case 8: os_sig = SIGFPE; break; | |
5236 | #endif | |
5237 | #ifdef SIGKILL | |
5238 | case 9: os_sig = SIGKILL; break; | |
5239 | #endif | |
5240 | #ifdef SIGBUS | |
5241 | case 10: os_sig = SIGBUS; break; | |
5242 | #endif | |
5243 | #ifdef SIGSEGV | |
5244 | case 11: os_sig = SIGSEGV; break; | |
5245 | #endif | |
5246 | #ifdef SIGSYS | |
5247 | case 12: os_sig = SIGSYS; break; | |
5248 | #endif | |
5249 | #ifdef SIGPIPE | |
5250 | case 13: os_sig = SIGPIPE; break; | |
5251 | #endif | |
5252 | #ifdef SIGALRM | |
5253 | case 14: os_sig = SIGALRM; break; | |
5254 | #endif | |
5255 | #ifdef SIGTERM | |
5256 | case 15: os_sig = SIGTERM; break; | |
5257 | #endif | |
5258 | #ifdef SIGURG | |
5259 | case 16: os_sig = SIGURG; break; | |
5260 | #endif | |
5261 | #ifdef SIGSTOP | |
5262 | case 17: os_sig = SIGSTOP; break; | |
5263 | #endif | |
5264 | #ifdef SIGTSTP | |
5265 | case 18: os_sig = SIGTSTP; break; | |
5266 | #endif | |
5267 | #ifdef SIGCONT | |
5268 | case 19: os_sig = SIGCONT; break; | |
5269 | #endif | |
5270 | #ifdef SIGCHLD | |
5271 | case 20: os_sig = SIGCHLD; break; | |
5272 | #elif defined(SIGCLD) | |
5273 | case 20: os_sig = SIGCLD; break; | |
5274 | #endif | |
5275 | #ifdef SIGTTIN | |
5276 | case 21: os_sig = SIGTTIN; break; | |
5277 | #endif | |
5278 | #ifdef SIGTTOU | |
5279 | case 22: os_sig = SIGTTOU; break; | |
5280 | #endif | |
5281 | #ifdef SIGIO | |
5282 | case 23: os_sig = SIGIO; break; | |
5283 | #elif defined (SIGPOLL) | |
5284 | case 23: os_sig = SIGPOLL; break; | |
5285 | #endif | |
5286 | #ifdef SIGXCPU | |
5287 | case 24: os_sig = SIGXCPU; break; | |
5288 | #endif | |
5289 | #ifdef SIGXFSZ | |
5290 | case 25: os_sig = SIGXFSZ; break; | |
5291 | #endif | |
5292 | #ifdef SIGVTALRM | |
5293 | case 26: os_sig = SIGVTALRM; break; | |
5294 | #endif | |
5295 | #ifdef SIGPROF | |
5296 | case 27: os_sig = SIGPROF; break; | |
5297 | #endif | |
5298 | #ifdef SIGWINCH | |
5299 | case 28: os_sig = SIGWINCH; break; | |
5300 | #endif | |
5301 | #ifdef SIGLOST | |
5302 | case 29: os_sig = SIGLOST; break; | |
5303 | #endif | |
5304 | #ifdef SIGUSR1 | |
5305 | case 30: os_sig = SIGUSR1; break; | |
5306 | #endif | |
5307 | #ifdef SIGUSR2 | |
5308 | case 31: os_sig = SIGUSR2; break; | |
5309 | #endif | |
5310 | } | |
5311 | ||
5312 | if (os_sig == -1) | |
5313 | { | |
5314 | trace_output_void (); | |
5315 | (*cr16_callback->printf_filtered) (cr16_callback, "Unknown signal %d\n", PARM2); | |
5316 | (*cr16_callback->flush_stdout) (cr16_callback); | |
5317 | State.exception = SIGILL; | |
5318 | } | |
5319 | else | |
5320 | { | |
5321 | RETVAL (kill (PARM1, PARM2)); | |
5322 | trace_output_16 (result); | |
5323 | } | |
5324 | } | |
5325 | break; | |
5326 | ||
5327 | case TARGET_SYS_execve: | |
5328 | trace_input ("<execve>", OP_VOID, OP_VOID, OP_VOID); | |
5329 | RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2<<16|PARM3), | |
5330 | (char **)MEMPTR (PARM4))); | |
5331 | trace_output_16 (result); | |
5332 | break; | |
5333 | ||
5334 | #ifdef TARGET_SYS_execv | |
5335 | case TARGET_SYS_execv: | |
5336 | trace_input ("<execv>", OP_VOID, OP_VOID, OP_VOID); | |
5337 | RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL)); | |
5338 | trace_output_16 (result); | |
5339 | break; | |
5340 | #endif | |
5341 | ||
5342 | case TARGET_SYS_pipe: | |
5343 | { | |
5344 | reg_t buf; | |
5345 | int host_fd[2]; | |
5346 | ||
5347 | trace_input ("<pipe>", OP_VOID, OP_VOID, OP_VOID); | |
5348 | buf = PARM1; | |
5349 | RETVAL (pipe (host_fd)); | |
5350 | SW (buf, host_fd[0]); | |
5351 | buf += sizeof(uint16); | |
5352 | SW (buf, host_fd[1]); | |
5353 | trace_output_16 (result); | |
5354 | } | |
5355 | break; | |
5356 | ||
5357 | #ifdef TARGET_SYS_wait | |
5358 | case TARGET_SYS_wait: | |
5359 | { | |
5360 | int status; | |
5361 | trace_input ("<wait>", OP_REG, OP_VOID, OP_VOID); | |
5362 | RETVAL (wait (&status)); | |
5363 | if (PARM1) | |
5364 | SW (PARM1, status); | |
5365 | trace_output_16 (result); | |
5366 | } | |
5367 | break; | |
5368 | #endif | |
5369 | #else | |
5370 | case TARGET_SYS_getpid: | |
5371 | trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); | |
5372 | RETVAL (1); | |
5373 | trace_output_16 (result); | |
5374 | break; | |
5375 | ||
5376 | case TARGET_SYS_kill: | |
5377 | trace_input ("<kill>", OP_REG, OP_REG, OP_VOID); | |
5378 | trace_output_void (); | |
5379 | State.exception = PARM2; | |
5380 | break; | |
5381 | #endif | |
5382 | ||
5383 | case TARGET_SYS_read: | |
5384 | trace_input ("<read>", OP_REG, OP_MEMREF, OP_REG); | |
5385 | RETVAL (cr16_callback->read (cr16_callback, PARM1, | |
5386 | MEMPTR (((unsigned long)PARM3 << 16) | |
5387 | |((unsigned long)PARM2)), PARM4)); | |
5388 | trace_output_16 (result); | |
5389 | break; | |
5390 | ||
5391 | case TARGET_SYS_write: | |
5392 | trace_input ("<write>", OP_REG, OP_MEMREF, OP_REG); | |
5393 | RETVAL ((int)cr16_callback->write (cr16_callback, PARM1, | |
5394 | MEMPTR (((unsigned long)PARM3 << 16) | PARM2), PARM4)); | |
5395 | trace_output_16 (result); | |
5396 | break; | |
5397 | ||
5398 | case TARGET_SYS_lseek: | |
5399 | trace_input ("<lseek>", OP_REG, OP_REGP, OP_REG); | |
5400 | RETVAL32 (cr16_callback->lseek (cr16_callback, PARM1, | |
5401 | ((((long) PARM3) << 16) | PARM2), | |
5402 | PARM4)); | |
5403 | trace_output_32 (result); | |
5404 | break; | |
5405 | ||
5406 | case TARGET_SYS_close: | |
5407 | trace_input ("<close>", OP_REG, OP_VOID, OP_VOID); | |
5408 | RETVAL (cr16_callback->close (cr16_callback, PARM1)); | |
5409 | trace_output_16 (result); | |
5410 | break; | |
5411 | ||
5412 | case TARGET_SYS_open: | |
5413 | trace_input ("<open>", OP_MEMREF, OP_REG, OP_VOID); | |
5414 | RETVAL32 (cr16_callback->open (cr16_callback, | |
5415 | MEMPTR ((((unsigned long)PARM2)<<16)|PARM1), | |
5416 | PARM3)); | |
5417 | trace_output_32 (result); | |
5418 | break; | |
5419 | ||
5420 | case TARGET_SYS_rename: | |
5421 | trace_input ("<rename>", OP_MEMREF, OP_MEMREF, OP_VOID); | |
5422 | RETVAL (cr16_callback->rename (cr16_callback, | |
5423 | MEMPTR ((((unsigned long)PARM2)<<16) |PARM1), | |
5424 | MEMPTR ((((unsigned long)PARM4)<<16) |PARM3))); | |
5425 | trace_output_16 (result); | |
5426 | break; | |
5427 | ||
5428 | case 0x408: /* REVISIT: Added a dummy getenv call. */ | |
5429 | trace_input ("<getenv>", OP_MEMREF, OP_MEMREF, OP_VOID); | |
5430 | RETVAL32(NULL); | |
5431 | trace_output_32 (result); | |
5432 | break; | |
5433 | ||
5434 | case TARGET_SYS_exit: | |
5435 | trace_input ("<exit>", OP_VOID, OP_VOID, OP_VOID); | |
5436 | State.exception = SIG_CR16_EXIT; | |
5437 | trace_output_void (); | |
5438 | break; | |
5439 | ||
5440 | case TARGET_SYS_unlink: | |
5441 | trace_input ("<unlink>", OP_MEMREF, OP_VOID, OP_VOID); | |
5442 | RETVAL (cr16_callback->unlink (cr16_callback, | |
5443 | MEMPTR (((unsigned long)PARM2<<16)|PARM1))); | |
5444 | trace_output_16 (result); | |
5445 | break; | |
5446 | ||
5447 | ||
5448 | #ifdef TARGET_SYS_stat | |
5449 | case TARGET_SYS_stat: | |
5450 | trace_input ("<stat>", OP_VOID, OP_VOID, OP_VOID); | |
5451 | /* stat system call. */ | |
5452 | { | |
5453 | struct stat host_stat; | |
5454 | reg_t buf; | |
5455 | ||
5456 | RETVAL (stat (MEMPTR ((((unsigned long)PARM2) << 16)|PARM1), &host_stat)); | |
5457 | ||
5458 | buf = PARM2; | |
5459 | ||
5460 | /* The hard-coded offsets and sizes were determined by using | |
5461 | * the CR16 compiler on a test program that used struct stat. | |
5462 | */ | |
5463 | SW (buf, host_stat.st_dev); | |
5464 | SW (buf+2, host_stat.st_ino); | |
5465 | SW (buf+4, host_stat.st_mode); | |
5466 | SW (buf+6, host_stat.st_nlink); | |
5467 | SW (buf+8, host_stat.st_uid); | |
5468 | SW (buf+10, host_stat.st_gid); | |
5469 | SW (buf+12, host_stat.st_rdev); | |
5470 | SLW (buf+16, host_stat.st_size); | |
5471 | SLW (buf+20, host_stat.st_atime); | |
5472 | SLW (buf+28, host_stat.st_mtime); | |
5473 | SLW (buf+36, host_stat.st_ctime); | |
5474 | } | |
5475 | trace_output_16 (result); | |
5476 | break; | |
5477 | #endif | |
5478 | ||
5479 | case TARGET_SYS_chown: | |
5480 | trace_input ("<chown>", OP_VOID, OP_VOID, OP_VOID); | |
5481 | RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3)); | |
5482 | trace_output_16 (result); | |
5483 | break; | |
5484 | ||
5485 | case TARGET_SYS_chmod: | |
5486 | trace_input ("<chmod>", OP_VOID, OP_VOID, OP_VOID); | |
5487 | RETVAL (chmod (MEMPTR (PARM1), PARM2)); | |
5488 | trace_output_16 (result); | |
5489 | break; | |
5490 | ||
5491 | #ifdef TARGET_SYS_utime | |
5492 | case TARGET_SYS_utime: | |
5493 | trace_input ("<utime>", OP_REG, OP_REG, OP_REG); | |
5494 | /* Cast the second argument to void *, to avoid type mismatch | |
5495 | if a prototype is present. */ | |
5496 | RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2))); | |
5497 | trace_output_16 (result); | |
5498 | break; | |
5499 | #endif | |
5500 | ||
5501 | #ifdef TARGET_SYS_time | |
5502 | case TARGET_SYS_time: | |
5503 | trace_input ("<time>", OP_VOID, OP_VOID, OP_REG); | |
5504 | RETVAL32 (time (NULL)); | |
5505 | trace_output_32 (result); | |
5506 | break; | |
5507 | #endif | |
5508 | ||
5509 | default: | |
5510 | cr16_callback->error (cr16_callback, "Unknown syscall %d", FUNC); | |
5511 | } | |
5512 | ||
5513 | if ((uint16) result == (uint16) -1) | |
5514 | RETERR (cr16_callback->get_errno(cr16_callback)); | |
5515 | else | |
5516 | RETERR (0); | |
5517 | break; | |
5518 | } | |
5519 | } | |
5520 | } | |
5521 | ||
5522 | ||
5523 | /* push. */ | |
5524 | void | |
5525 | OP_3_9 () | |
5526 | { | |
5527 | uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0; | |
5528 | uint32 tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0; | |
5529 | trace_input ("push", OP_CONSTANT3, OP_REG, OP_REG); | |
5530 | ||
5531 | for (; i < a; ++i) | |
5532 | { | |
5533 | if ((b+i) <= 11) | |
5534 | { | |
5535 | SW (sp_addr, (GPR (b+i))); | |
5536 | sp_addr +=2; | |
5537 | } | |
5538 | else | |
5539 | { | |
5540 | if (is_regp == 0) | |
5541 | tmp = (GPR32 (b+i)); | |
5542 | else | |
5543 | tmp = (GPR32 (b+i-1)); | |
5544 | ||
5545 | if ((a-i) > 1) | |
5546 | { | |
5547 | SLW (sp_addr, tmp); | |
5548 | sp_addr +=4; | |
5549 | } | |
5550 | else | |
5551 | { | |
5552 | SW (sp_addr, tmp); | |
5553 | sp_addr +=2; | |
5554 | } | |
5555 | ++i; | |
5556 | is_regp = 1; | |
5557 | } | |
5558 | } | |
5559 | ||
5560 | sp_addr +=4; | |
5561 | ||
5562 | /* Store RA address. */ | |
5563 | tmp = (GPR32 (14)); | |
5564 | SLW(sp_addr,tmp); | |
5565 | ||
5566 | sp_addr = (GPR32 (15)) - (a * 2) - 4; | |
5567 | SET_GPR32 (15, sp_addr); /* Update SP address. */ | |
5568 | ||
5569 | trace_output_void (); | |
5570 | } | |
5571 | ||
5572 | /* push. */ | |
5573 | void | |
5574 | OP_1_8 () | |
5575 | { | |
5576 | uint32 sp_addr, tmp, is_regp = 0; | |
5577 | uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0; | |
5578 | trace_input ("push", OP_CONSTANT3, OP_REG, OP_VOID); | |
5579 | ||
5580 | if (c == 1) | |
5581 | sp_addr = (GPR32 (15)) - (a * 2) - 4; | |
5582 | else | |
5583 | sp_addr = (GPR32 (15)) - (a * 2); | |
5584 | ||
5585 | for (; i < a; ++i) | |
5586 | { | |
5587 | if ((b+i) <= 11) | |
5588 | { | |
5589 | SW (sp_addr, (GPR (b+i))); | |
5590 | sp_addr +=2; | |
5591 | } | |
5592 | else | |
5593 | { | |
5594 | if (is_regp == 0) | |
5595 | tmp = (GPR32 (b+i)); | |
5596 | else | |
5597 | tmp = (GPR32 (b+i-1)); | |
5598 | ||
5599 | if ((a-i) > 1) | |
5600 | { | |
5601 | SLW (sp_addr, tmp); | |
5602 | sp_addr +=4; | |
5603 | } | |
5604 | else | |
5605 | { | |
5606 | SW (sp_addr, tmp); | |
5607 | sp_addr +=2; | |
5608 | } | |
5609 | ++i; | |
5610 | is_regp = 1; | |
5611 | } | |
5612 | } | |
5613 | ||
5614 | if (c == 1) | |
5615 | { | |
5616 | /* Store RA address. */ | |
5617 | tmp = (GPR32 (14)); | |
5618 | SLW(sp_addr,tmp); | |
5619 | sp_addr = (GPR32 (15)) - (a * 2) - 4; | |
5620 | } | |
5621 | else | |
5622 | sp_addr = (GPR32 (15)) - (a * 2); | |
5623 | ||
5624 | SET_GPR32 (15, sp_addr); /* Update SP address. */ | |
5625 | ||
5626 | trace_output_void (); | |
5627 | } | |
5628 | ||
5629 | ||
5630 | /* push. */ | |
5631 | void | |
5632 | OP_11E_10 () | |
5633 | { | |
5634 | uint32 sp_addr = (GPR32 (15)), tmp; | |
5635 | trace_input ("push", OP_VOID, OP_VOID, OP_VOID); | |
5636 | tmp = (GPR32 (14)); | |
5637 | SLW(sp_addr-4,tmp); /* Store RA address. */ | |
5638 | SET_GPR32 (15, (sp_addr - 4)); /* Update SP address. */ | |
5639 | trace_output_void (); | |
5640 | } | |
5641 | ||
5642 | ||
5643 | /* pop. */ | |
5644 | void | |
5645 | OP_5_9 () | |
5646 | { | |
5647 | uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0; | |
5648 | uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;; | |
5649 | trace_input ("pop", OP_CONSTANT3, OP_REG, OP_REG); | |
5650 | ||
5651 | for (; i < a; ++i) | |
5652 | { | |
5653 | if ((b+i) <= 11) | |
5654 | { | |
5655 | SET_GPR ((b+i), RW(sp_addr)); | |
5656 | sp_addr +=2; | |
5657 | } | |
5658 | else | |
5659 | { | |
5660 | if ((a-i) > 1) | |
5661 | { | |
5662 | tmp = RLW(sp_addr); | |
5663 | sp_addr +=4; | |
5664 | } | |
5665 | else | |
5666 | { | |
5667 | tmp = RW(sp_addr); | |
5668 | sp_addr +=2; | |
5669 | ||
5670 | if (is_regp == 0) | |
5671 | tmp = (tmp << 16) | (GPR32 (b+i)); | |
5672 | else | |
5673 | tmp = (tmp << 16) | (GPR32 (b+i-1)); | |
5674 | } | |
5675 | ||
5676 | if (is_regp == 0) | |
5677 | SET_GPR32 ((b+i), (((tmp & 0xffff) << 16) | |
5678 | | ((tmp >> 16) & 0xffff))); | |
5679 | else | |
5680 | SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16) | |
5681 | | ((tmp >> 16) & 0xffff))); | |
5682 | ||
5683 | ++i; | |
5684 | is_regp = 1; | |
5685 | } | |
5686 | } | |
5687 | ||
5688 | tmp = RLW(sp_addr); /* store RA also. */ | |
5689 | SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff))); | |
5690 | ||
5691 | SET_GPR32 (15, (sp_addr + 4)); /* Update SP address. */ | |
5692 | ||
5693 | trace_output_void (); | |
5694 | } | |
5695 | ||
5696 | /* pop. */ | |
5697 | void | |
5698 | OP_2_8 () | |
5699 | { | |
5700 | uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0; | |
5701 | uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0; | |
5702 | trace_input ("pop", OP_CONSTANT3, OP_REG, OP_VOID); | |
5703 | ||
5704 | for (; i < a; ++i) | |
5705 | { | |
5706 | if ((b+i) <= 11) | |
5707 | { | |
5708 | SET_GPR ((b+i), RW(sp_addr)); | |
5709 | sp_addr +=2; | |
5710 | } | |
5711 | else | |
5712 | { | |
5713 | if ((a-i) > 1) | |
5714 | { | |
5715 | tmp = RLW(sp_addr); | |
5716 | sp_addr +=4; | |
5717 | } | |
5718 | else | |
5719 | { | |
5720 | tmp = RW(sp_addr); | |
5721 | sp_addr +=2; | |
5722 | ||
5723 | if (is_regp == 0) | |
5724 | tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i)); | |
5725 | else | |
5726 | tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i-1)); | |
5727 | } | |
5728 | ||
5729 | if (is_regp == 0) | |
5730 | SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff))); | |
5731 | else | |
5732 | SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff))); | |
5733 | ++i; | |
5734 | is_regp = 1; | |
5735 | } | |
5736 | } | |
5737 | ||
5738 | if (c == 1) | |
5739 | { | |
5740 | tmp = RLW(sp_addr); /* Store RA Reg. */ | |
5741 | SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff))); | |
5742 | sp_addr +=4; | |
5743 | } | |
5744 | ||
5745 | SET_GPR32 (15, sp_addr); /* Update SP address. */ | |
5746 | ||
5747 | trace_output_void (); | |
5748 | } | |
5749 | ||
5750 | /* pop. */ | |
5751 | void | |
5752 | OP_21E_10 () | |
5753 | { | |
5754 | uint32 sp_addr = GPR32 (15); | |
5755 | uint32 tmp; | |
5756 | trace_input ("pop", OP_VOID, OP_VOID, OP_VOID); | |
5757 | ||
5758 | tmp = RLW(sp_addr); | |
5759 | SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff))); | |
5760 | SET_GPR32 (15, (sp_addr+4)); /* Update SP address. */ | |
5761 | ||
5762 | trace_output_void (); | |
5763 | } | |
5764 | ||
5765 | /* popret. */ | |
5766 | void | |
5767 | OP_7_9 () | |
5768 | { | |
5769 | uint16 a = OP[0], b = OP[1]; | |
5770 | trace_input ("popret", OP_CONSTANT3, OP_REG, OP_REG); | |
5771 | OP_5_9 (); | |
5772 | JMP(((GPR32(14)) << 1) & 0xffffff); | |
5773 | ||
5774 | trace_output_void (); | |
5775 | } | |
5776 | ||
5777 | /* popret. */ | |
5778 | void | |
5779 | OP_3_8 () | |
5780 | { | |
5781 | uint16 a = OP[0], b = OP[1]; | |
5782 | trace_input ("popret", OP_CONSTANT3, OP_REG, OP_VOID); | |
5783 | OP_2_8 (); | |
5784 | JMP(((GPR32(14)) << 1) & 0xffffff); | |
5785 | ||
5786 | trace_output_void (); | |
5787 | } | |
5788 | ||
5789 | /* popret. */ | |
5790 | void | |
5791 | OP_31E_10 () | |
5792 | { | |
5793 | uint32 tmp; | |
5794 | trace_input ("popret", OP_VOID, OP_VOID, OP_VOID); | |
5795 | OP_21E_10 (); | |
5796 | tmp = (((GPR32(14)) << 1) & 0xffffff); | |
5797 | /* If the resulting PC value is less than 0x00_0000 or greater | |
5798 | than 0xFF_FFFF, this instruction causes an IAD trap.*/ | |
5799 | ||
5800 | if ((tmp < 0x0) || (tmp > 0xFFFFFF)) | |
5801 | { | |
5802 | State.exception = SIG_CR16_BUS; | |
5803 | State.pc_changed = 1; /* Don't increment the PC. */ | |
5804 | trace_output_void (); | |
5805 | return; | |
5806 | } | |
5807 | else | |
5808 | JMP (tmp); | |
5809 | ||
5810 | trace_output_32 (tmp); | |
5811 | } | |
5812 | ||
5813 | ||
5814 | /* cinv[i]. */ | |
5815 | void | |
5816 | OP_A_10 () | |
5817 | { | |
5818 | trace_input ("cinv[i]", OP_VOID, OP_VOID, OP_VOID); | |
5819 | SET_PSR_I (1); | |
5820 | trace_output_void (); | |
5821 | } | |
5822 | ||
5823 | /* cinv[i,u]. */ | |
5824 | void | |
5825 | OP_B_10 () | |
5826 | { | |
5827 | trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID); | |
5828 | SET_PSR_I (1); | |
5829 | trace_output_void (); | |
5830 | } | |
5831 | ||
5832 | /* cinv[d]. */ | |
5833 | void | |
5834 | OP_C_10 () | |
5835 | { | |
5836 | trace_input ("cinv[d]", OP_VOID, OP_VOID, OP_VOID); | |
5837 | SET_PSR_I (1); | |
5838 | trace_output_void (); | |
5839 | } | |
5840 | ||
5841 | /* cinv[d,u]. */ | |
5842 | void | |
5843 | OP_D_10 () | |
5844 | { | |
5845 | trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID); | |
5846 | SET_PSR_I (1); | |
5847 | trace_output_void (); | |
5848 | } | |
5849 | ||
5850 | /* cinv[d,i]. */ | |
5851 | void | |
5852 | OP_E_10 () | |
5853 | { | |
5854 | trace_input ("cinv[d,i]", OP_VOID, OP_VOID, OP_VOID); | |
5855 | SET_PSR_I (1); | |
5856 | trace_output_void (); | |
5857 | } | |
5858 | ||
5859 | /* cinv[d,i,u]. */ | |
5860 | void | |
5861 | OP_F_10 () | |
5862 | { | |
5863 | trace_input ("cinv[d,i,u]", OP_VOID, OP_VOID, OP_VOID); | |
5864 | SET_PSR_I (1); | |
5865 | trace_output_void (); | |
5866 | } | |
5867 | ||
5868 | /* retx. */ | |
5869 | void | |
5870 | OP_3_10 () | |
5871 | { | |
5872 | trace_input ("retx", OP_VOID, OP_VOID, OP_VOID); | |
5873 | SET_PSR_I (1); | |
5874 | trace_output_void (); | |
5875 | } | |
5876 | ||
5877 | /* di. */ | |
5878 | void | |
5879 | OP_4_10 () | |
5880 | { | |
5881 | trace_input ("di", OP_VOID, OP_VOID, OP_VOID); | |
5882 | SET_PSR_I (1); | |
5883 | trace_output_void (); | |
5884 | } | |
5885 | ||
5886 | /* ei. */ | |
5887 | void | |
5888 | OP_5_10 () | |
5889 | { | |
5890 | trace_input ("ei", OP_VOID, OP_VOID, OP_VOID); | |
5891 | SET_PSR_I (1); | |
5892 | trace_output_void (); | |
5893 | } | |
5894 | ||
5895 | /* wait. */ | |
5896 | void | |
5897 | OP_6_10 () | |
5898 | { | |
5899 | trace_input ("wait", OP_VOID, OP_VOID, OP_VOID); | |
5900 | State.exception = SIGTRAP; | |
5901 | trace_output_void (); | |
5902 | } | |
5903 | ||
5904 | /* ewait. */ | |
5905 | void | |
5906 | OP_7_10 () | |
5907 | { | |
5908 | trace_input ("ewait", OP_VOID, OP_VOID, OP_VOID); | |
5909 | SET_PSR_I (1); | |
5910 | trace_output_void (); | |
5911 | } | |
5912 | ||
5913 | /* xorb. */ | |
5914 | void | |
5915 | OP_28_8 () | |
5916 | { | |
5917 | uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; | |
5918 | trace_input ("xorb", OP_CONSTANT4, OP_REG, OP_VOID); | |
5919 | tmp = a ^ b; | |
5920 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
5921 | trace_output_16 (tmp); | |
5922 | } | |
5923 | ||
5924 | /* xorb. */ | |
5925 | void | |
5926 | OP_28B_C () | |
5927 | { | |
5928 | uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; | |
5929 | trace_input ("xorb", OP_CONSTANT16, OP_REG, OP_VOID); | |
5930 | tmp = a ^ b; | |
5931 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
5932 | trace_output_16 (tmp); | |
5933 | } | |
5934 | ||
5935 | /* xorb. */ | |
5936 | void | |
5937 | OP_29_8 () | |
5938 | { | |
5939 | uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; | |
5940 | trace_input ("xorb", OP_REG, OP_REG, OP_VOID); | |
5941 | tmp = a ^ b; | |
5942 | SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); | |
5943 | trace_output_16 (tmp); | |
5944 | } | |
5945 | ||
5946 | /* xorw. */ | |
5947 | void | |
5948 | OP_2A_8 () | |
5949 | { | |
5950 | uint16 tmp, a = (OP[0]), b = (GPR (OP[1])); | |
5951 | trace_input ("xorw", OP_CONSTANT4, OP_REG, OP_VOID); | |
5952 | tmp = a ^ b; | |
5953 | SET_GPR (OP[1], tmp); | |
5954 | trace_output_16 (tmp); | |
5955 | } | |
5956 | ||
5957 | /* xorw. */ | |
5958 | void | |
5959 | OP_2AB_C () | |
5960 | { | |
5961 | uint16 tmp, a = (OP[0]), b = (GPR (OP[1])); | |
5962 | trace_input ("xorw", OP_CONSTANT16, OP_REG, OP_VOID); | |
5963 | tmp = a ^ b; | |
5964 | SET_GPR (OP[1], tmp); | |
5965 | trace_output_16 (tmp); | |
5966 | } | |
5967 | ||
5968 | /* xorw. */ | |
5969 | void | |
5970 | OP_2B_8 () | |
5971 | { | |
5972 | uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1])); | |
5973 | trace_input ("xorw", OP_REG, OP_REG, OP_VOID); | |
5974 | tmp = a ^ b; | |
5975 | SET_GPR (OP[1], tmp); | |
5976 | trace_output_16 (tmp); | |
5977 | } | |
5978 | ||
5979 | /*REVISIT FOR LPR/SPR . */ | |
5980 | ||
5981 | /* lpr. */ | |
5982 | void | |
5983 | OP_140_14 () | |
5984 | { | |
5985 | uint16 a = GPR (OP[0]); | |
5986 | trace_input ("lpr", OP_REG, OP_REG, OP_VOID); | |
5987 | SET_CREG (OP[1], a); | |
5988 | trace_output_16 (a); | |
5989 | } | |
5990 | ||
5991 | /* lprd. */ | |
5992 | void | |
5993 | OP_141_14 () | |
5994 | { | |
5995 | uint32 a = GPR32 (OP[0]); | |
5996 | trace_input ("lprd", OP_REGP, OP_REG, OP_VOID); | |
5997 | SET_CREG (OP[1], a); | |
5998 | trace_output_flag (); | |
5999 | } | |
6000 | ||
6001 | /* spr. */ | |
6002 | void | |
6003 | OP_142_14 () | |
6004 | { | |
6005 | uint16 a = CREG (OP[0]); | |
6006 | trace_input ("spr", OP_REG, OP_REG, OP_VOID); | |
6007 | SET_GPR (OP[1], a); | |
6008 | trace_output_16 (a); | |
6009 | } | |
6010 | ||
6011 | /* sprd. */ | |
6012 | void | |
6013 | OP_143_14 () | |
6014 | { | |
6015 | uint32 a = CREG (OP[0]); | |
6016 | trace_input ("sprd", OP_REGP, OP_REGP, OP_VOID); | |
6017 | SET_GPR32 (OP[1], a); | |
6018 | trace_output_32 (a); | |
6019 | } | |
6020 | ||
6021 | /* null. */ | |
6022 | void | |
6023 | OP_0_20 () | |
6024 | { | |
6025 | trace_input ("null", OP_VOID, OP_VOID, OP_VOID); | |
6026 | State.exception = SIG_CR16_STOP; | |
6027 | } |