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f6bcefef HPN |
1 | /* CPU data header for cris. |
2 | ||
3 | THIS FILE IS MACHINE GENERATED WITH CGEN. | |
4 | ||
0f51e9bf | 5 | Copyright 1996-2010 Free Software Foundation, Inc. |
f6bcefef HPN |
6 | |
7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger. | |
8 | ||
c9b3544a HPN |
9 | This file is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
f6bcefef | 13 | |
c9b3544a HPN |
14 | It is distributed in the hope that it will be useful, but WITHOUT |
15 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | License for more details. | |
f6bcefef | 18 | |
c9b3544a HPN |
19 | You should have received a copy of the GNU General Public License along |
20 | with this program; if not, write to the Free Software Foundation, Inc., | |
21 | 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. | |
f6bcefef HPN |
22 | |
23 | */ | |
24 | ||
25 | #ifndef CRIS_CPU_H | |
26 | #define CRIS_CPU_H | |
27 | ||
28 | #define CGEN_ARCH cris | |
29 | ||
30 | /* Given symbol S, return cris_cgen_<S>. */ | |
f6bcefef | 31 | #define CGEN_SYM(s) cris##_cgen_##s |
f6bcefef HPN |
32 | |
33 | ||
34 | /* Selected cpu families. */ | |
35 | #define HAVE_CPU_CRISV0F | |
36 | #define HAVE_CPU_CRISV3F | |
37 | #define HAVE_CPU_CRISV8F | |
38 | #define HAVE_CPU_CRISV10F | |
39 | #define HAVE_CPU_CRISV32F | |
40 | ||
41 | #define CGEN_INSN_LSB0_P 1 | |
42 | ||
43 | /* Minimum size of any insn (in bytes). */ | |
44 | #define CGEN_MIN_INSN_SIZE 2 | |
45 | ||
46 | /* Maximum size of any insn (in bytes). */ | |
47 | #define CGEN_MAX_INSN_SIZE 6 | |
48 | ||
49 | #define CGEN_INT_INSN_P 0 | |
50 | ||
51 | /* Maximum number of syntax elements in an instruction. */ | |
52 | #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22 | |
53 | ||
54 | /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. | |
55 | e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands | |
56 | we can't hash on everything up to the space. */ | |
57 | #define CGEN_MNEMONIC_OPERANDS | |
58 | ||
59 | /* Maximum number of fields in an instruction. */ | |
60 | #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 6 | |
61 | ||
62 | /* Enums. */ | |
63 | ||
64 | /* Enum declaration for . */ | |
65 | typedef enum gr_names_pcreg { | |
66 | H_GR_REAL_PC_PC = 15, H_GR_REAL_PC_SP = 14, H_GR_REAL_PC_R0 = 0, H_GR_REAL_PC_R1 = 1 | |
67 | , H_GR_REAL_PC_R2 = 2, H_GR_REAL_PC_R3 = 3, H_GR_REAL_PC_R4 = 4, H_GR_REAL_PC_R5 = 5 | |
68 | , H_GR_REAL_PC_R6 = 6, H_GR_REAL_PC_R7 = 7, H_GR_REAL_PC_R8 = 8, H_GR_REAL_PC_R9 = 9 | |
69 | , H_GR_REAL_PC_R10 = 10, H_GR_REAL_PC_R11 = 11, H_GR_REAL_PC_R12 = 12, H_GR_REAL_PC_R13 = 13 | |
70 | , H_GR_REAL_PC_R14 = 14 | |
71 | } GR_NAMES_PCREG; | |
72 | ||
73 | /* Enum declaration for . */ | |
74 | typedef enum gr_names_acr { | |
75 | H_GR_ACR = 15, H_GR_SP = 14, H_GR_R0 = 0, H_GR_R1 = 1 | |
76 | , H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4, H_GR_R5 = 5 | |
77 | , H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8, H_GR_R9 = 9 | |
78 | , H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12, H_GR_R13 = 13 | |
79 | , H_GR_R14 = 14 | |
80 | } GR_NAMES_ACR; | |
81 | ||
82 | /* Enum declaration for . */ | |
83 | typedef enum gr_names_v32 { | |
84 | H_GR_V32_ACR = 15, H_GR_V32_SP = 14, H_GR_V32_R0 = 0, H_GR_V32_R1 = 1 | |
85 | , H_GR_V32_R2 = 2, H_GR_V32_R3 = 3, H_GR_V32_R4 = 4, H_GR_V32_R5 = 5 | |
86 | , H_GR_V32_R6 = 6, H_GR_V32_R7 = 7, H_GR_V32_R8 = 8, H_GR_V32_R9 = 9 | |
87 | , H_GR_V32_R10 = 10, H_GR_V32_R11 = 11, H_GR_V32_R12 = 12, H_GR_V32_R13 = 13 | |
88 | , H_GR_V32_R14 = 14 | |
89 | } GR_NAMES_V32; | |
90 | ||
91 | /* Enum declaration for . */ | |
92 | typedef enum p_names_v10 { | |
93 | H_SR_PRE_V32_CCR = 5, H_SR_PRE_V32_MOF = 7, H_SR_PRE_V32_IBR = 9, H_SR_PRE_V32_IRP = 10 | |
94 | , H_SR_PRE_V32_BAR = 12, H_SR_PRE_V32_DCCR = 13, H_SR_PRE_V32_BRP = 14, H_SR_PRE_V32_USP = 15 | |
95 | , H_SR_PRE_V32_VR = 1, H_SR_PRE_V32_SRP = 11, H_SR_PRE_V32_P0 = 0, H_SR_PRE_V32_P1 = 1 | |
96 | , H_SR_PRE_V32_P2 = 2, H_SR_PRE_V32_P3 = 3, H_SR_PRE_V32_P4 = 4, H_SR_PRE_V32_P5 = 5 | |
97 | , H_SR_PRE_V32_P6 = 6, H_SR_PRE_V32_P7 = 7, H_SR_PRE_V32_P8 = 8, H_SR_PRE_V32_P9 = 9 | |
98 | , H_SR_PRE_V32_P10 = 10, H_SR_PRE_V32_P11 = 11, H_SR_PRE_V32_P12 = 12, H_SR_PRE_V32_P13 = 13 | |
99 | , H_SR_PRE_V32_P14 = 14 | |
100 | } P_NAMES_V10; | |
101 | ||
102 | /* Enum declaration for . */ | |
103 | typedef enum p_names_v32 { | |
104 | H_SR_BZ = 0, H_SR_PID = 2, H_SR_SRS = 3, H_SR_WZ = 4 | |
105 | , H_SR_EXS = 5, H_SR_EDA = 6, H_SR_MOF = 7, H_SR_DZ = 8 | |
106 | , H_SR_EBP = 9, H_SR_ERP = 10, H_SR_NRP = 12, H_SR_CCS = 13 | |
107 | , H_SR_USP = 14, H_SR_SPC = 15, H_SR_VR = 1, H_SR_SRP = 11 | |
108 | , H_SR_P0 = 0, H_SR_P1 = 1, H_SR_P2 = 2, H_SR_P3 = 3 | |
109 | , H_SR_P4 = 4, H_SR_P5 = 5, H_SR_P6 = 6, H_SR_P7 = 7 | |
110 | , H_SR_P8 = 8, H_SR_P9 = 9, H_SR_P10 = 10, H_SR_P11 = 11 | |
111 | , H_SR_P12 = 12, H_SR_P13 = 13, H_SR_P14 = 14 | |
112 | } P_NAMES_V32; | |
113 | ||
114 | /* Enum declaration for . */ | |
115 | typedef enum p_names_v32_x { | |
116 | H_SR_V32_BZ = 0, H_SR_V32_PID = 2, H_SR_V32_SRS = 3, H_SR_V32_WZ = 4 | |
117 | , H_SR_V32_EXS = 5, H_SR_V32_EDA = 6, H_SR_V32_MOF = 7, H_SR_V32_DZ = 8 | |
118 | , H_SR_V32_EBP = 9, H_SR_V32_ERP = 10, H_SR_V32_NRP = 12, H_SR_V32_CCS = 13 | |
119 | , H_SR_V32_USP = 14, H_SR_V32_SPC = 15, H_SR_V32_VR = 1, H_SR_V32_SRP = 11 | |
120 | , H_SR_V32_P0 = 0, H_SR_V32_P1 = 1, H_SR_V32_P2 = 2, H_SR_V32_P3 = 3 | |
121 | , H_SR_V32_P4 = 4, H_SR_V32_P5 = 5, H_SR_V32_P6 = 6, H_SR_V32_P7 = 7 | |
122 | , H_SR_V32_P8 = 8, H_SR_V32_P9 = 9, H_SR_V32_P10 = 10, H_SR_V32_P11 = 11 | |
123 | , H_SR_V32_P12 = 12, H_SR_V32_P13 = 13, H_SR_V32_P14 = 14 | |
124 | } P_NAMES_V32_X; | |
125 | ||
126 | /* Enum declaration for Standard instruction operand size. */ | |
127 | typedef enum insn_size { | |
128 | SIZE_BYTE, SIZE_WORD, SIZE_DWORD, SIZE_FIXED | |
129 | } INSN_SIZE; | |
130 | ||
131 | /* Enum declaration for Standard instruction addressing modes. */ | |
132 | typedef enum insn_mode { | |
133 | MODE_QUICK_IMMEDIATE, MODE_REGISTER, MODE_INDIRECT, MODE_AUTOINCREMENT | |
134 | } INSN_MODE; | |
135 | ||
136 | /* Enum declaration for Whether the operand is indirect. */ | |
137 | typedef enum insn_memoryness_mode { | |
138 | MODEMEMP_NO, MODEMEMP_YES | |
139 | } INSN_MEMORYNESS_MODE; | |
140 | ||
141 | /* Enum declaration for Whether the indirect operand is autoincrement. */ | |
142 | typedef enum insn_memincness_mode { | |
143 | MODEINCP_NO, MODEINCP_YES | |
144 | } INSN_MEMINCNESS_MODE; | |
145 | ||
146 | /* Enum declaration for Signed instruction operand size. */ | |
147 | typedef enum insn_signed_size { | |
148 | SIGNED_UNDEF_SIZE_0, SIGNED_UNDEF_SIZE_1, SIGNED_BYTE, SIGNED_WORD | |
149 | } INSN_SIGNED_SIZE; | |
150 | ||
151 | /* Enum declaration for Unsigned instruction operand size. */ | |
152 | typedef enum insn_unsigned_size { | |
153 | UNSIGNED_BYTE, UNSIGNED_WORD, UNSIGNED_UNDEF_SIZE_2, UNSIGNED_UNDEF_SIZE_3 | |
154 | } INSN_UNSIGNED_SIZE; | |
155 | ||
156 | /* Enum declaration for Insns for MODE_QUICK_IMMEDIATE. */ | |
157 | typedef enum insn_qi_opc { | |
158 | Q_BCC_0, Q_BCC_1, Q_BCC_2, Q_BCC_3 | |
159 | , Q_BDAP_0, Q_BDAP_1, Q_BDAP_2, Q_BDAP_3 | |
160 | , Q_ADDQ, Q_MOVEQ, Q_SUBQ, Q_CMPQ | |
161 | , Q_ANDQ, Q_ORQ, Q_ASHQ, Q_LSHQ | |
162 | } INSN_QI_OPC; | |
163 | ||
164 | /* Enum declaration for Same as insn-qi-opc, though using only the high two bits of the opcode. */ | |
165 | typedef enum insn_qihi_opc { | |
166 | QHI_BCC, QHI_BDAP, QHI_OTHER2, QHI_OTHER3 | |
167 | } INSN_QIHI_OPC; | |
168 | ||
169 | /* Enum declaration for Insns for MODE_REGISTER and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD. */ | |
170 | typedef enum insn_r_opc { | |
171 | R_ADDX, R_MOVX, R_SUBX, R_LSL | |
172 | , R_ADDI, R_BIAP, R_NEG, R_BOUND | |
173 | , R_ADD, R_MOVE, R_SUB, R_CMP | |
174 | , R_AND, R_OR, R_ASR, R_LSR | |
175 | } INSN_R_OPC; | |
176 | ||
177 | /* Enum declaration for Insns for MODE_REGISTER and SIZE_FIXED. */ | |
178 | typedef enum insn_rfix_opc { | |
179 | RFIX_ADDX, RFIX_MOVX, RFIX_SUBX, RFIX_BTST | |
180 | , RFIX_SCC, RFIX_ADDC, RFIX_SETF, RFIX_CLEARF | |
181 | , RFIX_MOVE_R_S, RFIX_MOVE_S_R, RFIX_ABS, RFIX_DSTEP | |
182 | , RFIX_LZ, RFIX_SWAP, RFIX_XOR, RFIX_MSTEP | |
183 | } INSN_RFIX_OPC; | |
184 | ||
185 | /* Enum declaration for Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD. */ | |
186 | typedef enum insn_indir_opc { | |
187 | INDIR_ADDX, INDIR_MOVX, INDIR_SUBX, INDIR_CMPX | |
188 | , INDIR_MUL, INDIR_BDAP_M, INDIR_ADDC, INDIR_BOUND | |
189 | , INDIR_ADD, INDIR_MOVE_M_R, INDIR_SUB, INDIR_CMP | |
190 | , INDIR_AND, INDIR_OR, INDIR_TEST, INDIR_MOVE_R_M | |
191 | } INSN_INDIR_OPC; | |
192 | ||
193 | /* Enum declaration for Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and SIZE_FIXED. */ | |
194 | typedef enum insn_infix_opc { | |
195 | INFIX_ADDX, INFIX_MOVX, INFIX_SUBX, INFIX_CMPX | |
196 | , INFIX_JUMP_M, INFIX_DIP, INFIX_JUMP_R, INFIX_BCC_M | |
197 | , INFIX_MOVE_M_S, INFIX_MOVE_S_M, INFIX_BMOD, INFIX_BSTORE | |
198 | , INFIX_RBF, INFIX_SBFS, INFIX_MOVEM_M_R, INFIX_MOVEM_R_M | |
199 | } INSN_INFIX_OPC; | |
200 | ||
201 | /* Attributes. */ | |
202 | ||
203 | /* Enum declaration for machine type selection. */ | |
204 | typedef enum mach_attr { | |
205 | MACH_BASE, MACH_CRISV0, MACH_CRISV3, MACH_CRISV8 | |
206 | , MACH_CRISV10, MACH_CRISV32, MACH_MAX | |
207 | } MACH_ATTR; | |
208 | ||
209 | /* Enum declaration for instruction set selection. */ | |
210 | typedef enum isa_attr { | |
211 | ISA_CRIS, ISA_MAX | |
212 | } ISA_ATTR; | |
213 | ||
214 | /* Number of architecture variants. */ | |
215 | #define MAX_ISAS 1 | |
216 | #define MAX_MACHS ((int) MACH_MAX) | |
217 | ||
218 | /* Ifield support. */ | |
219 | ||
f6bcefef HPN |
220 | /* Ifield attribute indices. */ |
221 | ||
222 | /* Enum declaration for cgen_ifld attrs. */ | |
223 | typedef enum cgen_ifld_attr { | |
224 | CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED | |
225 | , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 | |
226 | , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS | |
227 | } CGEN_IFLD_ATTR; | |
228 | ||
229 | /* Number of non-boolean elements in cgen_ifld_attr. */ | |
230 | #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) | |
231 | ||
cf2bf87e HPN |
232 | /* cgen_ifld attribute accessor macros. */ |
233 | #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) | |
234 | #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) | |
235 | #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) | |
236 | #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) | |
237 | #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) | |
238 | #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) | |
239 | #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) | |
240 | ||
f6bcefef HPN |
241 | /* Enum declaration for cris ifield types. */ |
242 | typedef enum ifield_type { | |
243 | CRIS_F_NIL, CRIS_F_ANYOF, CRIS_F_OPERAND1, CRIS_F_SIZE | |
244 | , CRIS_F_OPCODE, CRIS_F_MODE, CRIS_F_OPERAND2, CRIS_F_MEMMODE | |
245 | , CRIS_F_MEMBIT, CRIS_F_B5, CRIS_F_OPCODE_HI, CRIS_F_DSTSRC | |
246 | , CRIS_F_U6, CRIS_F_S6, CRIS_F_U5, CRIS_F_U4 | |
247 | , CRIS_F_S8, CRIS_F_DISP9_HI, CRIS_F_DISP9_LO, CRIS_F_DISP9 | |
248 | , CRIS_F_QO, CRIS_F_INDIR_PC__BYTE, CRIS_F_INDIR_PC__WORD, CRIS_F_INDIR_PC__WORD_PCREL | |
249 | , CRIS_F_INDIR_PC__DWORD, CRIS_F_INDIR_PC__DWORD_PCREL, CRIS_F_MAX | |
250 | } IFIELD_TYPE; | |
251 | ||
252 | #define MAX_IFLD ((int) CRIS_F_MAX) | |
253 | ||
254 | /* Hardware attribute indices. */ | |
255 | ||
256 | /* Enum declaration for cgen_hw attrs. */ | |
257 | typedef enum cgen_hw_attr { | |
258 | CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE | |
259 | , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS | |
260 | } CGEN_HW_ATTR; | |
261 | ||
262 | /* Number of non-boolean elements in cgen_hw_attr. */ | |
263 | #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) | |
264 | ||
cf2bf87e HPN |
265 | /* cgen_hw attribute accessor macros. */ |
266 | #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) | |
267 | #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) | |
268 | #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) | |
269 | #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) | |
270 | #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) | |
271 | ||
f6bcefef HPN |
272 | /* Enum declaration for cris hardware types. */ |
273 | typedef enum cgen_hw_type { | |
274 | HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR | |
275 | , HW_H_IADDR, HW_H_INC, HW_H_CCODE, HW_H_SWAP | |
276 | , HW_H_FLAGBITS, HW_H_V32, HW_H_PC, HW_H_GR | |
277 | , HW_H_GR_X, HW_H_GR_REAL_PC, HW_H_RAW_GR, HW_H_SR | |
278 | , HW_H_SR_X, HW_H_SUPR, HW_H_CBIT, HW_H_CBIT_MOVE | |
279 | , HW_H_CBIT_MOVE_X, HW_H_VBIT, HW_H_VBIT_MOVE, HW_H_VBIT_MOVE_X | |
280 | , HW_H_ZBIT, HW_H_ZBIT_MOVE, HW_H_ZBIT_MOVE_X, HW_H_NBIT | |
281 | , HW_H_NBIT_MOVE, HW_H_NBIT_MOVE_X, HW_H_XBIT, HW_H_IBIT | |
282 | , HW_H_IBIT_X, HW_H_PBIT, HW_H_RBIT, HW_H_UBIT | |
283 | , HW_H_UBIT_X, HW_H_GBIT, HW_H_KERNEL_SP, HW_H_MBIT | |
284 | , HW_H_QBIT, HW_H_SBIT, HW_H_INSN_PREFIXED_P, HW_H_INSN_PREFIXED_P_X | |
285 | , HW_H_PREFIXREG, HW_MAX | |
286 | } CGEN_HW_TYPE; | |
287 | ||
288 | #define MAX_HW ((int) HW_MAX) | |
289 | ||
290 | /* Operand attribute indices. */ | |
291 | ||
292 | /* Enum declaration for cgen_operand attrs. */ | |
293 | typedef enum cgen_operand_attr { | |
294 | CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT | |
295 | , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY | |
296 | , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS | |
297 | } CGEN_OPERAND_ATTR; | |
298 | ||
299 | /* Number of non-boolean elements in cgen_operand_attr. */ | |
300 | #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) | |
301 | ||
cf2bf87e HPN |
302 | /* cgen_operand attribute accessor macros. */ |
303 | #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) | |
304 | #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) | |
305 | #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) | |
306 | #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) | |
307 | #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) | |
308 | #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) | |
309 | #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) | |
310 | #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) | |
311 | #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) | |
312 | ||
f6bcefef HPN |
313 | /* Enum declaration for cris operand types. */ |
314 | typedef enum cgen_operand_type { | |
315 | CRIS_OPERAND_PC, CRIS_OPERAND_CBIT, CRIS_OPERAND_CBIT_MOVE, CRIS_OPERAND_VBIT | |
316 | , CRIS_OPERAND_VBIT_MOVE, CRIS_OPERAND_ZBIT, CRIS_OPERAND_ZBIT_MOVE, CRIS_OPERAND_NBIT | |
317 | , CRIS_OPERAND_NBIT_MOVE, CRIS_OPERAND_XBIT, CRIS_OPERAND_IBIT, CRIS_OPERAND_UBIT | |
318 | , CRIS_OPERAND_PBIT, CRIS_OPERAND_RBIT, CRIS_OPERAND_SBIT, CRIS_OPERAND_MBIT | |
319 | , CRIS_OPERAND_QBIT, CRIS_OPERAND_PREFIX_SET, CRIS_OPERAND_PREFIXREG, CRIS_OPERAND_RS | |
320 | , CRIS_OPERAND_INC, CRIS_OPERAND_PS, CRIS_OPERAND_SS, CRIS_OPERAND_SD | |
321 | , CRIS_OPERAND_I, CRIS_OPERAND_J, CRIS_OPERAND_C, CRIS_OPERAND_QO | |
322 | , CRIS_OPERAND_RD, CRIS_OPERAND_SCONST8, CRIS_OPERAND_UCONST8, CRIS_OPERAND_SCONST16 | |
323 | , CRIS_OPERAND_UCONST16, CRIS_OPERAND_CONST32, CRIS_OPERAND_CONST32_PCREL, CRIS_OPERAND_PD | |
324 | , CRIS_OPERAND_O, CRIS_OPERAND_O_PCREL, CRIS_OPERAND_O_WORD_PCREL, CRIS_OPERAND_CC | |
325 | , CRIS_OPERAND_N, CRIS_OPERAND_SWAPOPTION, CRIS_OPERAND_LIST_OF_FLAGS, CRIS_OPERAND_MAX | |
326 | } CGEN_OPERAND_TYPE; | |
327 | ||
328 | /* Number of operands types. */ | |
329 | #define MAX_OPERANDS 43 | |
330 | ||
331 | /* Maximum number of operands referenced by any insn. */ | |
332 | #define MAX_OPERAND_INSTANCES 8 | |
333 | ||
334 | /* Insn attribute indices. */ | |
335 | ||
336 | /* Enum declaration for cgen_insn attrs. */ | |
337 | typedef enum cgen_insn_attr { | |
338 | CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI | |
339 | , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED | |
340 | , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 | |
341 | , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS | |
342 | } CGEN_INSN_ATTR; | |
343 | ||
344 | /* Number of non-boolean elements in cgen_insn_attr. */ | |
345 | #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) | |
346 | ||
cf2bf87e HPN |
347 | /* cgen_insn attribute accessor macros. */ |
348 | #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) | |
349 | #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) | |
350 | #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) | |
351 | #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) | |
352 | #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) | |
353 | #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) | |
354 | #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) | |
355 | #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) | |
356 | #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) | |
357 | #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) | |
358 | #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) | |
359 | ||
f6bcefef HPN |
360 | /* cgen.h uses things we just defined. */ |
361 | #include "opcode/cgen.h" | |
362 | ||
cce0efb5 HPN |
363 | extern const struct cgen_ifld cris_cgen_ifld_table[]; |
364 | ||
f6bcefef HPN |
365 | /* Attributes. */ |
366 | extern const CGEN_ATTR_TABLE cris_cgen_hardware_attr_table[]; | |
367 | extern const CGEN_ATTR_TABLE cris_cgen_ifield_attr_table[]; | |
368 | extern const CGEN_ATTR_TABLE cris_cgen_operand_attr_table[]; | |
369 | extern const CGEN_ATTR_TABLE cris_cgen_insn_attr_table[]; | |
370 | ||
371 | /* Hardware decls. */ | |
372 | ||
373 | extern CGEN_KEYWORD cris_cgen_opval_h_inc; | |
374 | extern CGEN_KEYWORD cris_cgen_opval_h_ccode; | |
375 | extern CGEN_KEYWORD cris_cgen_opval_h_swap; | |
376 | extern CGEN_KEYWORD cris_cgen_opval_h_flagbits; | |
377 | extern CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg; | |
378 | extern CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg; | |
379 | extern CGEN_KEYWORD cris_cgen_opval_gr_names_acr; | |
380 | extern CGEN_KEYWORD cris_cgen_opval_p_names_v10; | |
381 | extern CGEN_KEYWORD cris_cgen_opval_p_names_v10; | |
382 | extern CGEN_KEYWORD cris_cgen_opval_p_names_v10; | |
383 | extern CGEN_KEYWORD cris_cgen_opval_p_names_v10; | |
384 | extern CGEN_KEYWORD cris_cgen_opval_p_names_v32; | |
385 | extern CGEN_KEYWORD cris_cgen_opval_h_supr; | |
386 | ||
387 | extern const CGEN_HW_ENTRY cris_cgen_hw_table[]; | |
388 | ||
389 | ||
390 | ||
391 | #endif /* CRIS_CPU_H */ |