Commit | Line | Data |
---|---|---|
f6bcefef | 1 | /* CRIS v10 simulator support code |
32d0add0 | 2 | Copyright (C) 2004-2015 Free Software Foundation, Inc. |
f6bcefef HPN |
3 | Contributed by Axis Communications. |
4 | ||
5 | This file is part of the GNU simulators. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
9 | the Free Software Foundation; either version 3 of the License, or |
10 | (at your option) any later version. | |
f6bcefef HPN |
11 | |
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
4744ac1b JB |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
f6bcefef HPN |
19 | |
20 | /* The infrastructure is based on that of i960.c. */ | |
21 | ||
22 | #define WANT_CPU_CRISV10F | |
23 | ||
24 | #define BASENUM 10 | |
ddf2c972 | 25 | #define CRIS_TLS_REGISTER 14 |
f6bcefef HPN |
26 | #include "cris-tmpl.c" |
27 | ||
28 | #if WITH_PROFILE_MODEL_P | |
29 | ||
30 | /* Model function for u-multiply unit. */ | |
31 | ||
32 | int | |
33 | MY (XCONCAT3 (f_model_crisv,BASENUM, | |
34 | _u_multiply)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED, | |
35 | const IDESC *idesc ATTRIBUTE_UNUSED, | |
36 | int unit_num ATTRIBUTE_UNUSED, | |
37 | int referenced ATTRIBUTE_UNUSED) | |
38 | { | |
39 | return 1; | |
40 | } | |
41 | ||
42 | #endif /* WITH_PROFILE_MODEL_P */ | |
aad3b3cb HPN |
43 | |
44 | /* Do the interrupt sequence if possible, and return 1. If interrupts | |
45 | are disabled or some other lockout is active, return 0 and do | |
46 | nothing. | |
47 | ||
48 | Beware, the v10 implementation is incomplete and doesn't properly | |
49 | lock out interrupts e.g. after special-register access and doesn't | |
50 | handle user-mode. */ | |
51 | ||
52 | int | |
53 | MY (deliver_interrupt) (SIM_CPU *current_cpu, | |
54 | enum cris_interrupt_type type, | |
55 | unsigned int vec) | |
56 | { | |
57 | unsigned char entryaddr_le[4]; | |
58 | int was_user; | |
59 | SIM_DESC sd = CPU_STATE (current_cpu); | |
60 | unsigned32 entryaddr; | |
61 | ||
62 | /* We haven't implemented other interrupt-types yet. */ | |
63 | if (type != CRIS_INT_INT) | |
64 | abort (); | |
65 | ||
66 | /* We're supposed to be called outside of prefixes and branch | |
67 | delay-slots etc, but why not check. */ | |
68 | if (GET_H_INSN_PREFIXED_P ()) | |
69 | abort (); | |
70 | ||
71 | if (!GET_H_IBIT ()) | |
72 | return 0; | |
73 | ||
74 | /* User mode isn't supported for interrupts. (And we shouldn't see | |
75 | this as 1 anyway. The user-mode bit isn't visible from user | |
76 | mode. It doesn't make it into the U bit until the next | |
77 | interrupt/exception.) */ | |
78 | if (GET_H_UBIT ()) | |
79 | abort (); | |
80 | ||
81 | SET_H_PBIT (1); | |
82 | ||
83 | if (sim_core_read_buffer (sd, | |
84 | current_cpu, | |
85 | read_map, entryaddr_le, | |
86 | GET_H_SR (H_SR_PRE_V32_IBR) + vec * 4, 4) == 0) | |
87 | { | |
88 | /* Nothing to do actually; either abort or send a signal. */ | |
034685f9 | 89 | sim_core_signal (sd, current_cpu, CPU_PC_GET (current_cpu), 0, 4, |
aad3b3cb HPN |
90 | GET_H_SR (H_SR_PRE_V32_IBR) + vec * 4, |
91 | read_transfer, sim_core_unmapped_signal); | |
92 | return 0; | |
93 | } | |
94 | ||
95 | entryaddr = bfd_getl32 (entryaddr_le); | |
96 | ||
97 | SET_H_SR (H_SR_PRE_V32_IRP, GET_H_PC ()); | |
98 | SET_H_PC (entryaddr); | |
99 | ||
100 | return 1; | |
101 | } |