[deliverable/binutils-gdb.git] / sim / d10v / d10v_sim.h

#include "config.h"
#include <stdio.h>
#include <ctype.h>
#include <limits.h>
#include "ansidecl.h"
#include "callback.h"
#include "opcode/d10v.h"
#include "bfd.h"

#define DEBUG_TRACE		0x00000001
#define DEBUG_VALUES		0x00000002
#define DEBUG_LINE_NUMBER	0x00000004
#define DEBUG_MEMSIZE		0x00000008
#define DEBUG_INSTRUCTION	0x00000010
#define DEBUG_TRAP		0x00000020

#ifndef	DEBUG
#define	DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
#endif

extern int d10v_debug;

#include "remote-sim.h"
#include "sim-config.h"
#include "sim-types.h"

typedef unsigned8 uint8;
typedef unsigned16 uint16;
typedef signed16 int16;
typedef unsigned32 uint32;
typedef signed32 int32;
typedef unsigned64 uint64;
typedef signed64 int64;

/* FIXME: D10V defines */
typedef uint16 reg_t;

struct simops 
{
  long opcode;
  int  is_long;
  long mask;
  int format;
  int cycles;
  int unit;
  int exec_type;
  void (*func)();
  int numops;
  int operands[9];
};

enum _ins_type
{
  INS_UNKNOWN,			/* unknown instruction */
  INS_COND_TRUE,		/* # times EXExxx executed other instruction */
  INS_COND_FALSE,		/* # times EXExxx did not execute other instruction */
  INS_COND_JUMP,		/* # times JUMP skipped other instruction */
  INS_CYCLES,			/* # cycles */
  INS_LONG,			/* long instruction (both containers, ie FM == 11) */
  INS_LEFTRIGHT,		/* # times instruction encoded as L -> R (ie, FM == 01) */
  INS_RIGHTLEFT,		/* # times instruction encoded as L <- R (ie, FM == 10) */
  INS_PARALLEL,			/* # times instruction encoded as L || R (ie, RM == 00) */

  INS_LEFT,			/* normal left instructions */
  INS_LEFT_PARALLEL,		/* left side of || */
  INS_LEFT_COND_TEST,		/* EXExx test on left side */
  INS_LEFT_COND_EXE,		/* execution after EXExxx test on right side succeeded */
  INS_LEFT_NOPS,		/* NOP on left side */

  INS_RIGHT,			/* normal right instructions */
  INS_RIGHT_PARALLEL,		/* right side of || */
  INS_RIGHT_COND_TEST,		/* EXExx test on right side */
  INS_RIGHT_COND_EXE,		/* execution after EXExxx test on left side succeeded */
  INS_RIGHT_NOPS,		/* NOP on right side */

  INS_MAX
};

extern unsigned long ins_type_counters[ (int)INS_MAX ];

enum {
  SP_IDX = 15,
};

/* Write-back slots */
union slot_data {
  unsigned_1 _1;
  unsigned_2 _2;
  unsigned_4 _4;
  unsigned_8 _8;
};
struct slot {
  void *dest;
  int size;
  union slot_data data;
  union slot_data mask;
};
enum {
 NR_SLOTS = 16,
};
#define SLOT (State.slot)
#define SLOT_NR (State.slot_nr)
#define SLOT_PEND_MASK(DEST, MSK, VAL) \
  do \
    { \
      SLOT[SLOT_NR].dest = &(DEST); \
      SLOT[SLOT_NR].size = sizeof (DEST); \
      switch (sizeof (DEST)) \
        { \
        case 1: \
          SLOT[SLOT_NR].data._1 = (unsigned_1) (VAL); \
          SLOT[SLOT_NR].mask._1 = (unsigned_1) (MSK); \
          break; \
        case 2: \
          SLOT[SLOT_NR].data._2 = (unsigned_2) (VAL); \
          SLOT[SLOT_NR].mask._2 = (unsigned_2) (MSK); \
          break; \
        case 4: \
          SLOT[SLOT_NR].data._4 = (unsigned_4) (VAL); \
          SLOT[SLOT_NR].mask._4 = (unsigned_4) (MSK); \
          break; \
        case 8: \
          SLOT[SLOT_NR].data._8 = (unsigned_8) (VAL); \
          SLOT[SLOT_NR].mask._8 = (unsigned_8) (MSK); \
          break; \
        } \
      SLOT_NR = (SLOT_NR + 1); \
    } \
  while (0)
#define SLOT_PEND(DEST, VAL) SLOT_PEND_MASK(DEST, 0, VAL)
#define SLOT_DISCARD() (SLOT_NR = 0)
#define SLOT_FLUSH() \
  do \
    { \
      int i; \
      for (i = 0; i < SLOT_NR; i++) \
	{ \
	  switch (SLOT[i].size) \
	    { \
	    case 1: \
	      *(unsigned_1*) SLOT[i].dest &= SLOT[i].mask._1; \
	      *(unsigned_1*) SLOT[i].dest |= SLOT[i].data._1; \
	      break; \
	    case 2: \
	      *(unsigned_2*) SLOT[i].dest &= SLOT[i].mask._2; \
	      *(unsigned_2*) SLOT[i].dest |= SLOT[i].data._2; \
	      break; \
	    case 4: \
	      *(unsigned_4*) SLOT[i].dest &= SLOT[i].mask._4; \
	      *(unsigned_4*) SLOT[i].dest |= SLOT[i].data._4; \
	      break; \
	    case 8: \
	      *(unsigned_8*) SLOT[i].dest &= SLOT[i].mask._8; \
	      *(unsigned_8*) SLOT[i].dest |= SLOT[i].data._8; \
	      break; \
	    } \
        } \
      SLOT_NR = 0; \
    } \
  while (0)
#define SLOT_DUMP() \
  do \
    { \
      int i; \
      for (i = 0; i < SLOT_NR; i++) \
	{ \
	  switch (SLOT[i].size) \
	    { \
	    case 1: \
              printf ("SLOT %d *0x%08lx & 0x%02x | 0x%02x\n", i, \
		      (long) SLOT[i].dest, \
                      (unsigned) SLOT[i].mask._1, \
                      (unsigned) SLOT[i].data._1); \
	      break; \
	    case 2: \
              printf ("SLOT %d *0x%08lx & 0x%04x | 0x%04x\n", i, \
		      (long) SLOT[i].dest, \
                      (unsigned) SLOT[i].mask._2, \
                      (unsigned) SLOT[i].data._2); \
	      break; \
	    case 4: \
              printf ("SLOT %d *0x%08lx & 0x%08x | 0x%08x\n", i, \
		      (long) SLOT[i].dest, \
                      (unsigned) SLOT[i].mask._4, \
                      (unsigned) SLOT[i].data._4); \
	      break; \
	    case 8: \
              printf ("SLOT %d *0x%08lx & 0x%08x%08x | 0x%08x%08x\n", i, \
		      (long) SLOT[i].dest, \
                      (unsigned) (SLOT[i].mask._8 >> 32),  \
                      (unsigned) SLOT[i].mask._8, \
                      (unsigned) (SLOT[i].data._8 >> 32),  \
                      (unsigned) SLOT[i].data._8); \
	      break; \
	    } \
        } \
    } \
  while (0)

struct _state
{
  reg_t regs[16];		/* general-purpose registers */
#define GPR(N) (State.regs[(N)] + 0)
#define SET_GPR(N,VAL) SLOT_PEND (State.regs[(N)], (VAL))

#define GPR32(N) ((((uint32) State.regs[(N) + 0]) << 16) \
		  | (uint16) State.regs[(N) + 1])
#define SET_GPR32(N,VAL) do { SET_GPR (OP[0] + 0, (VAL) >> 16); SET_GPR (OP[0] + 1, (VAL)); } while (0)

  reg_t cregs[16];		/* control registers */
#define CREG(N) (State.cregs[(N)] + 0)
#define SET_CREG(N,VAL) move_to_cr ((N), 0, (VAL))

  reg_t sp[2];                  /* holding area for SPI(0)/SPU(1) */
#define HELD_SP(N) (State.sp[(N)] + 0)
#define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL))

  int64 a[2];			/* accumulators */
#define ACC(N) (State.a[(N)] + 0)
#define SET_ACC(N,VAL) SLOT_PEND (State.a[(N)], (VAL) & MASK40)

  /* writeback info */
  struct slot slot[NR_SLOTS];
  int slot_nr;

  /* trace data */
  struct {
    uint16 psw;
  } trace;

  uint8 exe;
  int	exception;
  int	pc_changed;

  /* NOTE: everything below this line is not reset by sim_create_inferior() */
  uint8 *imem;
  uint8 *dmem;
  uint8 *umem[128];
  enum _ins_type ins_type;

} State;


extern host_callback *d10v_callback;
extern uint16 OP[4];
extern struct simops Simops[];
extern asection *text;
extern bfd_vma text_start;
extern bfd_vma text_end;
extern bfd *prog_bfd;

enum
{
  PSW_CR = 0,
  BPSW_CR = 1,
  PC_CR = 2,
  BPC_CR = 3,
  DPSW_CR = 4,
  DPC_CR = 5,
  RPT_C_CR = 7,
  RPT_S_CR = 8,
  RPT_E_CR = 9,
  MOD_S_CR = 10,
  MOD_E_CR = 11,
  IBA_CR = 14,
};

enum
{
  PSW_SM_BIT = 0x8000,
  PSW_EA_BIT = 0x2000,
  PSW_DB_BIT = 0x1000,
  PSW_DM_BIT = 0x0800,
  PSW_IE_BIT = 0x0400,
  PSW_RP_BIT = 0x0200,
  PSW_MD_BIT = 0x0100,
  PSW_FX_BIT = 0x0080,
  PSW_ST_BIT = 0x0040,
  PSW_F0_BIT = 0x0008,
  PSW_F1_BIT = 0x0004,
  PSW_C_BIT =  0x0001,
};

#define PSW CREG (PSW_CR)
#define SET_PSW(VAL) SET_CREG (PSW_CR, (VAL))
#define SET_PSW_BIT(MASK,VAL) move_to_cr (PSW_CR, ~(MASK), (VAL) ? (MASK) : 0)

#define PSW_SM ((PSW & PSW_SM_BIT) != 0)
#define SET_PSW_SM(VAL) SET_PSW_BIT (PSW_SM_BIT, (VAL))

#define PSW_EA ((PSW & PSW_EA_BIT) != 0)
#define SET_PSW_EA(VAL) SET_PSW_BIT (PSW_EA_BIT, (VAL))

#define PSW_DB ((PSW & PSW_DB_BIT) != 0)
#define SET_PSW_DB(VAL) SET_PSW_BIT (PSW_DB_BIT, (VAL))

#define PSW_DM ((PSW & PSW_DM_BIT) != 0)
#define SET_PSW_DM(VAL) SET_PSW_BIT (PSW_DM_BIT, (VAL))

#define PSW_IE ((PSW & PSW_IE_BIT) != 0)
#define SET_PSW_IE(VAL) SET_PSW_BIT (PSW_IE_BIT, (VAL))

#define PSW_RP ((PSW & PSW_RP_BIT) != 0)
#define SET_PSW_RP(VAL) SET_PSW_BIT (PSW_RP_BIT, (VAL))

#define PSW_MD ((PSW & PSW_MD_BIT) != 0)
#define SET_PSW_MD(VAL) SET_PSW_BIT (PSW_MD_BIT, (VAL))

#define PSW_FX ((PSW & PSW_FX_BIT) != 0)
#define SET_PSW_FX(VAL) SET_PSW_BIT (PSW_FX_BIT, (VAL))

#define PSW_ST ((PSW & PSW_ST_BIT) != 0)
#define SET_PSW_ST(VAL) SET_PSW_BIT (PSW_ST_BIT, (VAL))

#define PSW_F0 ((PSW & PSW_F0_BIT) != 0)
#define SET_PSW_F0(VAL) SET_PSW_BIT (PSW_F0_BIT, (VAL))

#define PSW_F1 ((PSW & PSW_F1_BIT) != 0)
#define SET_PSW_F1(VAL) SET_PSW_BIT (PSW_F1_BIT, (VAL))

#define PSW_C ((PSW & PSW_C_BIT) != 0)
#define SET_PSW_C(VAL) SET_PSW_BIT (PSW_C_BIT, (VAL))

/* See simopsc.:move_to_cr() for registers that can not be read-from
   or assigned-to directly */

#define PC	CREG (PC_CR)
#define SET_PC(VAL) SET_CREG (PC_CR, (VAL))

#define BPSW	CREG (BPSW_CR)
#define SET_BPSW(VAL) SET_CREG (BPSW_CR, (VAL))

#define BPC	CREG (BPC_CR)
#define SET_BPC(VAL) SET_CREG (BPC_CR, (VAL))

#define DPSW	CREG (DPSW_CR)
#define SET_DPSW(VAL) SET_CREG (DPSW_CR, (VAL))

#define DPC	CREG (DPC_CR)
#define SET_DPC(VAL) SET_CREG (DPC_CR, (VAL))

#define RPT_C	CREG (RPT_C_CR)
#define SET_RPT_C(VAL) SET_CREG (RPT_C_CR, (VAL))

#define RPT_S	CREG (RPT_S_CR)
#define SET_RPT_S(VAL) SET_CREG (RPT_S_CR, (VAL))

#define RPT_E	CREG (RPT_E_CR)
#define SET_RPT_E(VAL) SET_CREG (RPT_E_CR, (VAL))

#define MOD_S	CREG (MOD_S_CR)
#define SET_MOD_S(VAL) SET_CREG (MOD_S_CR, (VAL))

#define MOD_E	CREG (MOD_E_CR)
#define SET_MOD_E(VAL) SET_CREG (MOD_E_CR, (VAL))

#define IBA	CREG (IBA_CR)
#define SET_IBA(VAL) SET_CREG (IBA_CR, (VAL))


#define SIG_D10V_STOP	-1
#define SIG_D10V_EXIT	-2

#define SEXT3(x)	((((x)&0x7)^(~3))+4)	

/* sign-extend a 4-bit number */
#define SEXT4(x)	((((x)&0xf)^(~7))+8)	

/* sign-extend an 8-bit number */
#define SEXT8(x)	((((x)&0xff)^(~0x7f))+0x80)

/* sign-extend a 16-bit number */
#define SEXT16(x)	((((x)&0xffff)^(~0x7fff))+0x8000)

/* sign-extend a 32-bit number */
#define SEXT32(x)	((((x)&SIGNED64(0xffffffff))^(~SIGNED64(0x7fffffff)))+SIGNED64(0x80000000))

/* sign extend a 40 bit number */
#define SEXT40(x)	((((x)&SIGNED64(0xffffffffff))^(~SIGNED64(0x7fffffffff)))+SIGNED64(0x8000000000))

/* sign extend a 44 bit number */
#define SEXT44(x)	((((x)&SIGNED64(0xfffffffffff))^(~SIGNED64(0x7ffffffffff)))+SIGNED64(0x80000000000))

/* sign extend a 56 bit number */
#define SEXT56(x)	((((x)&SIGNED64(0xffffffffffffff))^(~SIGNED64(0x7fffffffffffff)))+SIGNED64(0x80000000000000))

/* sign extend a 60 bit number */
#define SEXT60(x)	((((x)&SIGNED64(0xfffffffffffffff))^(~SIGNED64(0x7ffffffffffffff)))+SIGNED64(0x800000000000000))

#define MAX32	SIGNED64(0x7fffffff)
#define MIN32	SIGNED64(0xff80000000)
#define MASK32	SIGNED64(0xffffffff)
#define MASK40	SIGNED64(0xffffffffff)

/* The alignment of MOD_E in the following macro depends upon "i"
   always being a power of 2. */
#define INC_ADDR(x,i) \
do \
  { \
    if (PSW_MD && GPR (x) == (MOD_E & ~((i) - 1))) \
      SET_GPR (x, MOD_S); \
    else \
      SET_GPR (x, GPR (x) + (i)); \
  } \
while (0)

extern uint8 *dmem_addr PARAMS ((uint32));
extern uint8 *imem_addr PARAMS ((uint32));
extern bfd_vma decode_pc PARAMS ((void));

#define	RB(x)	(*(dmem_addr(x)))
#define SB(addr,data)	( RB(addr) = (data & 0xff))

#if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE)
#define ENDIAN_INLINE static __inline__
#include "endian.c"
#undef ENDIAN_INLINE

#else
extern uint32 get_longword PARAMS ((uint8 *));
extern uint16 get_word PARAMS ((uint8 *));
extern int64 get_longlong PARAMS ((uint8 *));
extern void write_word PARAMS ((uint8 *addr, uint16 data));
extern void write_longword PARAMS ((uint8 *addr, uint32 data));
extern void write_longlong PARAMS ((uint8 *addr, int64 data));
#endif

#define SW(addr,data)		write_word(dmem_addr(addr),data)
#define RW(x)			get_word(dmem_addr(x))
#define SLW(addr,data)  	write_longword(dmem_addr(addr),data)
#define RLW(x)			get_longword(dmem_addr(x))
#define READ_16(x)		get_word(x)
#define WRITE_16(addr,data)	write_word(addr,data)
#define READ_64(x)		get_longlong(x)
#define WRITE_64(addr,data)	write_longlong(addr,data)

#define IMAP0			RW(0xff00)
#define IMAP1			RW(0xff02)
#define DMAP			RW(0xff04)
#define SET_IMAP0(x)		SW(0xff00,x)
#define SET_IMAP1(x)		SW(0xff02,x)
#define SET_DMAP(x)		SW(0xff04,x)

#define JMP(x)			do { SET_PC (x); State.pc_changed = 1; } while (0)

#define RIE_VECTOR_START 0xffc2
#define AE_VECTOR_START 0xffc3
#define TRAP_VECTOR_START 0xffc4	/* vector for trap 0 */
#define DBT_VECTOR_START 0xffd4
#define SDBT_VECTOR_START 0xffd5

extern reg_t move_to_cr PARAMS ((int cr, reg_t mask, reg_t val));
Commit	Line	Data
c906108c SS	1	#include "config.h"
	2	#include <stdio.h>
	3	#include <ctype.h>
	4	#include <limits.h>
	5	#include "ansidecl.h"
	6	#include "callback.h"
	7	#include "opcode/d10v.h"
	8	#include "bfd.h"
	9
	10	#define DEBUG_TRACE 0x00000001
	11	#define DEBUG_VALUES 0x00000002
	12	#define DEBUG_LINE_NUMBER 0x00000004
	13	#define DEBUG_MEMSIZE 0x00000008
	14	#define DEBUG_INSTRUCTION 0x00000010
	15	#define DEBUG_TRAP 0x00000020
	16
	17	#ifndef DEBUG
	18	#define DEBUG (DEBUG_TRACE \| DEBUG_VALUES \| DEBUG_LINE_NUMBER)
	19	#endif
	20
	21	extern int d10v_debug;
	22
	23	#include "remote-sim.h"
	24	#include "sim-config.h"
	25	#include "sim-types.h"
	26
	27	typedef unsigned8 uint8;
	28	typedef unsigned16 uint16;
	29	typedef signed16 int16;
	30	typedef unsigned32 uint32;
	31	typedef signed32 int32;
	32	typedef unsigned64 uint64;
	33	typedef signed64 int64;
	34
	35	/* FIXME: D10V defines */
	36	typedef uint16 reg_t;
	37
	38	struct simops
	39	{
	40	long opcode;
	41	int is_long;
	42	long mask;
	43	int format;
	44	int cycles;
	45	int unit;
	46	int exec_type;
	47	void (*func)();
	48	int numops;
	49	int operands[9];
	50	};
	51
	52	enum _ins_type
	53	{
	54	INS_UNKNOWN, /* unknown instruction */
	55	INS_COND_TRUE, /* # times EXExxx executed other instruction */
	56	INS_COND_FALSE, /* # times EXExxx did not execute other instruction */
	57	INS_COND_JUMP, /* # times JUMP skipped other instruction */
	58	INS_CYCLES, /* # cycles */
	59	INS_LONG, /* long instruction (both containers, ie FM == 11) */
	60	INS_LEFTRIGHT, /* # times instruction encoded as L -> R (ie, FM == 01) */
	61	INS_RIGHTLEFT, /* # times instruction encoded as L <- R (ie, FM == 10) */
	62	INS_PARALLEL, /* # times instruction encoded as L \|\| R (ie, RM == 00) */
	63
	64	INS_LEFT, /* normal left instructions */
65	INS_LEFT_PARALLEL, /* left side of \|\| */
66	INS_LEFT_COND_TEST, /* EXExx test on left side */
67	INS_LEFT_COND_EXE, /* execution after EXExxx test on right side succeeded */
68	INS_LEFT_NOPS, /* NOP on left side */
69
70	INS_RIGHT, /* normal right instructions */
71	INS_RIGHT_PARALLEL, /* right side of \|\| */
72	INS_RIGHT_COND_TEST, /* EXExx test on right side */
73	INS_RIGHT_COND_EXE, /* execution after EXExxx test on left side succeeded */
74	INS_RIGHT_NOPS, /* NOP on right side */
75
76	INS_MAX
77	};
78
79	extern unsigned long ins_type_counters[ (int)INS_MAX ];
80
81	enum {
82	SP_IDX = 15,
83	};
84
85	/* Write-back slots */
86	union slot_data {
87	unsigned_1 _1;
88	unsigned_2 _2;
89	unsigned_4 _4;
90	unsigned_8 _8;
91	};
92	struct slot {
93	void *dest;
94	int size;
95	union slot_data data;
96	union slot_data mask;
97	};
98	enum {
99	NR_SLOTS = 16,
100	};
101	#define SLOT (State.slot)
102	#define SLOT_NR (State.slot_nr)
103	#define SLOT_PEND_MASK(DEST, MSK, VAL) \
104	do \
105	{ \
106	SLOT[SLOT_NR].dest = &(DEST); \
107	SLOT[SLOT_NR].size = sizeof (DEST); \
108	switch (sizeof (DEST)) \
109	{ \
110	case 1: \
111	SLOT[SLOT_NR].data._1 = (unsigned_1) (VAL); \
112	SLOT[SLOT_NR].mask._1 = (unsigned_1) (MSK); \
113	break; \
114	case 2: \
115	SLOT[SLOT_NR].data._2 = (unsigned_2) (VAL); \
116	SLOT[SLOT_NR].mask._2 = (unsigned_2) (MSK); \
117	break; \
118	case 4: \
119	SLOT[SLOT_NR].data._4 = (unsigned_4) (VAL); \
120	SLOT[SLOT_NR].mask._4 = (unsigned_4) (MSK); \
121	break; \
122	case 8: \
123	SLOT[SLOT_NR].data._8 = (unsigned_8) (VAL); \
124	SLOT[SLOT_NR].mask._8 = (unsigned_8) (MSK); \
125	break; \
126	} \
127	SLOT_NR = (SLOT_NR + 1); \
128	} \
129	while (0)
130	#define SLOT_PEND(DEST, VAL) SLOT_PEND_MASK(DEST, 0, VAL)
131	#define SLOT_DISCARD() (SLOT_NR = 0)
132	#define SLOT_FLUSH() \
133	do \
134	{ \
135	int i; \
136	for (i = 0; i < SLOT_NR; i++) \
137	{ \
138	switch (SLOT[i].size) \
139	{ \
140	case 1: \
141	(unsigned_1) SLOT[i].dest &= SLOT[i].mask._1; \
142	(unsigned_1) SLOT[i].dest \|= SLOT[i].data._1; \
143	break; \
144	case 2: \
145	(unsigned_2) SLOT[i].dest &= SLOT[i].mask._2; \
146	(unsigned_2) SLOT[i].dest \|= SLOT[i].data._2; \
147	break; \
148	case 4: \
149	(unsigned_4) SLOT[i].dest &= SLOT[i].mask._4; \
150	(unsigned_4) SLOT[i].dest \|= SLOT[i].data._4; \
151	break; \
152	case 8: \
153	(unsigned_8) SLOT[i].dest &= SLOT[i].mask._8; \
154	(unsigned_8) SLOT[i].dest \|= SLOT[i].data._8; \
155	break; \
156	} \
157	} \
158	SLOT_NR = 0; \
159	} \
160	while (0)
161	#define SLOT_DUMP() \
162	do \
163	{ \
164	int i; \
165	for (i = 0; i < SLOT_NR; i++) \
166	{ \
167	switch (SLOT[i].size) \
168	{ \
169	case 1: \
170	printf ("SLOT %d *0x%08lx & 0x%02x \| 0x%02x\n", i, \
171	(long) SLOT[i].dest, \
172	(unsigned) SLOT[i].mask._1, \
173	(unsigned) SLOT[i].data._1); \
174	break; \
175	case 2: \
176	printf ("SLOT %d *0x%08lx & 0x%04x \| 0x%04x\n", i, \
177	(long) SLOT[i].dest, \
178	(unsigned) SLOT[i].mask._2, \
179	(unsigned) SLOT[i].data._2); \
180	break; \
181	case 4: \
182	printf ("SLOT %d *0x%08lx & 0x%08x \| 0x%08x\n", i, \
183	(long) SLOT[i].dest, \
184	(unsigned) SLOT[i].mask._4, \
185	(unsigned) SLOT[i].data._4); \
186	break; \
187	case 8: \
188	printf ("SLOT %d *0x%08lx & 0x%08x%08x \| 0x%08x%08x\n", i, \
189	(long) SLOT[i].dest, \
190	(unsigned) (SLOT[i].mask._8 >> 32), \
191	(unsigned) SLOT[i].mask._8, \
192	(unsigned) (SLOT[i].data._8 >> 32), \
193	(unsigned) SLOT[i].data._8); \
194	break; \
195	} \
196	} \
197	} \
198	while (0)
199
200	struct _state
201	{
202	reg_t regs[16]; /* general-purpose registers */
203	#define GPR(N) (State.regs[(N)] + 0)
204	#define SET_GPR(N,VAL) SLOT_PEND (State.regs[(N)], (VAL))
205
206	#define GPR32(N) ((((uint32) State.regs[(N) + 0]) << 16) \
207	\| (uint16) State.regs[(N) + 1])
208	#define SET_GPR32(N,VAL) do { SET_GPR (OP[0] + 0, (VAL) >> 16); SET_GPR (OP[0] + 1, (VAL)); } while (0)
209
210	reg_t cregs[16]; /* control registers */
211	#define CREG(N) (State.cregs[(N)] + 0)
212	#define SET_CREG(N,VAL) move_to_cr ((N), 0, (VAL))
213
214	reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */
215	#define HELD_SP(N) (State.sp[(N)] + 0)
216	#define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL))
217
218	int64 a[2]; /* accumulators */
219	#define ACC(N) (State.a[(N)] + 0)
220	#define SET_ACC(N,VAL) SLOT_PEND (State.a[(N)], (VAL) & MASK40)
221
222	/* writeback info */
223	struct slot slot[NR_SLOTS];
224	int slot_nr;
225
226	/* trace data */
227	struct {
228	uint16 psw;
229	} trace;
230
231	uint8 exe;
232	int exception;
233	int pc_changed;
234
235	/* NOTE: everything below this line is not reset by sim_create_inferior() */
236	uint8 *imem;
237	uint8 *dmem;
238	uint8 *umem[128];
239	enum _ins_type ins_type;
240
241	} State;
242
243
244	extern host_callback *d10v_callback;
245	extern uint16 OP[4];
246	extern struct simops Simops[];
247	extern asection *text;
248	extern bfd_vma text_start;
249	extern bfd_vma text_end;
250	extern bfd *prog_bfd;
251
252	enum
253	{
254	PSW_CR = 0,
255	BPSW_CR = 1,
256	PC_CR = 2,
257	BPC_CR = 3,
258	DPSW_CR = 4,
259	DPC_CR = 5,
260	RPT_C_CR = 7,
261	RPT_S_CR = 8,
262	RPT_E_CR = 9,
263	MOD_S_CR = 10,
264	MOD_E_CR = 11,
265	IBA_CR = 14,
266	};
267
268	enum
269	{
270	PSW_SM_BIT = 0x8000,
271	PSW_EA_BIT = 0x2000,
272	PSW_DB_BIT = 0x1000,
273	PSW_DM_BIT = 0x0800,
274	PSW_IE_BIT = 0x0400,
275	PSW_RP_BIT = 0x0200,
276	PSW_MD_BIT = 0x0100,
277	PSW_FX_BIT = 0x0080,
278	PSW_ST_BIT = 0x0040,
279	PSW_F0_BIT = 0x0008,
280	PSW_F1_BIT = 0x0004,
281	PSW_C_BIT = 0x0001,
282	};
283
284	#define PSW CREG (PSW_CR)
285	#define SET_PSW(VAL) SET_CREG (PSW_CR, (VAL))
286	#define SET_PSW_BIT(MASK,VAL) move_to_cr (PSW_CR, ~(MASK), (VAL) ? (MASK) : 0)
287
288	#define PSW_SM ((PSW & PSW_SM_BIT) != 0)
289	#define SET_PSW_SM(VAL) SET_PSW_BIT (PSW_SM_BIT, (VAL))
290
291	#define PSW_EA ((PSW & PSW_EA_BIT) != 0)
292	#define SET_PSW_EA(VAL) SET_PSW_BIT (PSW_EA_BIT, (VAL))
293
294	#define PSW_DB ((PSW & PSW_DB_BIT) != 0)
295	#define SET_PSW_DB(VAL) SET_PSW_BIT (PSW_DB_BIT, (VAL))
296
297	#define PSW_DM ((PSW & PSW_DM_BIT) != 0)
298	#define SET_PSW_DM(VAL) SET_PSW_BIT (PSW_DM_BIT, (VAL))
299
300	#define PSW_IE ((PSW & PSW_IE_BIT) != 0)
301	#define SET_PSW_IE(VAL) SET_PSW_BIT (PSW_IE_BIT, (VAL))
302
303	#define PSW_RP ((PSW & PSW_RP_BIT) != 0)
304	#define SET_PSW_RP(VAL) SET_PSW_BIT (PSW_RP_BIT, (VAL))
305
306	#define PSW_MD ((PSW & PSW_MD_BIT) != 0)
307	#define SET_PSW_MD(VAL) SET_PSW_BIT (PSW_MD_BIT, (VAL))
308
309	#define PSW_FX ((PSW & PSW_FX_BIT) != 0)
310	#define SET_PSW_FX(VAL) SET_PSW_BIT (PSW_FX_BIT, (VAL))
311
312	#define PSW_ST ((PSW & PSW_ST_BIT) != 0)
313	#define SET_PSW_ST(VAL) SET_PSW_BIT (PSW_ST_BIT, (VAL))
314
315	#define PSW_F0 ((PSW & PSW_F0_BIT) != 0)
316	#define SET_PSW_F0(VAL) SET_PSW_BIT (PSW_F0_BIT, (VAL))
317
318	#define PSW_F1 ((PSW & PSW_F1_BIT) != 0)
319	#define SET_PSW_F1(VAL) SET_PSW_BIT (PSW_F1_BIT, (VAL))
320
321	#define PSW_C ((PSW & PSW_C_BIT) != 0)
322	#define SET_PSW_C(VAL) SET_PSW_BIT (PSW_C_BIT, (VAL))
323
324	/* See simopsc.:move_to_cr() for registers that can not be read-from
325	or assigned-to directly */
326
327	#define PC CREG (PC_CR)
328	#define SET_PC(VAL) SET_CREG (PC_CR, (VAL))
329
330	#define BPSW CREG (BPSW_CR)
331	#define SET_BPSW(VAL) SET_CREG (BPSW_CR, (VAL))
332
333	#define BPC CREG (BPC_CR)
334	#define SET_BPC(VAL) SET_CREG (BPC_CR, (VAL))
335
336	#define DPSW CREG (DPSW_CR)
337	#define SET_DPSW(VAL) SET_CREG (DPSW_CR, (VAL))
338
339	#define DPC CREG (DPC_CR)
340	#define SET_DPC(VAL) SET_CREG (DPC_CR, (VAL))
341
342	#define RPT_C CREG (RPT_C_CR)
343	#define SET_RPT_C(VAL) SET_CREG (RPT_C_CR, (VAL))
344
345	#define RPT_S CREG (RPT_S_CR)
346	#define SET_RPT_S(VAL) SET_CREG (RPT_S_CR, (VAL))
347
348	#define RPT_E CREG (RPT_E_CR)
349	#define SET_RPT_E(VAL) SET_CREG (RPT_E_CR, (VAL))
350
351	#define MOD_S CREG (MOD_S_CR)
352	#define SET_MOD_S(VAL) SET_CREG (MOD_S_CR, (VAL))
353
354	#define MOD_E CREG (MOD_E_CR)
355	#define SET_MOD_E(VAL) SET_CREG (MOD_E_CR, (VAL))
356
357	#define IBA CREG (IBA_CR)
358	#define SET_IBA(VAL) SET_CREG (IBA_CR, (VAL))
359
360
361	#define SIG_D10V_STOP -1
362	#define SIG_D10V_EXIT -2
363
364	#define SEXT3(x) ((((x)&0x7)^(~3))+4)
365
366	/* sign-extend a 4-bit number */
367	#define SEXT4(x) ((((x)&0xf)^(~7))+8)
368
369	/* sign-extend an 8-bit number */
370	#define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
371
372	/* sign-extend a 16-bit number */
373	#define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
374
375	/* sign-extend a 32-bit number */
376	#define SEXT32(x) ((((x)&SIGNED64(0xffffffff))^(~SIGNED64(0x7fffffff)))+SIGNED64(0x80000000))
377
378	/* sign extend a 40 bit number */
379	#define SEXT40(x) ((((x)&SIGNED64(0xffffffffff))^(~SIGNED64(0x7fffffffff)))+SIGNED64(0x8000000000))
380
381	/* sign extend a 44 bit number */
382	#define SEXT44(x) ((((x)&SIGNED64(0xfffffffffff))^(~SIGNED64(0x7ffffffffff)))+SIGNED64(0x80000000000))
383
384	/* sign extend a 56 bit number */
385	#define SEXT56(x) ((((x)&SIGNED64(0xffffffffffffff))^(~SIGNED64(0x7fffffffffffff)))+SIGNED64(0x80000000000000))
386
387	/* sign extend a 60 bit number */
388	#define SEXT60(x) ((((x)&SIGNED64(0xfffffffffffffff))^(~SIGNED64(0x7ffffffffffffff)))+SIGNED64(0x800000000000000))
389
390	#define MAX32 SIGNED64(0x7fffffff)
391	#define MIN32 SIGNED64(0xff80000000)
392	#define MASK32 SIGNED64(0xffffffff)
393	#define MASK40 SIGNED64(0xffffffffff)
394
395	/* The alignment of MOD_E in the following macro depends upon "i"
396	always being a power of 2. */
397	#define INC_ADDR(x,i) \
398	do \
399	{ \
400	if (PSW_MD && GPR (x) == (MOD_E & ~((i) - 1))) \
401	SET_GPR (x, MOD_S); \
402	else \
403	SET_GPR (x, GPR (x) + (i)); \
404	} \
405	while (0)
406
407	extern uint8 *dmem_addr PARAMS ((uint32));
408	extern uint8 *imem_addr PARAMS ((uint32));
409	extern bfd_vma decode_pc PARAMS ((void));
410
411	#define RB(x) (*(dmem_addr(x)))
412	#define SB(addr,data) ( RB(addr) = (data & 0xff))
413
414	#if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE)
415	#define ENDIAN_INLINE static __inline__
416	#include "endian.c"
417	#undef ENDIAN_INLINE
418
419	#else
420	extern uint32 get_longword PARAMS ((uint8 *));
421	extern uint16 get_word PARAMS ((uint8 *));
422	extern int64 get_longlong PARAMS ((uint8 *));
423	extern void write_word PARAMS ((uint8 *addr, uint16 data));
424	extern void write_longword PARAMS ((uint8 *addr, uint32 data));
425	extern void write_longlong PARAMS ((uint8 *addr, int64 data));
426	#endif
427
428	#define SW(addr,data) write_word(dmem_addr(addr),data)
429	#define RW(x) get_word(dmem_addr(x))
430	#define SLW(addr,data) write_longword(dmem_addr(addr),data)
431	#define RLW(x) get_longword(dmem_addr(x))
432	#define READ_16(x) get_word(x)
433	#define WRITE_16(addr,data) write_word(addr,data)
434	#define READ_64(x) get_longlong(x)
435	#define WRITE_64(addr,data) write_longlong(addr,data)
436
437	#define IMAP0 RW(0xff00)
438	#define IMAP1 RW(0xff02)
439	#define DMAP RW(0xff04)
440	#define SET_IMAP0(x) SW(0xff00,x)
441	#define SET_IMAP1(x) SW(0xff02,x)
442	#define SET_DMAP(x) SW(0xff04,x)
443
444	#define JMP(x) do { SET_PC (x); State.pc_changed = 1; } while (0)
445
446	#define RIE_VECTOR_START 0xffc2
447	#define AE_VECTOR_START 0xffc3
448	#define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */
449	#define DBT_VECTOR_START 0xffd4
450	#define SDBT_VECTOR_START 0xffd5
451
452	extern reg_t move_to_cr PARAMS ((int cr, reg_t mask, reg_t val));