Commit | Line | Data |
---|---|---|
d70b4d42 | 1 | #include <signal.h> |
2934d1c9 | 2 | #include "sysdep.h" |
04885cc3 | 3 | #include "bfd.h" |
cee402dd | 4 | #include "callback.h" |
2934d1c9 | 5 | #include "remote-sim.h" |
2934d1c9 MH |
6 | |
7 | #include "d10v_sim.h" | |
8 | ||
9 | #define IMEM_SIZE 18 /* D10V instruction memory size is 18 bits */ | |
c422ecc7 MH |
10 | #define DMEM_SIZE 16 /* Data memory is 64K (but only 32K internal RAM) */ |
11 | #define UMEM_SIZE 17 /* each unified memory region is 17 bits */ | |
2934d1c9 | 12 | |
87178dbd MM |
13 | enum _leftright { LEFT_FIRST, RIGHT_FIRST }; |
14 | ||
04885cc3 DE |
15 | static char *myname; |
16 | static SIM_OPEN_KIND sim_kind; | |
7eebfc62 | 17 | int d10v_debug; |
87178dbd | 18 | host_callback *d10v_callback; |
aeb1f26b | 19 | unsigned long ins_type_counters[ (int)INS_MAX ]; |
87178dbd | 20 | |
2934d1c9 MH |
21 | uint16 OP[4]; |
22 | ||
b30cdd35 | 23 | static int init_text_p = 0; |
04885cc3 DE |
24 | /* non-zero if we opened prog_bfd */ |
25 | static int prog_bfd_was_opened_p; | |
26 | bfd *prog_bfd; | |
b30cdd35 MM |
27 | asection *text; |
28 | bfd_vma text_start; | |
29 | bfd_vma text_end; | |
30 | ||
aeb1f26b | 31 | static long hash PARAMS ((long insn, int format)); |
2934d1c9 | 32 | static struct hash_entry *lookup_hash PARAMS ((uint32 ins, int size)); |
aeb1f26b MM |
33 | static void get_operands PARAMS ((struct simops *s, uint32 ins)); |
34 | static void do_long PARAMS ((uint32 ins)); | |
35 | static void do_2_short PARAMS ((uint16 ins1, uint16 ins2, enum _leftright leftright)); | |
36 | static void do_parallel PARAMS ((uint16 ins1, uint16 ins2)); | |
37 | static char *add_commas PARAMS ((char *buf, int sizeof_buf, unsigned long value)); | |
aeb1f26b | 38 | static void init_system PARAMS ((void)); |
aeb1f26b MM |
39 | extern void sim_set_profile PARAMS ((int n)); |
40 | extern void sim_set_profile_size PARAMS ((int n)); | |
aeb1f26b MM |
41 | |
42 | #ifndef INLINE | |
43 | #if defined(__GNUC__) && defined(__OPTIMIZE__) | |
44 | #define INLINE __inline__ | |
45 | #else | |
46 | #define INLINE | |
47 | #endif | |
48 | #endif | |
2934d1c9 MH |
49 | |
50 | #define MAX_HASH 63 | |
51 | struct hash_entry | |
52 | { | |
53 | struct hash_entry *next; | |
54 | long opcode; | |
55 | long mask; | |
cee402dd | 56 | int size; |
2934d1c9 MH |
57 | struct simops *ops; |
58 | }; | |
59 | ||
60 | struct hash_entry hash_table[MAX_HASH+1]; | |
61 | ||
aeb1f26b | 62 | INLINE static long |
2934d1c9 MH |
63 | hash(insn, format) |
64 | long insn; | |
65 | int format; | |
66 | { | |
67 | if (format & LONG_OPCODE) | |
68 | return ((insn & 0x3F000000) >> 24); | |
69 | else | |
70 | return((insn & 0x7E00) >> 9); | |
71 | } | |
72 | ||
aeb1f26b | 73 | INLINE static struct hash_entry * |
2934d1c9 MH |
74 | lookup_hash (ins, size) |
75 | uint32 ins; | |
76 | int size; | |
77 | { | |
78 | struct hash_entry *h; | |
79 | ||
80 | if (size) | |
81 | h = &hash_table[(ins & 0x3F000000) >> 24]; | |
82 | else | |
83 | h = &hash_table[(ins & 0x7E00) >> 9]; | |
84 | ||
cee402dd | 85 | while ((ins & h->mask) != h->opcode || h->size != size) |
2934d1c9 MH |
86 | { |
87 | if (h->next == NULL) | |
88 | { | |
7eebfc62 | 89 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR looking up hash for %x at PC %x\n",ins, PC); |
aeb1f26b | 90 | exit (1); |
2934d1c9 MH |
91 | } |
92 | h = h->next; | |
93 | } | |
94 | return (h); | |
95 | } | |
96 | ||
aeb1f26b | 97 | INLINE static void |
2934d1c9 MH |
98 | get_operands (struct simops *s, uint32 ins) |
99 | { | |
100 | int i, shift, bits, flags; | |
101 | uint32 mask; | |
102 | for (i=0; i < s->numops; i++) | |
103 | { | |
104 | shift = s->operands[3*i]; | |
105 | bits = s->operands[3*i+1]; | |
106 | flags = s->operands[3*i+2]; | |
107 | mask = 0x7FFFFFFF >> (31 - bits); | |
108 | OP[i] = (ins >> shift) & mask; | |
109 | } | |
110 | } | |
111 | ||
b30cdd35 MM |
112 | bfd_vma |
113 | decode_pc () | |
114 | { | |
115 | asection *s; | |
116 | if (!init_text_p) | |
117 | { | |
118 | init_text_p = 1; | |
04885cc3 DE |
119 | for (s = prog_bfd->sections; s; s = s->next) |
120 | if (strcmp (bfd_get_section_name (prog_bfd, s), ".text") == 0) | |
b30cdd35 MM |
121 | { |
122 | text = s; | |
04885cc3 DE |
123 | text_start = bfd_get_section_vma (prog_bfd, s); |
124 | text_end = text_start + bfd_section_size (prog_bfd, s); | |
b30cdd35 MM |
125 | break; |
126 | } | |
127 | } | |
128 | ||
129 | return (PC << 2) + text_start; | |
130 | } | |
131 | ||
2934d1c9 MH |
132 | static void |
133 | do_long (ins) | |
134 | uint32 ins; | |
135 | { | |
136 | struct hash_entry *h; | |
7eebfc62 MM |
137 | #ifdef DEBUG |
138 | if ((d10v_debug & DEBUG_INSTRUCTION) != 0) | |
139 | (*d10v_callback->printf_filtered) (d10v_callback, "do_long 0x%x\n", ins); | |
140 | #endif | |
2934d1c9 MH |
141 | h = lookup_hash (ins, 1); |
142 | get_operands (h->ops, ins); | |
87178dbd | 143 | State.ins_type = INS_LONG; |
7eebfc62 | 144 | ins_type_counters[ (int)State.ins_type ]++; |
2934d1c9 MH |
145 | (h->ops->func)(); |
146 | } | |
215ac953 | 147 | |
2934d1c9 | 148 | static void |
87178dbd | 149 | do_2_short (ins1, ins2, leftright) |
2934d1c9 | 150 | uint16 ins1, ins2; |
87178dbd | 151 | enum _leftright leftright; |
2934d1c9 MH |
152 | { |
153 | struct hash_entry *h; | |
215ac953 | 154 | reg_t orig_pc = PC; |
c422ecc7 | 155 | enum _ins_type first, second; |
215ac953 | 156 | |
7eebfc62 MM |
157 | #ifdef DEBUG |
158 | if ((d10v_debug & DEBUG_INSTRUCTION) != 0) | |
159 | (*d10v_callback->printf_filtered) (d10v_callback, "do_2_short 0x%x (%s) -> 0x%x\n", | |
160 | ins1, (leftright) ? "left" : "right", ins2); | |
161 | #endif | |
c422ecc7 MH |
162 | |
163 | if (leftright == LEFT_FIRST) | |
164 | { | |
165 | first = INS_LEFT; | |
166 | second = INS_RIGHT; | |
167 | ins_type_counters[ (int)INS_LEFTRIGHT ]++; | |
168 | } | |
169 | else | |
170 | { | |
171 | first = INS_RIGHT; | |
172 | second = INS_LEFT; | |
173 | ins_type_counters[ (int)INS_RIGHTLEFT ]++; | |
174 | } | |
175 | ||
2934d1c9 MH |
176 | h = lookup_hash (ins1, 0); |
177 | get_operands (h->ops, ins1); | |
c422ecc7 | 178 | State.ins_type = first; |
7eebfc62 | 179 | ins_type_counters[ (int)State.ins_type ]++; |
2934d1c9 | 180 | (h->ops->func)(); |
215ac953 MM |
181 | |
182 | /* If the PC has changed (ie, a jump), don't do the second instruction */ | |
57bc1a72 | 183 | if (orig_pc == PC && !State.exception) |
215ac953 MM |
184 | { |
185 | h = lookup_hash (ins2, 0); | |
186 | get_operands (h->ops, ins2); | |
c422ecc7 | 187 | State.ins_type = second; |
215ac953 | 188 | ins_type_counters[ (int)State.ins_type ]++; |
c422ecc7 | 189 | ins_type_counters[ (int)INS_CYCLES ]++; |
215ac953 MM |
190 | (h->ops->func)(); |
191 | } | |
c422ecc7 MH |
192 | else if (orig_pc != PC && !State.exception) |
193 | ins_type_counters[ (int)INS_COND_JUMP ]++; | |
2934d1c9 | 194 | } |
215ac953 | 195 | |
2934d1c9 MH |
196 | static void |
197 | do_parallel (ins1, ins2) | |
198 | uint16 ins1, ins2; | |
199 | { | |
200 | struct hash_entry *h1, *h2; | |
7eebfc62 MM |
201 | #ifdef DEBUG |
202 | if ((d10v_debug & DEBUG_INSTRUCTION) != 0) | |
203 | (*d10v_callback->printf_filtered) (d10v_callback, "do_parallel 0x%x || 0x%x\n", ins1, ins2); | |
204 | #endif | |
c422ecc7 | 205 | ins_type_counters[ (int)INS_PARALLEL ]++; |
2934d1c9 | 206 | h1 = lookup_hash (ins1, 0); |
2934d1c9 | 207 | h2 = lookup_hash (ins2, 0); |
d70b4d42 | 208 | |
2934d1c9 MH |
209 | if (h1->ops->exec_type == PARONLY) |
210 | { | |
d70b4d42 | 211 | get_operands (h1->ops, ins1); |
aeb1f26b | 212 | State.ins_type = INS_LEFT_COND_TEST; |
7eebfc62 | 213 | ins_type_counters[ (int)State.ins_type ]++; |
2934d1c9 MH |
214 | (h1->ops->func)(); |
215 | if (State.exe) | |
d70b4d42 | 216 | { |
aeb1f26b | 217 | ins_type_counters[ (int)INS_COND_TRUE ]++; |
d70b4d42 | 218 | get_operands (h2->ops, ins2); |
aeb1f26b MM |
219 | State.ins_type = INS_RIGHT_COND_EXE; |
220 | ins_type_counters[ (int)State.ins_type ]++; | |
d70b4d42 MH |
221 | (h2->ops->func)(); |
222 | } | |
aeb1f26b MM |
223 | else |
224 | ins_type_counters[ (int)INS_COND_FALSE ]++; | |
2934d1c9 MH |
225 | } |
226 | else if (h2->ops->exec_type == PARONLY) | |
227 | { | |
d70b4d42 | 228 | get_operands (h2->ops, ins2); |
aeb1f26b | 229 | State.ins_type = INS_RIGHT_COND_TEST; |
7eebfc62 | 230 | ins_type_counters[ (int)State.ins_type ]++; |
2934d1c9 MH |
231 | (h2->ops->func)(); |
232 | if (State.exe) | |
d70b4d42 | 233 | { |
aeb1f26b | 234 | ins_type_counters[ (int)INS_COND_TRUE ]++; |
d70b4d42 | 235 | get_operands (h1->ops, ins1); |
aeb1f26b MM |
236 | State.ins_type = INS_LEFT_COND_EXE; |
237 | ins_type_counters[ (int)State.ins_type ]++; | |
d70b4d42 MH |
238 | (h1->ops->func)(); |
239 | } | |
aeb1f26b MM |
240 | else |
241 | ins_type_counters[ (int)INS_COND_FALSE ]++; | |
2934d1c9 MH |
242 | } |
243 | else | |
244 | { | |
d70b4d42 | 245 | get_operands (h1->ops, ins1); |
87178dbd | 246 | State.ins_type = INS_LEFT_PARALLEL; |
7eebfc62 | 247 | ins_type_counters[ (int)State.ins_type ]++; |
2934d1c9 | 248 | (h1->ops->func)(); |
57bc1a72 MM |
249 | if (!State.exception) |
250 | { | |
251 | get_operands (h2->ops, ins2); | |
252 | State.ins_type = INS_RIGHT_PARALLEL; | |
253 | ins_type_counters[ (int)State.ins_type ]++; | |
254 | (h2->ops->func)(); | |
255 | } | |
2934d1c9 MH |
256 | } |
257 | } | |
258 | ||
aeb1f26b MM |
259 | static char * |
260 | add_commas(buf, sizeof_buf, value) | |
261 | char *buf; | |
262 | int sizeof_buf; | |
263 | unsigned long value; | |
264 | { | |
265 | int comma = 3; | |
266 | char *endbuf = buf + sizeof_buf - 1; | |
267 | ||
268 | *--endbuf = '\0'; | |
269 | do { | |
270 | if (comma-- == 0) | |
271 | { | |
272 | *--endbuf = ','; | |
273 | comma = 2; | |
274 | } | |
275 | ||
276 | *--endbuf = (value % 10) + '0'; | |
277 | } while ((value /= 10) != 0); | |
278 | ||
279 | return endbuf; | |
280 | } | |
2934d1c9 MH |
281 | |
282 | void | |
283 | sim_size (power) | |
284 | int power; | |
285 | ||
286 | { | |
c422ecc7 MH |
287 | int i; |
288 | ||
2934d1c9 MH |
289 | if (State.imem) |
290 | { | |
c422ecc7 MH |
291 | for (i=0;i<128;i++) |
292 | { | |
293 | if (State.umem[i]) | |
294 | { | |
295 | free (State.umem[i]); | |
296 | State.umem[i] = NULL; | |
297 | } | |
298 | } | |
2934d1c9 MH |
299 | free (State.imem); |
300 | free (State.dmem); | |
301 | } | |
302 | ||
303 | State.imem = (uint8 *)calloc(1,1<<IMEM_SIZE); | |
304 | State.dmem = (uint8 *)calloc(1,1<<DMEM_SIZE); | |
c422ecc7 MH |
305 | for (i=1;i<127;i++) |
306 | State.umem[i] = NULL; | |
307 | State.umem[0] = (uint8 *)calloc(1,1<<UMEM_SIZE); | |
308 | State.umem[1] = (uint8 *)calloc(1,1<<UMEM_SIZE); | |
309 | State.umem[2] = (uint8 *)calloc(1,1<<UMEM_SIZE); | |
310 | State.umem[127] = (uint8 *)calloc(1,1<<UMEM_SIZE); | |
311 | if (!State.imem || !State.dmem || !State.umem[0] || !State.umem[1] || !State.umem[2] || !State.umem[127] ) | |
2934d1c9 | 312 | { |
7eebfc62 | 313 | (*d10v_callback->printf_filtered) (d10v_callback, "Memory allocation failed.\n"); |
2934d1c9 MH |
314 | exit(1); |
315 | } | |
c422ecc7 MH |
316 | |
317 | SET_IMAP0(0x1000); | |
318 | SET_IMAP1(0x1000); | |
319 | SET_DMAP(0); | |
57bc1a72 | 320 | |
7eebfc62 MM |
321 | #ifdef DEBUG |
322 | if ((d10v_debug & DEBUG_MEMSIZE) != 0) | |
323 | { | |
aeb1f26b MM |
324 | char buffer[20]; |
325 | (*d10v_callback->printf_filtered) (d10v_callback, | |
326 | "Allocated %s bytes instruction memory and\n", | |
327 | add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE))); | |
328 | ||
329 | (*d10v_callback->printf_filtered) (d10v_callback, " %s bytes data memory.\n", | |
330 | add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE))); | |
7eebfc62 | 331 | } |
87178dbd | 332 | #endif |
2934d1c9 MH |
333 | } |
334 | ||
335 | static void | |
336 | init_system () | |
337 | { | |
338 | if (!State.imem) | |
339 | sim_size(1); | |
340 | } | |
341 | ||
c422ecc7 MH |
342 | static int |
343 | xfer_mem (addr, buffer, size, write) | |
2934d1c9 MH |
344 | SIM_ADDR addr; |
345 | unsigned char *buffer; | |
346 | int size; | |
c422ecc7 | 347 | int write; |
2934d1c9 | 348 | { |
c422ecc7 MH |
349 | if (!State.imem) |
350 | init_system (); | |
2934d1c9 | 351 | |
57bc1a72 MM |
352 | #ifdef DEBUG |
353 | if ((d10v_debug & DEBUG_INSTRUCTION) != 0) | |
c422ecc7 MH |
354 | { |
355 | if (write) | |
356 | (*d10v_callback->printf_filtered) (d10v_callback, "sim_write %d bytes to 0x%x\n", size, addr); | |
357 | else | |
358 | (*d10v_callback->printf_filtered) (d10v_callback, "sim_read %d bytes from 0x%x\n", size, addr); | |
359 | } | |
57bc1a72 MM |
360 | #endif |
361 | ||
c422ecc7 MH |
362 | /* to access data, we use the following mapping */ |
363 | /* 0x01000000 - 0x0103ffff : instruction memory */ | |
364 | /* 0x02000000 - 0x0200ffff : data memory */ | |
04885cc3 | 365 | /* 0x00000000 - 0x00ffffff : unified memory */ |
57bc1a72 | 366 | |
04885cc3 | 367 | if ( (addr & 0x03000000) == 0) |
c422ecc7 MH |
368 | { |
369 | /* UNIFIED MEMORY */ | |
370 | int segment; | |
c422ecc7 MH |
371 | segment = addr >> UMEM_SIZE; |
372 | addr &= 0x1ffff; | |
373 | if (!State.umem[segment]) | |
04885cc3 DE |
374 | { |
375 | #ifdef DEBUG | |
376 | (*d10v_callback->printf_filtered) (d10v_callback,"Allocating %s bytes unified memory to region %d\n", | |
377 | add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)), segment); | |
378 | #endif | |
379 | State.umem[segment] = (uint8 *)calloc(1,1<<UMEM_SIZE); | |
380 | } | |
c422ecc7 MH |
381 | if (!State.umem[segment]) |
382 | { | |
383 | (*d10v_callback->printf_filtered) (d10v_callback, "Memory allocation failed.\n"); | |
384 | exit(1); | |
385 | } | |
c422ecc7 MH |
386 | /* FIXME: need to check size and read/write multiple segments if necessary */ |
387 | if (write) | |
04885cc3 | 388 | memcpy (State.umem[segment]+addr, buffer, size) ; |
c422ecc7 MH |
389 | else |
390 | memcpy (buffer, State.umem[segment]+addr, size); | |
391 | } | |
392 | else if ( (addr & 0x03000000) == 0x02000000) | |
393 | { | |
394 | /* DATA MEMORY */ | |
395 | addr &= ~0x02000000; | |
396 | if (size > (1<<(DMEM_SIZE-1))) | |
397 | { | |
398 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: data section is only %d bytes.\n",1<<(DMEM_SIZE-1)); | |
399 | exit(1); | |
400 | } | |
401 | if (write) | |
402 | memcpy (State.dmem+addr, buffer, size); | |
403 | else | |
404 | memcpy (buffer, State.dmem+addr, size); | |
405 | } | |
406 | else if ( (addr & 0x03000000) == 0x01000000) | |
407 | { | |
408 | /* INSTRUCTION MEMORY */ | |
409 | addr &= ~0x01000000; | |
410 | if (size > (1<<IMEM_SIZE)) | |
411 | { | |
412 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: inst section is only %d bytes.\n",1<<IMEM_SIZE); | |
413 | exit(1); | |
414 | } | |
415 | if (write) | |
416 | memcpy (State.imem+addr, buffer, size); | |
417 | else | |
418 | memcpy (buffer, State.imem+addr, size); | |
419 | } | |
420 | else if (write) | |
421 | { | |
422 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: address 0x%x is not in valid range\n",addr); | |
423 | (*d10v_callback->printf_filtered) (d10v_callback, "Instruction addresses start at 0x01000000\n"); | |
424 | (*d10v_callback->printf_filtered) (d10v_callback, "Data addresses start at 0x02000000\n"); | |
04885cc3 | 425 | (*d10v_callback->printf_filtered) (d10v_callback, "Unified addresses start at 0x00000000\n"); |
c422ecc7 MH |
426 | exit(1); |
427 | } | |
428 | else | |
429 | return 0; | |
57bc1a72 | 430 | |
2934d1c9 MH |
431 | return size; |
432 | } | |
433 | ||
c422ecc7 | 434 | |
9e03a68f AC |
435 | static int |
436 | sim_write_phys (sd, addr, buffer, size) | |
437 | SIM_DESC sd; | |
438 | SIM_ADDR addr; | |
439 | unsigned char *buffer; | |
440 | int size; | |
441 | { | |
442 | return xfer_mem( addr, buffer, size, 1); | |
443 | } | |
444 | ||
c422ecc7 | 445 | int |
04885cc3 DE |
446 | sim_write (sd, addr, buffer, size) |
447 | SIM_DESC sd; | |
c422ecc7 MH |
448 | SIM_ADDR addr; |
449 | unsigned char *buffer; | |
450 | int size; | |
451 | { | |
9e03a68f | 452 | /* FIXME: this should be performing a virtual transfer */ |
c422ecc7 MH |
453 | return xfer_mem( addr, buffer, size, 1); |
454 | } | |
455 | ||
456 | int | |
04885cc3 DE |
457 | sim_read (sd, addr, buffer, size) |
458 | SIM_DESC sd; | |
c422ecc7 MH |
459 | SIM_ADDR addr; |
460 | unsigned char *buffer; | |
461 | int size; | |
462 | { | |
9e03a68f | 463 | /* FIXME: this should be performing a virtual transfer */ |
c422ecc7 MH |
464 | return xfer_mem( addr, buffer, size, 0); |
465 | } | |
466 | ||
467 | ||
04885cc3 | 468 | SIM_DESC |
247fccde | 469 | sim_open (kind, callback, abfd, argv) |
04885cc3 | 470 | SIM_OPEN_KIND kind; |
247fccde AC |
471 | host_callback *callback; |
472 | struct _bfd *abfd; | |
04885cc3 | 473 | char **argv; |
2934d1c9 MH |
474 | { |
475 | struct simops *s; | |
aeb1f26b | 476 | struct hash_entry *h; |
1eaaf305 | 477 | static int init_p = 0; |
04885cc3 DE |
478 | char **p; |
479 | ||
480 | sim_kind = kind; | |
247fccde | 481 | d10v_callback = callback; |
04885cc3 | 482 | myname = argv[0]; |
1eaaf305 | 483 | |
04885cc3 | 484 | for (p = argv + 1; *p; ++p) |
1eaaf305 MM |
485 | { |
486 | #ifdef DEBUG | |
04885cc3 | 487 | if (strcmp (*p, "-t") == 0) |
1eaaf305 MM |
488 | d10v_debug = DEBUG; |
489 | else | |
490 | #endif | |
04885cc3 | 491 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unsupported option(s): %s\n",*p); |
1eaaf305 | 492 | } |
c422ecc7 | 493 | |
2934d1c9 | 494 | /* put all the opcodes in the hash table */ |
1eaaf305 | 495 | if (!init_p++) |
2934d1c9 | 496 | { |
1eaaf305 | 497 | for (s = Simops; s->func; s++) |
2934d1c9 | 498 | { |
1eaaf305 MM |
499 | h = &hash_table[hash(s->opcode,s->format)]; |
500 | ||
501 | /* go to the last entry in the chain */ | |
502 | while (h->next) | |
503 | h = h->next; | |
504 | ||
505 | if (h->ops) | |
506 | { | |
04885cc3 DE |
507 | h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry)); |
508 | if (!h->next) | |
509 | perror ("malloc failure"); | |
510 | ||
1eaaf305 MM |
511 | h = h->next; |
512 | } | |
513 | h->ops = s; | |
514 | h->mask = s->mask; | |
515 | h->opcode = s->opcode; | |
cee402dd | 516 | h->size = s->is_long; |
2934d1c9 | 517 | } |
2934d1c9 | 518 | } |
04885cc3 DE |
519 | |
520 | /* Fudge our descriptor. */ | |
521 | return (SIM_DESC) 1; | |
2934d1c9 MH |
522 | } |
523 | ||
524 | ||
525 | void | |
04885cc3 DE |
526 | sim_close (sd, quitting) |
527 | SIM_DESC sd; | |
2934d1c9 MH |
528 | int quitting; |
529 | { | |
04885cc3 DE |
530 | if (prog_bfd != NULL && prog_bfd_was_opened_p) |
531 | bfd_close (prog_bfd); | |
2934d1c9 MH |
532 | } |
533 | ||
534 | void | |
535 | sim_set_profile (n) | |
536 | int n; | |
537 | { | |
7eebfc62 | 538 | (*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile %d\n",n); |
2934d1c9 MH |
539 | } |
540 | ||
541 | void | |
542 | sim_set_profile_size (n) | |
543 | int n; | |
544 | { | |
7eebfc62 | 545 | (*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile_size %d\n",n); |
2934d1c9 MH |
546 | } |
547 | ||
c422ecc7 MH |
548 | |
549 | uint8 * | |
550 | dmem_addr( addr ) | |
551 | uint32 addr; | |
552 | { | |
553 | int seg; | |
554 | ||
555 | addr &= 0xffff; | |
556 | ||
557 | if (addr > 0xbfff) | |
558 | { | |
559 | if ( (addr & 0xfff0) != 0xff00) | |
04885cc3 DE |
560 | { |
561 | (*d10v_callback->printf_filtered) (d10v_callback, "Data address 0x%lx is in I/O space, pc = 0x%lx.\n", | |
562 | (long)addr, (long)decode_pc ()); | |
563 | State.exception = SIGBUS; | |
564 | } | |
565 | ||
c422ecc7 MH |
566 | return State.dmem + addr; |
567 | } | |
568 | ||
569 | if (addr > 0x7fff) | |
570 | { | |
571 | if (DMAP & 0x1000) | |
572 | { | |
573 | /* instruction memory */ | |
574 | return (DMAP & 0xf) * 0x4000 + State.imem; | |
575 | } | |
576 | /* unified memory */ | |
577 | /* this is ugly because we allocate unified memory in 128K segments and */ | |
578 | /* dmap addresses 16k segments */ | |
cee402dd | 579 | seg = (DMAP & 0x3ff) >> 3; |
c422ecc7 MH |
580 | if (State.umem[seg] == NULL) |
581 | { | |
b30cdd35 MM |
582 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unified memory region %d unmapped, pc = 0x%lx\n", |
583 | seg, (long)decode_pc ()); | |
04885cc3 | 584 | State.exception = SIGBUS; |
c422ecc7 | 585 | } |
cee402dd | 586 | return State.umem[seg] + (DMAP & 7) * 0x4000; |
c422ecc7 MH |
587 | } |
588 | ||
589 | return State.dmem + addr; | |
590 | } | |
591 | ||
592 | ||
593 | static uint8 * | |
594 | pc_addr() | |
595 | { | |
596 | uint32 pc = ((uint32)PC) << 2; | |
597 | uint16 imap; | |
598 | ||
599 | if (pc & 0x20000) | |
600 | imap = IMAP1; | |
601 | else | |
602 | imap = IMAP0; | |
603 | ||
604 | if (imap & 0x1000) | |
605 | return State.imem + pc; | |
606 | ||
607 | if (State.umem[imap & 0xff] == NULL) | |
608 | { | |
b30cdd35 MM |
609 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unified memory region %d unmapped, pc = 0x%lx\n", |
610 | imap & 0xff, (long)PC); | |
04885cc3 | 611 | State.exception = SIGBUS; |
c422ecc7 MH |
612 | return 0; |
613 | } | |
614 | ||
9e03a68f AC |
615 | /* Discard upper bit(s) of PC in case IMAP1 selects unified memory. */ |
616 | pc &= (1 << UMEM_SIZE) - 1; | |
617 | ||
c422ecc7 MH |
618 | return State.umem[imap & 0xff] + pc; |
619 | } | |
620 | ||
621 | ||
193e528c | 622 | static int stop_simulator = 0; |
cee402dd | 623 | |
8517f62b AC |
624 | int |
625 | sim_stop (sd) | |
626 | SIM_DESC sd; | |
627 | { | |
628 | stop_simulator = 1; | |
629 | return 1; | |
630 | } | |
631 | ||
632 | ||
cee402dd | 633 | /* Run (or resume) the program. */ |
2934d1c9 | 634 | void |
04885cc3 DE |
635 | sim_resume (sd, step, siggnal) |
636 | SIM_DESC sd; | |
2934d1c9 MH |
637 | int step, siggnal; |
638 | { | |
639 | uint32 inst; | |
2934d1c9 | 640 | |
7eebfc62 | 641 | /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */ |
eca43eb1 | 642 | State.exception = 0; |
193e528c FF |
643 | if (step) |
644 | sim_stop (sd); | |
cee402dd | 645 | |
aeb1f26b MM |
646 | do |
647 | { | |
c422ecc7 | 648 | inst = get_longword( pc_addr() ); |
cee402dd | 649 | State.pc_changed = 0; |
c422ecc7 MH |
650 | ins_type_counters[ (int)INS_CYCLES ]++; |
651 | switch (inst & 0xC0000000) | |
aeb1f26b | 652 | { |
c422ecc7 MH |
653 | case 0xC0000000: |
654 | /* long instruction */ | |
655 | do_long (inst & 0x3FFFFFFF); | |
656 | break; | |
657 | case 0x80000000: | |
658 | /* R -> L */ | |
193e528c | 659 | do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15, RIGHT_FIRST); |
c422ecc7 MH |
660 | break; |
661 | case 0x40000000: | |
662 | /* L -> R */ | |
193e528c | 663 | do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF, LEFT_FIRST); |
c422ecc7 MH |
664 | break; |
665 | case 0: | |
666 | do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF); | |
667 | break; | |
aeb1f26b | 668 | } |
c422ecc7 | 669 | |
193e528c FF |
670 | /* calculate the next PC */ |
671 | if (!State.pc_changed) | |
aeb1f26b | 672 | { |
193e528c | 673 | if (State.RP && PC == RPT_E) |
9e03a68f | 674 | { |
193e528c FF |
675 | /* Note: The behavour of a branch instruction at RPT_E |
676 | is implementation dependant, this simulator takes the | |
677 | branch. Branching to RPT_E is valid, the instruction | |
678 | must be executed before the loop is taken. */ | |
679 | RPT_C -= 1; | |
680 | if (RPT_C == 0) | |
681 | { | |
682 | State.RP = 0; | |
683 | PC++; | |
684 | } | |
685 | else | |
686 | PC = RPT_S; | |
9e03a68f | 687 | } |
c422ecc7 | 688 | else |
193e528c | 689 | PC++; |
aeb1f26b | 690 | } |
193e528c | 691 | } |
cee402dd | 692 | while ( !State.exception && !stop_simulator); |
c422ecc7 | 693 | |
aeb1f26b MM |
694 | if (step && !State.exception) |
695 | State.exception = SIGTRAP; | |
2934d1c9 MH |
696 | } |
697 | ||
698 | int | |
04885cc3 DE |
699 | sim_trace (sd) |
700 | SIM_DESC sd; | |
2934d1c9 | 701 | { |
7eebfc62 MM |
702 | #ifdef DEBUG |
703 | d10v_debug = DEBUG; | |
704 | #endif | |
04885cc3 | 705 | sim_resume (sd, 0, 0); |
7eebfc62 | 706 | return 1; |
2934d1c9 MH |
707 | } |
708 | ||
709 | void | |
04885cc3 DE |
710 | sim_info (sd, verbose) |
711 | SIM_DESC sd; | |
2934d1c9 MH |
712 | int verbose; |
713 | { | |
aeb1f26b MM |
714 | char buf1[40]; |
715 | char buf2[40]; | |
716 | char buf3[40]; | |
717 | char buf4[40]; | |
718 | char buf5[40]; | |
719 | unsigned long left = ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_COND_EXE ]; | |
720 | unsigned long left_nops = ins_type_counters[ (int)INS_LEFT_NOPS ]; | |
721 | unsigned long left_parallel = ins_type_counters[ (int)INS_LEFT_PARALLEL ]; | |
722 | unsigned long left_cond = ins_type_counters[ (int)INS_LEFT_COND_TEST ]; | |
723 | unsigned long left_total = left + left_parallel + left_cond + left_nops; | |
724 | ||
725 | unsigned long right = ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_COND_EXE ]; | |
726 | unsigned long right_nops = ins_type_counters[ (int)INS_RIGHT_NOPS ]; | |
727 | unsigned long right_parallel = ins_type_counters[ (int)INS_RIGHT_PARALLEL ]; | |
728 | unsigned long right_cond = ins_type_counters[ (int)INS_RIGHT_COND_TEST ]; | |
729 | unsigned long right_total = right + right_parallel + right_cond + right_nops; | |
730 | ||
731 | unsigned long unknown = ins_type_counters[ (int)INS_UNKNOWN ]; | |
732 | unsigned long ins_long = ins_type_counters[ (int)INS_LONG ]; | |
c422ecc7 MH |
733 | unsigned long parallel = ins_type_counters[ (int)INS_PARALLEL ]; |
734 | unsigned long leftright = ins_type_counters[ (int)INS_LEFTRIGHT ]; | |
735 | unsigned long rightleft = ins_type_counters[ (int)INS_RIGHTLEFT ]; | |
aeb1f26b MM |
736 | unsigned long cond_true = ins_type_counters[ (int)INS_COND_TRUE ]; |
737 | unsigned long cond_false = ins_type_counters[ (int)INS_COND_FALSE ]; | |
c422ecc7 | 738 | unsigned long cond_jump = ins_type_counters[ (int)INS_COND_JUMP ]; |
aeb1f26b MM |
739 | unsigned long cycles = ins_type_counters[ (int)INS_CYCLES ]; |
740 | unsigned long total = (unknown + left_total + right_total + ins_long); | |
741 | ||
742 | int size = strlen (add_commas (buf1, sizeof (buf1), total)); | |
743 | int parallel_size = strlen (add_commas (buf1, sizeof (buf1), | |
744 | (left_parallel > right_parallel) ? left_parallel : right_parallel)); | |
745 | int cond_size = strlen (add_commas (buf1, sizeof (buf1), (left_cond > right_cond) ? left_cond : right_cond)); | |
746 | int nop_size = strlen (add_commas (buf1, sizeof (buf1), (left_nops > right_nops) ? left_nops : right_nops)); | |
747 | int normal_size = strlen (add_commas (buf1, sizeof (buf1), (left > right) ? left : right)); | |
748 | ||
749 | (*d10v_callback->printf_filtered) (d10v_callback, | |
c422ecc7 | 750 | "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n", |
aeb1f26b MM |
751 | size, add_commas (buf1, sizeof (buf1), left_total), |
752 | normal_size, add_commas (buf2, sizeof (buf2), left), | |
753 | parallel_size, add_commas (buf3, sizeof (buf3), left_parallel), | |
754 | cond_size, add_commas (buf4, sizeof (buf4), left_cond), | |
755 | nop_size, add_commas (buf5, sizeof (buf5), left_nops)); | |
756 | ||
757 | (*d10v_callback->printf_filtered) (d10v_callback, | |
c422ecc7 | 758 | "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n", |
aeb1f26b MM |
759 | size, add_commas (buf1, sizeof (buf1), right_total), |
760 | normal_size, add_commas (buf2, sizeof (buf2), right), | |
761 | parallel_size, add_commas (buf3, sizeof (buf3), right_parallel), | |
762 | cond_size, add_commas (buf4, sizeof (buf4), right_cond), | |
763 | nop_size, add_commas (buf5, sizeof (buf5), right_nops)); | |
764 | ||
c422ecc7 MH |
765 | if (ins_long) |
766 | (*d10v_callback->printf_filtered) (d10v_callback, | |
767 | "executed %*s long instruction(s)\n", | |
768 | size, add_commas (buf1, sizeof (buf1), ins_long)); | |
769 | ||
770 | if (parallel) | |
771 | (*d10v_callback->printf_filtered) (d10v_callback, | |
772 | "executed %*s parallel instruction(s)\n", | |
773 | size, add_commas (buf1, sizeof (buf1), parallel)); | |
774 | ||
775 | if (leftright) | |
776 | (*d10v_callback->printf_filtered) (d10v_callback, | |
777 | "executed %*s instruction(s) encoded L->R\n", | |
778 | size, add_commas (buf1, sizeof (buf1), leftright)); | |
779 | ||
780 | if (rightleft) | |
781 | (*d10v_callback->printf_filtered) (d10v_callback, | |
782 | "executed %*s instruction(s) encoded R->L\n", | |
783 | size, add_commas (buf1, sizeof (buf1), rightleft)); | |
7eebfc62 | 784 | |
aeb1f26b MM |
785 | if (unknown) |
786 | (*d10v_callback->printf_filtered) (d10v_callback, | |
c422ecc7 | 787 | "executed %*s unknown instruction(s)\n", |
aeb1f26b | 788 | size, add_commas (buf1, sizeof (buf1), unknown)); |
7eebfc62 | 789 | |
c422ecc7 MH |
790 | if (cond_true) |
791 | (*d10v_callback->printf_filtered) (d10v_callback, | |
792 | "executed %*s instruction(s) due to EXExxx condition being true\n", | |
793 | size, add_commas (buf1, sizeof (buf1), cond_true)); | |
7eebfc62 | 794 | |
c422ecc7 MH |
795 | if (cond_false) |
796 | (*d10v_callback->printf_filtered) (d10v_callback, | |
797 | "skipped %*s instruction(s) due to EXExxx condition being false\n", | |
798 | size, add_commas (buf1, sizeof (buf1), cond_false)); | |
799 | ||
800 | if (cond_jump) | |
801 | (*d10v_callback->printf_filtered) (d10v_callback, | |
802 | "skipped %*s instruction(s) due to conditional branch succeeding\n", | |
803 | size, add_commas (buf1, sizeof (buf1), cond_jump)); | |
7eebfc62 MM |
804 | |
805 | (*d10v_callback->printf_filtered) (d10v_callback, | |
c422ecc7 | 806 | "executed %*s cycle(s)\n", |
aeb1f26b | 807 | size, add_commas (buf1, sizeof (buf1), cycles)); |
7eebfc62 MM |
808 | |
809 | (*d10v_callback->printf_filtered) (d10v_callback, | |
aeb1f26b MM |
810 | "executed %*s total instructions\n", |
811 | size, add_commas (buf1, sizeof (buf1), total)); | |
2934d1c9 MH |
812 | } |
813 | ||
04885cc3 | 814 | SIM_RC |
fafce69a | 815 | sim_create_inferior (sd, abfd, argv, env) |
04885cc3 | 816 | SIM_DESC sd; |
fafce69a | 817 | struct _bfd *abfd; |
2934d1c9 MH |
818 | char **argv; |
819 | char **env; | |
820 | { | |
fafce69a | 821 | bfd_vma start_address; |
c422ecc7 | 822 | |
57bc1a72 | 823 | /* reset all state information */ |
c422ecc7 MH |
824 | memset (&State.regs, 0, (int)&State.imem - (int)&State.regs[0]); |
825 | ||
57bc1a72 | 826 | /* set PC */ |
fafce69a AC |
827 | if (abfd != NULL) |
828 | start_address = bfd_get_start_address (prog_bfd); | |
829 | else | |
830 | start_address = 0xffc0 << 2; | |
831 | #ifdef DEBUG | |
832 | if (d10v_debug) | |
833 | (*d10v_callback->printf_filtered) (d10v_callback, "sim_create_inferior: PC=0x%lx\n", (long) start_address); | |
834 | #endif | |
2934d1c9 | 835 | PC = start_address >> 2; |
c422ecc7 MH |
836 | |
837 | /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board */ | |
838 | /* resets imap0 and imap1 to 0x1000. */ | |
839 | ||
840 | SET_IMAP0(0x1000); | |
841 | SET_IMAP1(0x1000); | |
842 | SET_DMAP(0); | |
04885cc3 DE |
843 | |
844 | return SIM_RC_OK; | |
2934d1c9 MH |
845 | } |
846 | ||
847 | ||
2934d1c9 | 848 | void |
247fccde | 849 | sim_set_callbacks (p) |
2934d1c9 MH |
850 | host_callback *p; |
851 | { | |
87178dbd | 852 | d10v_callback = p; |
2934d1c9 MH |
853 | } |
854 | ||
855 | void | |
04885cc3 DE |
856 | sim_stop_reason (sd, reason, sigrc) |
857 | SIM_DESC sd; | |
2934d1c9 MH |
858 | enum sim_stop *reason; |
859 | int *sigrc; | |
860 | { | |
7eebfc62 | 861 | /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */ |
d70b4d42 | 862 | |
a49a15ad | 863 | switch (State.exception) |
d70b4d42 | 864 | { |
a49a15ad | 865 | case SIG_D10V_STOP: /* stop instruction */ |
d70b4d42 | 866 | *reason = sim_exited; |
a49a15ad MM |
867 | *sigrc = 0; |
868 | break; | |
869 | ||
870 | case SIG_D10V_EXIT: /* exit trap */ | |
871 | *reason = sim_exited; | |
872 | *sigrc = State.regs[2]; | |
873 | break; | |
874 | ||
875 | default: /* some signal */ | |
d70b4d42 | 876 | *reason = sim_stopped; |
193e528c FF |
877 | if (stop_simulator && !State.exception) |
878 | *sigrc = SIGINT; | |
879 | else | |
880 | *sigrc = State.exception; | |
a49a15ad | 881 | break; |
193e528c FF |
882 | } |
883 | ||
884 | stop_simulator = 0; | |
d70b4d42 MH |
885 | } |
886 | ||
887 | void | |
04885cc3 DE |
888 | sim_fetch_register (sd, rn, memory) |
889 | SIM_DESC sd; | |
d70b4d42 MH |
890 | int rn; |
891 | unsigned char *memory; | |
892 | { | |
c422ecc7 MH |
893 | if (!State.imem) |
894 | init_system(); | |
895 | ||
896 | if (rn > 34) | |
5c839c67 | 897 | WRITE_64 (memory, State.a[rn-35]); |
c422ecc7 MH |
898 | else if (rn == 32) |
899 | WRITE_16 (memory, IMAP0); | |
900 | else if (rn == 33) | |
901 | WRITE_16 (memory, IMAP1); | |
902 | else if (rn == 34) | |
903 | WRITE_16 (memory, DMAP); | |
d70b4d42 | 904 | else |
c422ecc7 | 905 | WRITE_16 (memory, State.regs[rn]); |
d70b4d42 MH |
906 | } |
907 | ||
908 | void | |
04885cc3 DE |
909 | sim_store_register (sd, rn, memory) |
910 | SIM_DESC sd; | |
d70b4d42 MH |
911 | int rn; |
912 | unsigned char *memory; | |
913 | { | |
c422ecc7 MH |
914 | if (!State.imem) |
915 | init_system(); | |
916 | ||
917 | if (rn > 34) | |
5c839c67 | 918 | State.a[rn-35] = READ_64 (memory) & MASK40; |
c422ecc7 MH |
919 | else if (rn == 34) |
920 | SET_DMAP( READ_16(memory) ); | |
921 | else if (rn == 33) | |
922 | SET_IMAP1( READ_16(memory) ); | |
923 | else if (rn == 32) | |
924 | SET_IMAP0( READ_16(memory) ); | |
d70b4d42 | 925 | else |
c422ecc7 | 926 | State.regs[rn]= READ_16 (memory); |
2934d1c9 | 927 | } |
d70b4d42 | 928 | |
d70b4d42 MH |
929 | |
930 | void | |
04885cc3 DE |
931 | sim_do_command (sd, cmd) |
932 | SIM_DESC sd; | |
d70b4d42 MH |
933 | char *cmd; |
934 | { | |
7eebfc62 | 935 | (*d10v_callback->printf_filtered) (d10v_callback, "sim_do_command: %s\n",cmd); |
d70b4d42 MH |
936 | } |
937 | ||
04885cc3 DE |
938 | SIM_RC |
939 | sim_load (sd, prog, abfd, from_tty) | |
940 | SIM_DESC sd; | |
d70b4d42 | 941 | char *prog; |
04885cc3 | 942 | bfd *abfd; |
d70b4d42 MH |
943 | int from_tty; |
944 | { | |
04885cc3 DE |
945 | extern bfd *sim_load_file (); /* ??? Don't know where this should live. */ |
946 | ||
947 | if (prog_bfd != NULL && prog_bfd_was_opened_p) | |
948 | bfd_close (prog_bfd); | |
949 | prog_bfd = sim_load_file (sd, myname, d10v_callback, prog, abfd, | |
9e03a68f AC |
950 | sim_kind == SIM_OPEN_DEBUG, |
951 | 0, sim_write_phys); | |
04885cc3 DE |
952 | if (prog_bfd == NULL) |
953 | return SIM_RC_FAIL; | |
04885cc3 DE |
954 | prog_bfd_was_opened_p = abfd == NULL; |
955 | return SIM_RC_OK; | |
d70b4d42 | 956 | } |