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* Makefile.in (SIM_OBJS): Add sim-load.o.
[deliverable/binutils-gdb.git] / sim / d10v / interp.c
CommitLineData
d70b4d42 1#include <signal.h>
2934d1c9 2#include "sysdep.h"
cee402dd 3#include "callback.h"
2934d1c9 4#include "remote-sim.h"
2934d1c9
MH		 5
6#include "d10v_sim.h"
7
8#define IMEM_SIZE 18 /* D10V instruction memory size is 18 bits */
c422ecc7
MH		 9#define DMEM_SIZE 16 /* Data memory is 64K (but only 32K internal RAM) */
10#define UMEM_SIZE 17 /* each unified memory region is 17 bits */
2934d1c9 11
87178dbd
MM		 12enum _leftright { LEFT_FIRST, RIGHT_FIRST };
13
7eebfc62 14int d10v_debug;
87178dbd 15host_callback *d10v_callback;
aeb1f26b 16unsigned long ins_type_counters[ (int)INS_MAX ];
87178dbd 17
2934d1c9
MH		 18uint16 OP[4];
19
b30cdd35
MM		 20static int init_text_p = 0;
21asection *text;
22bfd_vma text_start;
23bfd_vma text_end;
24
aeb1f26b 25static long hash PARAMS ((long insn, int format));
2934d1c9 26static struct hash_entry *lookup_hash PARAMS ((uint32 ins, int size));
aeb1f26b
MM		 27static void get_operands PARAMS ((struct simops *s, uint32 ins));
28static void do_long PARAMS ((uint32 ins));
29static void do_2_short PARAMS ((uint16 ins1, uint16 ins2, enum _leftright leftright));
30static void do_parallel PARAMS ((uint16 ins1, uint16 ins2));
31static char *add_commas PARAMS ((char *buf, int sizeof_buf, unsigned long value));
32extern void sim_size PARAMS ((int power));
33static void init_system PARAMS ((void));
34extern int sim_write PARAMS ((SIM_ADDR addr, unsigned char *buffer, int size));
35extern void sim_open PARAMS ((char *args));
36extern void sim_close PARAMS ((int quitting));
37extern void sim_set_profile PARAMS ((int n));
38extern void sim_set_profile_size PARAMS ((int n));
39extern void sim_resume PARAMS ((int step, int siggnal));
40extern void sim_info PARAMS ((int verbose));
41extern void sim_create_inferior PARAMS ((SIM_ADDR start_address, char **argv, char **env));
42extern void sim_kill PARAMS ((void));
43extern void sim_set_callbacks PARAMS ((host_callback *p));
44extern void sim_stop_reason PARAMS ((enum sim_stop *reason, int *sigrc));
45extern void sim_fetch_register PARAMS ((int rn, unsigned char *memory));
46extern void sim_store_register PARAMS ((int rn, unsigned char *memory));
47extern int sim_read PARAMS ((SIM_ADDR addr, unsigned char *buffer, int size));
48extern void sim_do_command PARAMS ((char *cmd));
49
50#ifndef INLINE
51#if defined(__GNUC__) && defined(__OPTIMIZE__)
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
2934d1c9
MH		 57
58#define MAX_HASH 63
59struct hash_entry
60{
61 struct hash_entry *next;
62 long opcode;
63 long mask;
cee402dd 64 int size;
2934d1c9
MH		 65 struct simops *ops;
66};
67
68struct hash_entry hash_table[MAX_HASH+1];
69
aeb1f26b 70INLINE static long
2934d1c9
MH		 71hash(insn, format)
72 long insn;
73 int format;
74{
75 if (format & LONG_OPCODE)
76 return ((insn & 0x3F000000) >> 24);
77 else
78 return((insn & 0x7E00) >> 9);
79}
80
aeb1f26b 81INLINE static struct hash_entry *
2934d1c9
MH		 82lookup_hash (ins, size)
83 uint32 ins;
84 int size;
85{
86 struct hash_entry *h;
87
88 if (size)
89 h = &hash_table[(ins & 0x3F000000) >> 24];
90 else
91 h = &hash_table[(ins & 0x7E00) >> 9];
92
cee402dd 93 while ((ins & h->mask) != h->opcode || h->size != size)
2934d1c9
MH		 94 {
95 if (h->next == NULL)
96 {
7eebfc62 97 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR looking up hash for %x at PC %x\n",ins, PC);
aeb1f26b 98 exit (1);
2934d1c9
MH		 99 }
100 h = h->next;
101 }
102 return (h);
103}
104
aeb1f26b 105INLINE static void
2934d1c9
MH		 106get_operands (struct simops *s, uint32 ins)
107{
108 int i, shift, bits, flags;
109 uint32 mask;
110 for (i=0; i < s->numops; i++)
111 {
112 shift = s->operands[3*i];
113 bits = s->operands[3*i+1];
114 flags = s->operands[3*i+2];
115 mask = 0x7FFFFFFF >> (31 - bits);
116 OP[i] = (ins >> shift) & mask;
117 }
118}
119
b30cdd35
MM		 120bfd_vma
121decode_pc ()
122{
123 asection *s;
124 if (!init_text_p)
125 {
126 init_text_p = 1;
127 for (s = exec_bfd->sections; s; s = s->next)
128 if (strcmp (bfd_get_section_name (exec_bfd, s), ".text") == 0)
129 {
130 text = s;
131 text_start = bfd_get_section_vma (exec_bfd, s);
132 text_end = text_start + bfd_section_size (exec_bfd, s);
133 break;
134 }
135 }
136
137 return (PC << 2) + text_start;
138}
139
2934d1c9
MH		 140static void
141do_long (ins)
142 uint32 ins;
143{
144 struct hash_entry *h;
7eebfc62
MM		 145#ifdef DEBUG
146 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
147 (*d10v_callback->printf_filtered) (d10v_callback, "do_long 0x%x\n", ins);
148#endif
2934d1c9
MH		 149 h = lookup_hash (ins, 1);
150 get_operands (h->ops, ins);
87178dbd 151 State.ins_type = INS_LONG;
7eebfc62 152 ins_type_counters[ (int)State.ins_type ]++;
2934d1c9
MH		 153 (h->ops->func)();
154}
215ac953 155
2934d1c9 156static void
87178dbd 157do_2_short (ins1, ins2, leftright)
2934d1c9 158 uint16 ins1, ins2;
87178dbd 159 enum _leftright leftright;
2934d1c9
MH		 160{
161 struct hash_entry *h;
215ac953 162 reg_t orig_pc = PC;
c422ecc7 163 enum _ins_type first, second;
215ac953 164
7eebfc62
MM		 165#ifdef DEBUG
166 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
167 (*d10v_callback->printf_filtered) (d10v_callback, "do_2_short 0x%x (%s) -> 0x%x\n",
168 ins1, (leftright) ? "left" : "right", ins2);
169#endif
c422ecc7
MH		 170
171 if (leftright == LEFT_FIRST)
172 {
173 first = INS_LEFT;
174 second = INS_RIGHT;
175 ins_type_counters[ (int)INS_LEFTRIGHT ]++;
176 }
177 else
178 {
179 first = INS_RIGHT;
180 second = INS_LEFT;
181 ins_type_counters[ (int)INS_RIGHTLEFT ]++;
182 }
183
2934d1c9
MH		 184 h = lookup_hash (ins1, 0);
185 get_operands (h->ops, ins1);
c422ecc7 186 State.ins_type = first;
7eebfc62 187 ins_type_counters[ (int)State.ins_type ]++;
2934d1c9 188 (h->ops->func)();
215ac953
MM		 189
190 /* If the PC has changed (ie, a jump), don't do the second instruction */
57bc1a72 191 if (orig_pc == PC && !State.exception)
215ac953
MM		 192 {
193 h = lookup_hash (ins2, 0);
194 get_operands (h->ops, ins2);
c422ecc7 195 State.ins_type = second;
215ac953 196 ins_type_counters[ (int)State.ins_type ]++;
c422ecc7 197 ins_type_counters[ (int)INS_CYCLES ]++;
215ac953
MM		 198 (h->ops->func)();
199 }
c422ecc7
MH		 200 else if (orig_pc != PC && !State.exception)
201 ins_type_counters[ (int)INS_COND_JUMP ]++;
2934d1c9 202}
215ac953 203
2934d1c9
MH		 204static void
205do_parallel (ins1, ins2)
206 uint16 ins1, ins2;
207{
208 struct hash_entry *h1, *h2;
7eebfc62
MM		 209#ifdef DEBUG
210 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
211 (*d10v_callback->printf_filtered) (d10v_callback, "do_parallel 0x%x || 0x%x\n", ins1, ins2);
212#endif
c422ecc7 213 ins_type_counters[ (int)INS_PARALLEL ]++;
2934d1c9 214 h1 = lookup_hash (ins1, 0);
2934d1c9 215 h2 = lookup_hash (ins2, 0);
d70b4d42 216
2934d1c9
MH		 217 if (h1->ops->exec_type == PARONLY)
218 {
d70b4d42 219 get_operands (h1->ops, ins1);
aeb1f26b 220 State.ins_type = INS_LEFT_COND_TEST;
7eebfc62 221 ins_type_counters[ (int)State.ins_type ]++;
2934d1c9
MH		 222 (h1->ops->func)();
223 if (State.exe)
d70b4d42 224 {
aeb1f26b 225 ins_type_counters[ (int)INS_COND_TRUE ]++;
d70b4d42 226 get_operands (h2->ops, ins2);
aeb1f26b
MM		 227 State.ins_type = INS_RIGHT_COND_EXE;
228 ins_type_counters[ (int)State.ins_type ]++;
d70b4d42
MH		 229 (h2->ops->func)();
230 }
aeb1f26b
MM		 231 else
232 ins_type_counters[ (int)INS_COND_FALSE ]++;
2934d1c9
MH		 233 }
234 else if (h2->ops->exec_type == PARONLY)
235 {
d70b4d42 236 get_operands (h2->ops, ins2);
aeb1f26b 237 State.ins_type = INS_RIGHT_COND_TEST;
7eebfc62 238 ins_type_counters[ (int)State.ins_type ]++;
2934d1c9
MH		 239 (h2->ops->func)();
240 if (State.exe)
d70b4d42 241 {
aeb1f26b 242 ins_type_counters[ (int)INS_COND_TRUE ]++;
d70b4d42 243 get_operands (h1->ops, ins1);
aeb1f26b
MM		 244 State.ins_type = INS_LEFT_COND_EXE;
245 ins_type_counters[ (int)State.ins_type ]++;
d70b4d42
MH		 246 (h1->ops->func)();
247 }
aeb1f26b
MM		 248 else
249 ins_type_counters[ (int)INS_COND_FALSE ]++;
2934d1c9
MH		 250 }
251 else
252 {
d70b4d42 253 get_operands (h1->ops, ins1);
87178dbd 254 State.ins_type = INS_LEFT_PARALLEL;
7eebfc62 255 ins_type_counters[ (int)State.ins_type ]++;
2934d1c9 256 (h1->ops->func)();
57bc1a72
MM		 257 if (!State.exception)
258 {
259 get_operands (h2->ops, ins2);
260 State.ins_type = INS_RIGHT_PARALLEL;
261 ins_type_counters[ (int)State.ins_type ]++;
262 (h2->ops->func)();
263 }
2934d1c9
MH		 264 }
265}
266
aeb1f26b
MM		 267static char *
268add_commas(buf, sizeof_buf, value)
269 char *buf;
270 int sizeof_buf;
271 unsigned long value;
272{
273 int comma = 3;
274 char *endbuf = buf + sizeof_buf - 1;
275
276 *--endbuf = '\0';
277 do {
278 if (comma-- == 0)
279 {
280 *--endbuf = ',';
281 comma = 2;
282 }
283
284 *--endbuf = (value % 10) + '0';
285 } while ((value /= 10) != 0);
286
287 return endbuf;
288}
2934d1c9
MH		 289
290void
291sim_size (power)
292 int power;
293
294{
c422ecc7
MH		 295 int i;
296
2934d1c9
MH		 297 if (State.imem)
298 {
c422ecc7
MH		 299 for (i=0;i<128;i++)
300 {
301 if (State.umem[i])
302 {
303 free (State.umem[i]);
304 State.umem[i] = NULL;
305 }
306 }
2934d1c9
MH		 307 free (State.imem);
308 free (State.dmem);
309 }
310
311 State.imem = (uint8 *)calloc(1,1<<IMEM_SIZE);
312 State.dmem = (uint8 *)calloc(1,1<<DMEM_SIZE);
c422ecc7
MH		 313 for (i=1;i<127;i++)
314 State.umem[i] = NULL;
315 State.umem[0] = (uint8 *)calloc(1,1<<UMEM_SIZE);
316 State.umem[1] = (uint8 *)calloc(1,1<<UMEM_SIZE);
317 State.umem[2] = (uint8 *)calloc(1,1<<UMEM_SIZE);
318 State.umem[127] = (uint8 *)calloc(1,1<<UMEM_SIZE);
319 if (!State.imem || !State.dmem || !State.umem[0] || !State.umem[1] || !State.umem[2] || !State.umem[127] )
2934d1c9 320 {
7eebfc62 321 (*d10v_callback->printf_filtered) (d10v_callback, "Memory allocation failed.\n");
2934d1c9
MH		 322 exit(1);
323 }
c422ecc7
MH		 324
325 SET_IMAP0(0x1000);
326 SET_IMAP1(0x1000);
327 SET_DMAP(0);
57bc1a72 328
7eebfc62
MM		 329#ifdef DEBUG
330 if ((d10v_debug & DEBUG_MEMSIZE) != 0)
331 {
aeb1f26b
MM		 332 char buffer[20];
333 (*d10v_callback->printf_filtered) (d10v_callback,
334 "Allocated %s bytes instruction memory and\n",
335 add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)));
336
337 (*d10v_callback->printf_filtered) (d10v_callback, " %s bytes data memory.\n",
338 add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)));
7eebfc62 339 }
87178dbd 340#endif
2934d1c9
MH		 341}
342
343static void
344init_system ()
345{
346 if (!State.imem)
347 sim_size(1);
348}
349
c422ecc7
MH		 350static int
351xfer_mem (addr, buffer, size, write)
2934d1c9
MH		 352 SIM_ADDR addr;
353 unsigned char *buffer;
354 int size;
c422ecc7 355 int write;
2934d1c9 356{
c422ecc7
MH		 357 if (!State.imem)
358 init_system ();
2934d1c9 359
57bc1a72
MM		 360#ifdef DEBUG
361 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
c422ecc7
MH		 362 {
363 if (write)
364 (*d10v_callback->printf_filtered) (d10v_callback, "sim_write %d bytes to 0x%x\n", size, addr);
365 else
366 (*d10v_callback->printf_filtered) (d10v_callback, "sim_read %d bytes from 0x%x\n", size, addr);
367 }
57bc1a72
MM		 368#endif
369
c422ecc7
MH		 370 /* to access data, we use the following mapping */
371 /* 0x01000000 - 0x0103ffff : instruction memory */
372 /* 0x02000000 - 0x0200ffff : data memory */
373 /* 0x03000000 - 0x03ffffff : unified memory */
57bc1a72 374
c422ecc7
MH		 375 if ( (addr & 0x03000000) == 0x03000000)
376 {
377 /* UNIFIED MEMORY */
378 int segment;
379 addr &= ~0x03000000;
380 segment = addr >> UMEM_SIZE;
381 addr &= 0x1ffff;
382 if (!State.umem[segment])
383 State.umem[segment] = (uint8 *)calloc(1,1<<UMEM_SIZE);
384 if (!State.umem[segment])
385 {
386 (*d10v_callback->printf_filtered) (d10v_callback, "Memory allocation failed.\n");
387 exit(1);
388 }
389#ifdef DEBUG
390 (*d10v_callback->printf_filtered) (d10v_callback,"Allocated %s bytes unified memory to region %d\n",
391 add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)), segment);
392#endif
393 /* FIXME: need to check size and read/write multiple segments if necessary */
394 if (write)
395 memcpy (State.umem[segment]+addr, buffer, size);
396 else
397 memcpy (buffer, State.umem[segment]+addr, size);
398 }
399 else if ( (addr & 0x03000000) == 0x02000000)
400 {
401 /* DATA MEMORY */
402 addr &= ~0x02000000;
403 if (size > (1<<(DMEM_SIZE-1)))
404 {
405 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: data section is only %d bytes.\n",1<<(DMEM_SIZE-1));
406 exit(1);
407 }
408 if (write)
409 memcpy (State.dmem+addr, buffer, size);
410 else
411 memcpy (buffer, State.dmem+addr, size);
412 }
413 else if ( (addr & 0x03000000) == 0x01000000)
414 {
415 /* INSTRUCTION MEMORY */
416 addr &= ~0x01000000;
417 if (size > (1<<IMEM_SIZE))
418 {
419 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: inst section is only %d bytes.\n",1<<IMEM_SIZE);
420 exit(1);
421 }
422 if (write)
423 memcpy (State.imem+addr, buffer, size);
424 else
425 memcpy (buffer, State.imem+addr, size);
426 }
427 else if (write)
428 {
429 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: address 0x%x is not in valid range\n",addr);
430 (*d10v_callback->printf_filtered) (d10v_callback, "Instruction addresses start at 0x01000000\n");
431 (*d10v_callback->printf_filtered) (d10v_callback, "Data addresses start at 0x02000000\n");
432 (*d10v_callback->printf_filtered) (d10v_callback, "Unified addresses start at 0x03000000\n");
433 exit(1);
434 }
435 else
436 return 0;
57bc1a72 437
2934d1c9
MH		 438 return size;
439}
440
c422ecc7
MH		 441
442int
443sim_write (addr, buffer, size)
444 SIM_ADDR addr;
445 unsigned char *buffer;
446 int size;
447{
448 return xfer_mem( addr, buffer, size, 1);
449}
450
451int
452sim_read (addr, buffer, size)
453 SIM_ADDR addr;
454 unsigned char *buffer;
455 int size;
456{
457 return xfer_mem( addr, buffer, size, 0);
458}
459
460
2934d1c9
MH		 461void
462sim_open (args)
463 char *args;
464{
465 struct simops *s;
aeb1f26b 466 struct hash_entry *h;
1eaaf305
MM		 467 static int init_p = 0;
468
2934d1c9 469 if (args != NULL)
1eaaf305
MM		 470 {
471#ifdef DEBUG
472 if (strcmp (args, "-t") == 0)
473 d10v_debug = DEBUG;
474 else
475#endif
476 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unsupported option(s): %s\n",args);
477 }
c422ecc7 478
2934d1c9 479 /* put all the opcodes in the hash table */
1eaaf305 480 if (!init_p++)
2934d1c9 481 {
1eaaf305 482 for (s = Simops; s->func; s++)
2934d1c9 483 {
1eaaf305
MM		 484 h = &hash_table[hash(s->opcode,s->format)];
485
486 /* go to the last entry in the chain */
487 while (h->next)
488 h = h->next;
489
490 if (h->ops)
491 {
492 h->next = calloc(1,sizeof(struct hash_entry));
493 h = h->next;
494 }
495 h->ops = s;
496 h->mask = s->mask;
497 h->opcode = s->opcode;
cee402dd 498 h->size = s->is_long;
2934d1c9 499 }
2934d1c9
MH		 500 }
501}
502
503
504void
505sim_close (quitting)
506 int quitting;
507{
508 /* nothing to do */
509}
510
511void
512sim_set_profile (n)
513 int n;
514{
7eebfc62 515 (*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile %d\n",n);
2934d1c9
MH		 516}
517
518void
519sim_set_profile_size (n)
520 int n;
521{
7eebfc62 522 (*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile_size %d\n",n);
2934d1c9
MH		 523}
524
c422ecc7
MH		 525
526uint8 *
527dmem_addr( addr )
528 uint32 addr;
529{
530 int seg;
531
532 addr &= 0xffff;
533
534 if (addr > 0xbfff)
535 {
536 if ( (addr & 0xfff0) != 0xff00)
b30cdd35
MM		 537 (*d10v_callback->printf_filtered) (d10v_callback, "Data address 0x%lx is in I/O space, pc = 0x%lx.\n",
538 (long)addr, (long)decode_pc ());
c422ecc7
MH		 539 return State.dmem + addr;
540 }
541
542 if (addr > 0x7fff)
543 {
544 if (DMAP & 0x1000)
545 {
546 /* instruction memory */
547 return (DMAP & 0xf) * 0x4000 + State.imem;
548 }
549 /* unified memory */
550 /* this is ugly because we allocate unified memory in 128K segments and */
551 /* dmap addresses 16k segments */
cee402dd 552 seg = (DMAP & 0x3ff) >> 3;
c422ecc7
MH		 553 if (State.umem[seg] == NULL)
554 {
b30cdd35
MM		 555 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unified memory region %d unmapped, pc = 0x%lx\n",
556 seg, (long)decode_pc ());
c422ecc7
MH		 557 exit(1);
558 }
cee402dd 559 return State.umem[seg] + (DMAP & 7) * 0x4000;
c422ecc7
MH		 560 }
561
562 return State.dmem + addr;
563}
564
565
566static uint8 *
567pc_addr()
568{
569 uint32 pc = ((uint32)PC) << 2;
570 uint16 imap;
571
572 if (pc & 0x20000)
573 imap = IMAP1;
574 else
575 imap = IMAP0;
576
577 if (imap & 0x1000)
578 return State.imem + pc;
579
580 if (State.umem[imap & 0xff] == NULL)
581 {
b30cdd35
MM		 582 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unified memory region %d unmapped, pc = 0x%lx\n",
583 imap & 0xff, (long)PC);
c422ecc7
MH		 584 State.exception = SIGILL;
585 return 0;
586 }
587
588 return State.umem[imap & 0xff] + pc;
589}
590
591
cee402dd
DE		 592static int stop_simulator;
593
594static void
595sim_ctrl_c()
596{
597 stop_simulator = 1;
598}
599
600
601/* Run (or resume) the program. */
2934d1c9
MH		 602void
603sim_resume (step, siggnal)
604 int step, siggnal;
605{
cee402dd 606 void (*prev) ();
2934d1c9 607 uint32 inst;
2934d1c9 608
7eebfc62 609/* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
eca43eb1 610 State.exception = 0;
cee402dd
DE		 611 prev = signal(SIGINT, sim_ctrl_c);
612 stop_simulator = step;
613
aeb1f26b
MM		 614 do
615 {
c422ecc7 616 inst = get_longword( pc_addr() );
cee402dd 617 State.pc_changed = 0;
c422ecc7
MH		 618 ins_type_counters[ (int)INS_CYCLES ]++;
619 switch (inst & 0xC0000000)
aeb1f26b 620 {
c422ecc7
MH		 621 case 0xC0000000:
622 /* long instruction */
623 do_long (inst & 0x3FFFFFFF);
624 break;
625 case 0x80000000:
626 /* R -> L */
627 do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15, 0);
628 break;
629 case 0x40000000:
630 /* L -> R */
631 do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF, 1);
632 break;
633 case 0:
634 do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
635 break;
aeb1f26b 636 }
c422ecc7
MH		 637
638 if (State.RP && PC == RPT_E)
aeb1f26b 639 {
c422ecc7
MH		 640 RPT_C -= 1;
641 if (RPT_C == 0)
642 State.RP = 0;
643 else
644 PC = RPT_S;
aeb1f26b 645 }
cee402dd 646 else if (!State.pc_changed)
c422ecc7 647 PC++;
aeb1f26b 648 }
cee402dd 649 while ( !State.exception && !stop_simulator);
c422ecc7 650
aeb1f26b
MM		 651 if (step && !State.exception)
652 State.exception = SIGTRAP;
cee402dd
DE		 653
654 signal(SIGINT, prev);
2934d1c9
MH		 655}
656
657int
658sim_trace ()
659{
7eebfc62
MM		 660#ifdef DEBUG
661 d10v_debug = DEBUG;
662#endif
663 sim_resume (0, 0);
664 return 1;
2934d1c9
MH		 665}
666
667void
668sim_info (verbose)
669 int verbose;
670{
aeb1f26b
MM		 671 char buf1[40];
672 char buf2[40];
673 char buf3[40];
674 char buf4[40];
675 char buf5[40];
676 unsigned long left = ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_COND_EXE ];
677 unsigned long left_nops = ins_type_counters[ (int)INS_LEFT_NOPS ];
678 unsigned long left_parallel = ins_type_counters[ (int)INS_LEFT_PARALLEL ];
679 unsigned long left_cond = ins_type_counters[ (int)INS_LEFT_COND_TEST ];
680 unsigned long left_total = left + left_parallel + left_cond + left_nops;
681
682 unsigned long right = ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_COND_EXE ];
683 unsigned long right_nops = ins_type_counters[ (int)INS_RIGHT_NOPS ];
684 unsigned long right_parallel = ins_type_counters[ (int)INS_RIGHT_PARALLEL ];
685 unsigned long right_cond = ins_type_counters[ (int)INS_RIGHT_COND_TEST ];
686 unsigned long right_total = right + right_parallel + right_cond + right_nops;
687
688 unsigned long unknown = ins_type_counters[ (int)INS_UNKNOWN ];
689 unsigned long ins_long = ins_type_counters[ (int)INS_LONG ];
c422ecc7
MH		 690 unsigned long parallel = ins_type_counters[ (int)INS_PARALLEL ];
691 unsigned long leftright = ins_type_counters[ (int)INS_LEFTRIGHT ];
692 unsigned long rightleft = ins_type_counters[ (int)INS_RIGHTLEFT ];
aeb1f26b
MM		 693 unsigned long cond_true = ins_type_counters[ (int)INS_COND_TRUE ];
694 unsigned long cond_false = ins_type_counters[ (int)INS_COND_FALSE ];
c422ecc7 695 unsigned long cond_jump = ins_type_counters[ (int)INS_COND_JUMP ];
aeb1f26b
MM		 696 unsigned long cycles = ins_type_counters[ (int)INS_CYCLES ];
697 unsigned long total = (unknown + left_total + right_total + ins_long);
698
699 int size = strlen (add_commas (buf1, sizeof (buf1), total));
700 int parallel_size = strlen (add_commas (buf1, sizeof (buf1),
701 (left_parallel > right_parallel) ? left_parallel : right_parallel));
702 int cond_size = strlen (add_commas (buf1, sizeof (buf1), (left_cond > right_cond) ? left_cond : right_cond));
703 int nop_size = strlen (add_commas (buf1, sizeof (buf1), (left_nops > right_nops) ? left_nops : right_nops));
704 int normal_size = strlen (add_commas (buf1, sizeof (buf1), (left > right) ? left : right));
705
706 (*d10v_callback->printf_filtered) (d10v_callback,
c422ecc7 707 "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
aeb1f26b
MM		 708 size, add_commas (buf1, sizeof (buf1), left_total),
709 normal_size, add_commas (buf2, sizeof (buf2), left),
710 parallel_size, add_commas (buf3, sizeof (buf3), left_parallel),
711 cond_size, add_commas (buf4, sizeof (buf4), left_cond),
712 nop_size, add_commas (buf5, sizeof (buf5), left_nops));
713
714 (*d10v_callback->printf_filtered) (d10v_callback,
c422ecc7 715 "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
aeb1f26b
MM		 716 size, add_commas (buf1, sizeof (buf1), right_total),
717 normal_size, add_commas (buf2, sizeof (buf2), right),
718 parallel_size, add_commas (buf3, sizeof (buf3), right_parallel),
719 cond_size, add_commas (buf4, sizeof (buf4), right_cond),
720 nop_size, add_commas (buf5, sizeof (buf5), right_nops));
721
c422ecc7
MH		 722 if (ins_long)
723 (*d10v_callback->printf_filtered) (d10v_callback,
724 "executed %*s long instruction(s)\n",
725 size, add_commas (buf1, sizeof (buf1), ins_long));
726
727 if (parallel)
728 (*d10v_callback->printf_filtered) (d10v_callback,
729 "executed %*s parallel instruction(s)\n",
730 size, add_commas (buf1, sizeof (buf1), parallel));
731
732 if (leftright)
733 (*d10v_callback->printf_filtered) (d10v_callback,
734 "executed %*s instruction(s) encoded L->R\n",
735 size, add_commas (buf1, sizeof (buf1), leftright));
736
737 if (rightleft)
738 (*d10v_callback->printf_filtered) (d10v_callback,
739 "executed %*s instruction(s) encoded R->L\n",
740 size, add_commas (buf1, sizeof (buf1), rightleft));
7eebfc62 741
aeb1f26b
MM		 742 if (unknown)
743 (*d10v_callback->printf_filtered) (d10v_callback,
c422ecc7 744 "executed %*s unknown instruction(s)\n",
aeb1f26b 745 size, add_commas (buf1, sizeof (buf1), unknown));
7eebfc62 746
c422ecc7
MH		 747 if (cond_true)
748 (*d10v_callback->printf_filtered) (d10v_callback,
749 "executed %*s instruction(s) due to EXExxx condition being true\n",
750 size, add_commas (buf1, sizeof (buf1), cond_true));
7eebfc62 751
c422ecc7
MH		 752 if (cond_false)
753 (*d10v_callback->printf_filtered) (d10v_callback,
754 "skipped %*s instruction(s) due to EXExxx condition being false\n",
755 size, add_commas (buf1, sizeof (buf1), cond_false));
756
757 if (cond_jump)
758 (*d10v_callback->printf_filtered) (d10v_callback,
759 "skipped %*s instruction(s) due to conditional branch succeeding\n",
760 size, add_commas (buf1, sizeof (buf1), cond_jump));
7eebfc62
MM		 761
762 (*d10v_callback->printf_filtered) (d10v_callback,
c422ecc7 763 "executed %*s cycle(s)\n",
aeb1f26b 764 size, add_commas (buf1, sizeof (buf1), cycles));
7eebfc62
MM		 765
766 (*d10v_callback->printf_filtered) (d10v_callback,
aeb1f26b
MM		 767 "executed %*s total instructions\n",
768 size, add_commas (buf1, sizeof (buf1), total));
2934d1c9
MH		 769}
770
771void
772sim_create_inferior (start_address, argv, env)
773 SIM_ADDR start_address;
774 char **argv;
775 char **env;
776{
7eebfc62
MM		 777#ifdef DEBUG
778 if (d10v_debug)
779 (*d10v_callback->printf_filtered) (d10v_callback, "sim_create_inferior: PC=0x%x\n", start_address);
780#endif
c422ecc7 781
57bc1a72 782 /* reset all state information */
c422ecc7
MH		 783 memset (&State.regs, 0, (int)&State.imem - (int)&State.regs[0]);
784
57bc1a72 785 /* set PC */
2934d1c9 786 PC = start_address >> 2;
c422ecc7
MH		 787
788 /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board */
789 /* resets imap0 and imap1 to 0x1000. */
790
791 SET_IMAP0(0x1000);
792 SET_IMAP1(0x1000);
793 SET_DMAP(0);
2934d1c9
MH		 794}
795
796
797void
798sim_kill ()
799{
800 /* nothing to do */
801}
802
803void
804sim_set_callbacks(p)
805 host_callback *p;
806{
87178dbd 807 d10v_callback = p;
2934d1c9
MH		 808}
809
810void
811sim_stop_reason (reason, sigrc)
812 enum sim_stop *reason;
813 int *sigrc;
814{
7eebfc62 815/* (*d10v_callback->printf_filtered) (d10v_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */
d70b4d42 816
a49a15ad 817 switch (State.exception)
d70b4d42 818 {
a49a15ad 819 case SIG_D10V_STOP: /* stop instruction */
d70b4d42 820 *reason = sim_exited;
a49a15ad
MM		 821 *sigrc = 0;
822 break;
823
824 case SIG_D10V_EXIT: /* exit trap */
825 *reason = sim_exited;
826 *sigrc = State.regs[2];
827 break;
828
829 default: /* some signal */
d70b4d42
MH		 830 *reason = sim_stopped;
831 *sigrc = State.exception;
a49a15ad 832 break;
d70b4d42
MH		 833 }
834}
835
836void
837sim_fetch_register (rn, memory)
838 int rn;
839 unsigned char *memory;
840{
c422ecc7
MH		 841 if (!State.imem)
842 init_system();
843
844 if (rn > 34)
5c839c67 845 WRITE_64 (memory, State.a[rn-35]);
c422ecc7
MH		 846 else if (rn == 32)
847 WRITE_16 (memory, IMAP0);
848 else if (rn == 33)
849 WRITE_16 (memory, IMAP1);
850 else if (rn == 34)
851 WRITE_16 (memory, DMAP);
d70b4d42 852 else
c422ecc7 853 WRITE_16 (memory, State.regs[rn]);
d70b4d42
MH		 854}
855
856void
857sim_store_register (rn, memory)
858 int rn;
859 unsigned char *memory;
860{
c422ecc7
MH		 861 if (!State.imem)
862 init_system();
863
864 if (rn > 34)
5c839c67 865 State.a[rn-35] = READ_64 (memory) & MASK40;
c422ecc7
MH		 866 else if (rn == 34)
867 SET_DMAP( READ_16(memory) );
868 else if (rn == 33)
869 SET_IMAP1( READ_16(memory) );
870 else if (rn == 32)
871 SET_IMAP0( READ_16(memory) );
d70b4d42 872 else
c422ecc7 873 State.regs[rn]= READ_16 (memory);
2934d1c9 874}
d70b4d42 875
d70b4d42
MH		 876
877void
878sim_do_command (cmd)
879 char *cmd;
880{
7eebfc62 881 (*d10v_callback->printf_filtered) (d10v_callback, "sim_do_command: %s\n",cmd);
d70b4d42
MH		 882}
883
884int
885sim_load (prog, from_tty)
886 char *prog;
887 int from_tty;
888{
889 /* Return nonzero so GDB will handle it. */
890 return 1;
891}
GDB Binutils - Deliverables
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