Commit | Line | Data |
---|---|---|
d70b4d42 | 1 | #include <signal.h> |
2934d1c9 | 2 | #include "sysdep.h" |
04885cc3 | 3 | #include "bfd.h" |
cee402dd | 4 | #include "callback.h" |
2934d1c9 | 5 | #include "remote-sim.h" |
2934d1c9 MH |
6 | |
7 | #include "d10v_sim.h" | |
8 | ||
9 | #define IMEM_SIZE 18 /* D10V instruction memory size is 18 bits */ | |
c422ecc7 MH |
10 | #define DMEM_SIZE 16 /* Data memory is 64K (but only 32K internal RAM) */ |
11 | #define UMEM_SIZE 17 /* each unified memory region is 17 bits */ | |
2934d1c9 | 12 | |
87178dbd MM |
13 | enum _leftright { LEFT_FIRST, RIGHT_FIRST }; |
14 | ||
04885cc3 DE |
15 | static char *myname; |
16 | static SIM_OPEN_KIND sim_kind; | |
17 | static bfd_vma start_address; | |
7eebfc62 | 18 | int d10v_debug; |
87178dbd | 19 | host_callback *d10v_callback; |
aeb1f26b | 20 | unsigned long ins_type_counters[ (int)INS_MAX ]; |
87178dbd | 21 | |
2934d1c9 MH |
22 | uint16 OP[4]; |
23 | ||
b30cdd35 | 24 | static int init_text_p = 0; |
04885cc3 DE |
25 | /* non-zero if we opened prog_bfd */ |
26 | static int prog_bfd_was_opened_p; | |
27 | bfd *prog_bfd; | |
b30cdd35 MM |
28 | asection *text; |
29 | bfd_vma text_start; | |
30 | bfd_vma text_end; | |
31 | ||
aeb1f26b | 32 | static long hash PARAMS ((long insn, int format)); |
2934d1c9 | 33 | static struct hash_entry *lookup_hash PARAMS ((uint32 ins, int size)); |
aeb1f26b MM |
34 | static void get_operands PARAMS ((struct simops *s, uint32 ins)); |
35 | static void do_long PARAMS ((uint32 ins)); | |
36 | static void do_2_short PARAMS ((uint16 ins1, uint16 ins2, enum _leftright leftright)); | |
37 | static void do_parallel PARAMS ((uint16 ins1, uint16 ins2)); | |
38 | static char *add_commas PARAMS ((char *buf, int sizeof_buf, unsigned long value)); | |
39 | extern void sim_size PARAMS ((int power)); | |
40 | static void init_system PARAMS ((void)); | |
aeb1f26b MM |
41 | extern void sim_set_profile PARAMS ((int n)); |
42 | extern void sim_set_profile_size PARAMS ((int n)); | |
aeb1f26b MM |
43 | |
44 | #ifndef INLINE | |
45 | #if defined(__GNUC__) && defined(__OPTIMIZE__) | |
46 | #define INLINE __inline__ | |
47 | #else | |
48 | #define INLINE | |
49 | #endif | |
50 | #endif | |
2934d1c9 MH |
51 | |
52 | #define MAX_HASH 63 | |
53 | struct hash_entry | |
54 | { | |
55 | struct hash_entry *next; | |
56 | long opcode; | |
57 | long mask; | |
cee402dd | 58 | int size; |
2934d1c9 MH |
59 | struct simops *ops; |
60 | }; | |
61 | ||
62 | struct hash_entry hash_table[MAX_HASH+1]; | |
63 | ||
aeb1f26b | 64 | INLINE static long |
2934d1c9 MH |
65 | hash(insn, format) |
66 | long insn; | |
67 | int format; | |
68 | { | |
69 | if (format & LONG_OPCODE) | |
70 | return ((insn & 0x3F000000) >> 24); | |
71 | else | |
72 | return((insn & 0x7E00) >> 9); | |
73 | } | |
74 | ||
aeb1f26b | 75 | INLINE static struct hash_entry * |
2934d1c9 MH |
76 | lookup_hash (ins, size) |
77 | uint32 ins; | |
78 | int size; | |
79 | { | |
80 | struct hash_entry *h; | |
81 | ||
82 | if (size) | |
83 | h = &hash_table[(ins & 0x3F000000) >> 24]; | |
84 | else | |
85 | h = &hash_table[(ins & 0x7E00) >> 9]; | |
86 | ||
cee402dd | 87 | while ((ins & h->mask) != h->opcode || h->size != size) |
2934d1c9 MH |
88 | { |
89 | if (h->next == NULL) | |
90 | { | |
7eebfc62 | 91 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR looking up hash for %x at PC %x\n",ins, PC); |
aeb1f26b | 92 | exit (1); |
2934d1c9 MH |
93 | } |
94 | h = h->next; | |
95 | } | |
96 | return (h); | |
97 | } | |
98 | ||
aeb1f26b | 99 | INLINE static void |
2934d1c9 MH |
100 | get_operands (struct simops *s, uint32 ins) |
101 | { | |
102 | int i, shift, bits, flags; | |
103 | uint32 mask; | |
104 | for (i=0; i < s->numops; i++) | |
105 | { | |
106 | shift = s->operands[3*i]; | |
107 | bits = s->operands[3*i+1]; | |
108 | flags = s->operands[3*i+2]; | |
109 | mask = 0x7FFFFFFF >> (31 - bits); | |
110 | OP[i] = (ins >> shift) & mask; | |
111 | } | |
112 | } | |
113 | ||
b30cdd35 MM |
114 | bfd_vma |
115 | decode_pc () | |
116 | { | |
117 | asection *s; | |
118 | if (!init_text_p) | |
119 | { | |
120 | init_text_p = 1; | |
04885cc3 DE |
121 | for (s = prog_bfd->sections; s; s = s->next) |
122 | if (strcmp (bfd_get_section_name (prog_bfd, s), ".text") == 0) | |
b30cdd35 MM |
123 | { |
124 | text = s; | |
04885cc3 DE |
125 | text_start = bfd_get_section_vma (prog_bfd, s); |
126 | text_end = text_start + bfd_section_size (prog_bfd, s); | |
b30cdd35 MM |
127 | break; |
128 | } | |
129 | } | |
130 | ||
131 | return (PC << 2) + text_start; | |
132 | } | |
133 | ||
2934d1c9 MH |
134 | static void |
135 | do_long (ins) | |
136 | uint32 ins; | |
137 | { | |
138 | struct hash_entry *h; | |
7eebfc62 MM |
139 | #ifdef DEBUG |
140 | if ((d10v_debug & DEBUG_INSTRUCTION) != 0) | |
141 | (*d10v_callback->printf_filtered) (d10v_callback, "do_long 0x%x\n", ins); | |
142 | #endif | |
2934d1c9 MH |
143 | h = lookup_hash (ins, 1); |
144 | get_operands (h->ops, ins); | |
87178dbd | 145 | State.ins_type = INS_LONG; |
7eebfc62 | 146 | ins_type_counters[ (int)State.ins_type ]++; |
2934d1c9 MH |
147 | (h->ops->func)(); |
148 | } | |
215ac953 | 149 | |
2934d1c9 | 150 | static void |
87178dbd | 151 | do_2_short (ins1, ins2, leftright) |
2934d1c9 | 152 | uint16 ins1, ins2; |
87178dbd | 153 | enum _leftright leftright; |
2934d1c9 MH |
154 | { |
155 | struct hash_entry *h; | |
215ac953 | 156 | reg_t orig_pc = PC; |
c422ecc7 | 157 | enum _ins_type first, second; |
215ac953 | 158 | |
7eebfc62 MM |
159 | #ifdef DEBUG |
160 | if ((d10v_debug & DEBUG_INSTRUCTION) != 0) | |
161 | (*d10v_callback->printf_filtered) (d10v_callback, "do_2_short 0x%x (%s) -> 0x%x\n", | |
162 | ins1, (leftright) ? "left" : "right", ins2); | |
163 | #endif | |
c422ecc7 MH |
164 | |
165 | if (leftright == LEFT_FIRST) | |
166 | { | |
167 | first = INS_LEFT; | |
168 | second = INS_RIGHT; | |
169 | ins_type_counters[ (int)INS_LEFTRIGHT ]++; | |
170 | } | |
171 | else | |
172 | { | |
173 | first = INS_RIGHT; | |
174 | second = INS_LEFT; | |
175 | ins_type_counters[ (int)INS_RIGHTLEFT ]++; | |
176 | } | |
177 | ||
2934d1c9 MH |
178 | h = lookup_hash (ins1, 0); |
179 | get_operands (h->ops, ins1); | |
c422ecc7 | 180 | State.ins_type = first; |
7eebfc62 | 181 | ins_type_counters[ (int)State.ins_type ]++; |
2934d1c9 | 182 | (h->ops->func)(); |
215ac953 MM |
183 | |
184 | /* If the PC has changed (ie, a jump), don't do the second instruction */ | |
57bc1a72 | 185 | if (orig_pc == PC && !State.exception) |
215ac953 MM |
186 | { |
187 | h = lookup_hash (ins2, 0); | |
188 | get_operands (h->ops, ins2); | |
c422ecc7 | 189 | State.ins_type = second; |
215ac953 | 190 | ins_type_counters[ (int)State.ins_type ]++; |
c422ecc7 | 191 | ins_type_counters[ (int)INS_CYCLES ]++; |
215ac953 MM |
192 | (h->ops->func)(); |
193 | } | |
c422ecc7 MH |
194 | else if (orig_pc != PC && !State.exception) |
195 | ins_type_counters[ (int)INS_COND_JUMP ]++; | |
2934d1c9 | 196 | } |
215ac953 | 197 | |
2934d1c9 MH |
198 | static void |
199 | do_parallel (ins1, ins2) | |
200 | uint16 ins1, ins2; | |
201 | { | |
202 | struct hash_entry *h1, *h2; | |
7eebfc62 MM |
203 | #ifdef DEBUG |
204 | if ((d10v_debug & DEBUG_INSTRUCTION) != 0) | |
205 | (*d10v_callback->printf_filtered) (d10v_callback, "do_parallel 0x%x || 0x%x\n", ins1, ins2); | |
206 | #endif | |
c422ecc7 | 207 | ins_type_counters[ (int)INS_PARALLEL ]++; |
2934d1c9 | 208 | h1 = lookup_hash (ins1, 0); |
2934d1c9 | 209 | h2 = lookup_hash (ins2, 0); |
d70b4d42 | 210 | |
2934d1c9 MH |
211 | if (h1->ops->exec_type == PARONLY) |
212 | { | |
d70b4d42 | 213 | get_operands (h1->ops, ins1); |
aeb1f26b | 214 | State.ins_type = INS_LEFT_COND_TEST; |
7eebfc62 | 215 | ins_type_counters[ (int)State.ins_type ]++; |
2934d1c9 MH |
216 | (h1->ops->func)(); |
217 | if (State.exe) | |
d70b4d42 | 218 | { |
aeb1f26b | 219 | ins_type_counters[ (int)INS_COND_TRUE ]++; |
d70b4d42 | 220 | get_operands (h2->ops, ins2); |
aeb1f26b MM |
221 | State.ins_type = INS_RIGHT_COND_EXE; |
222 | ins_type_counters[ (int)State.ins_type ]++; | |
d70b4d42 MH |
223 | (h2->ops->func)(); |
224 | } | |
aeb1f26b MM |
225 | else |
226 | ins_type_counters[ (int)INS_COND_FALSE ]++; | |
2934d1c9 MH |
227 | } |
228 | else if (h2->ops->exec_type == PARONLY) | |
229 | { | |
d70b4d42 | 230 | get_operands (h2->ops, ins2); |
aeb1f26b | 231 | State.ins_type = INS_RIGHT_COND_TEST; |
7eebfc62 | 232 | ins_type_counters[ (int)State.ins_type ]++; |
2934d1c9 MH |
233 | (h2->ops->func)(); |
234 | if (State.exe) | |
d70b4d42 | 235 | { |
aeb1f26b | 236 | ins_type_counters[ (int)INS_COND_TRUE ]++; |
d70b4d42 | 237 | get_operands (h1->ops, ins1); |
aeb1f26b MM |
238 | State.ins_type = INS_LEFT_COND_EXE; |
239 | ins_type_counters[ (int)State.ins_type ]++; | |
d70b4d42 MH |
240 | (h1->ops->func)(); |
241 | } | |
aeb1f26b MM |
242 | else |
243 | ins_type_counters[ (int)INS_COND_FALSE ]++; | |
2934d1c9 MH |
244 | } |
245 | else | |
246 | { | |
d70b4d42 | 247 | get_operands (h1->ops, ins1); |
87178dbd | 248 | State.ins_type = INS_LEFT_PARALLEL; |
7eebfc62 | 249 | ins_type_counters[ (int)State.ins_type ]++; |
2934d1c9 | 250 | (h1->ops->func)(); |
57bc1a72 MM |
251 | if (!State.exception) |
252 | { | |
253 | get_operands (h2->ops, ins2); | |
254 | State.ins_type = INS_RIGHT_PARALLEL; | |
255 | ins_type_counters[ (int)State.ins_type ]++; | |
256 | (h2->ops->func)(); | |
257 | } | |
2934d1c9 MH |
258 | } |
259 | } | |
260 | ||
aeb1f26b MM |
261 | static char * |
262 | add_commas(buf, sizeof_buf, value) | |
263 | char *buf; | |
264 | int sizeof_buf; | |
265 | unsigned long value; | |
266 | { | |
267 | int comma = 3; | |
268 | char *endbuf = buf + sizeof_buf - 1; | |
269 | ||
270 | *--endbuf = '\0'; | |
271 | do { | |
272 | if (comma-- == 0) | |
273 | { | |
274 | *--endbuf = ','; | |
275 | comma = 2; | |
276 | } | |
277 | ||
278 | *--endbuf = (value % 10) + '0'; | |
279 | } while ((value /= 10) != 0); | |
280 | ||
281 | return endbuf; | |
282 | } | |
2934d1c9 MH |
283 | |
284 | void | |
285 | sim_size (power) | |
286 | int power; | |
287 | ||
288 | { | |
c422ecc7 MH |
289 | int i; |
290 | ||
2934d1c9 MH |
291 | if (State.imem) |
292 | { | |
c422ecc7 MH |
293 | for (i=0;i<128;i++) |
294 | { | |
295 | if (State.umem[i]) | |
296 | { | |
297 | free (State.umem[i]); | |
298 | State.umem[i] = NULL; | |
299 | } | |
300 | } | |
2934d1c9 MH |
301 | free (State.imem); |
302 | free (State.dmem); | |
303 | } | |
304 | ||
305 | State.imem = (uint8 *)calloc(1,1<<IMEM_SIZE); | |
306 | State.dmem = (uint8 *)calloc(1,1<<DMEM_SIZE); | |
c422ecc7 MH |
307 | for (i=1;i<127;i++) |
308 | State.umem[i] = NULL; | |
309 | State.umem[0] = (uint8 *)calloc(1,1<<UMEM_SIZE); | |
310 | State.umem[1] = (uint8 *)calloc(1,1<<UMEM_SIZE); | |
311 | State.umem[2] = (uint8 *)calloc(1,1<<UMEM_SIZE); | |
312 | State.umem[127] = (uint8 *)calloc(1,1<<UMEM_SIZE); | |
313 | if (!State.imem || !State.dmem || !State.umem[0] || !State.umem[1] || !State.umem[2] || !State.umem[127] ) | |
2934d1c9 | 314 | { |
7eebfc62 | 315 | (*d10v_callback->printf_filtered) (d10v_callback, "Memory allocation failed.\n"); |
2934d1c9 MH |
316 | exit(1); |
317 | } | |
c422ecc7 MH |
318 | |
319 | SET_IMAP0(0x1000); | |
320 | SET_IMAP1(0x1000); | |
321 | SET_DMAP(0); | |
57bc1a72 | 322 | |
7eebfc62 MM |
323 | #ifdef DEBUG |
324 | if ((d10v_debug & DEBUG_MEMSIZE) != 0) | |
325 | { | |
aeb1f26b MM |
326 | char buffer[20]; |
327 | (*d10v_callback->printf_filtered) (d10v_callback, | |
328 | "Allocated %s bytes instruction memory and\n", | |
329 | add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE))); | |
330 | ||
331 | (*d10v_callback->printf_filtered) (d10v_callback, " %s bytes data memory.\n", | |
332 | add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE))); | |
7eebfc62 | 333 | } |
87178dbd | 334 | #endif |
2934d1c9 MH |
335 | } |
336 | ||
337 | static void | |
338 | init_system () | |
339 | { | |
340 | if (!State.imem) | |
341 | sim_size(1); | |
342 | } | |
343 | ||
c422ecc7 MH |
344 | static int |
345 | xfer_mem (addr, buffer, size, write) | |
2934d1c9 MH |
346 | SIM_ADDR addr; |
347 | unsigned char *buffer; | |
348 | int size; | |
c422ecc7 | 349 | int write; |
2934d1c9 | 350 | { |
c422ecc7 MH |
351 | if (!State.imem) |
352 | init_system (); | |
2934d1c9 | 353 | |
57bc1a72 MM |
354 | #ifdef DEBUG |
355 | if ((d10v_debug & DEBUG_INSTRUCTION) != 0) | |
c422ecc7 MH |
356 | { |
357 | if (write) | |
358 | (*d10v_callback->printf_filtered) (d10v_callback, "sim_write %d bytes to 0x%x\n", size, addr); | |
359 | else | |
360 | (*d10v_callback->printf_filtered) (d10v_callback, "sim_read %d bytes from 0x%x\n", size, addr); | |
361 | } | |
57bc1a72 MM |
362 | #endif |
363 | ||
c422ecc7 MH |
364 | /* to access data, we use the following mapping */ |
365 | /* 0x01000000 - 0x0103ffff : instruction memory */ | |
366 | /* 0x02000000 - 0x0200ffff : data memory */ | |
04885cc3 | 367 | /* 0x00000000 - 0x00ffffff : unified memory */ |
57bc1a72 | 368 | |
04885cc3 | 369 | if ( (addr & 0x03000000) == 0) |
c422ecc7 MH |
370 | { |
371 | /* UNIFIED MEMORY */ | |
372 | int segment; | |
c422ecc7 MH |
373 | segment = addr >> UMEM_SIZE; |
374 | addr &= 0x1ffff; | |
375 | if (!State.umem[segment]) | |
04885cc3 DE |
376 | { |
377 | #ifdef DEBUG | |
378 | (*d10v_callback->printf_filtered) (d10v_callback,"Allocating %s bytes unified memory to region %d\n", | |
379 | add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)), segment); | |
380 | #endif | |
381 | State.umem[segment] = (uint8 *)calloc(1,1<<UMEM_SIZE); | |
382 | } | |
c422ecc7 MH |
383 | if (!State.umem[segment]) |
384 | { | |
385 | (*d10v_callback->printf_filtered) (d10v_callback, "Memory allocation failed.\n"); | |
386 | exit(1); | |
387 | } | |
c422ecc7 MH |
388 | /* FIXME: need to check size and read/write multiple segments if necessary */ |
389 | if (write) | |
04885cc3 | 390 | memcpy (State.umem[segment]+addr, buffer, size) ; |
c422ecc7 MH |
391 | else |
392 | memcpy (buffer, State.umem[segment]+addr, size); | |
393 | } | |
394 | else if ( (addr & 0x03000000) == 0x02000000) | |
395 | { | |
396 | /* DATA MEMORY */ | |
397 | addr &= ~0x02000000; | |
398 | if (size > (1<<(DMEM_SIZE-1))) | |
399 | { | |
400 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: data section is only %d bytes.\n",1<<(DMEM_SIZE-1)); | |
401 | exit(1); | |
402 | } | |
403 | if (write) | |
404 | memcpy (State.dmem+addr, buffer, size); | |
405 | else | |
406 | memcpy (buffer, State.dmem+addr, size); | |
407 | } | |
408 | else if ( (addr & 0x03000000) == 0x01000000) | |
409 | { | |
410 | /* INSTRUCTION MEMORY */ | |
411 | addr &= ~0x01000000; | |
412 | if (size > (1<<IMEM_SIZE)) | |
413 | { | |
414 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: inst section is only %d bytes.\n",1<<IMEM_SIZE); | |
415 | exit(1); | |
416 | } | |
417 | if (write) | |
418 | memcpy (State.imem+addr, buffer, size); | |
419 | else | |
420 | memcpy (buffer, State.imem+addr, size); | |
421 | } | |
422 | else if (write) | |
423 | { | |
424 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: address 0x%x is not in valid range\n",addr); | |
425 | (*d10v_callback->printf_filtered) (d10v_callback, "Instruction addresses start at 0x01000000\n"); | |
426 | (*d10v_callback->printf_filtered) (d10v_callback, "Data addresses start at 0x02000000\n"); | |
04885cc3 | 427 | (*d10v_callback->printf_filtered) (d10v_callback, "Unified addresses start at 0x00000000\n"); |
c422ecc7 MH |
428 | exit(1); |
429 | } | |
430 | else | |
431 | return 0; | |
57bc1a72 | 432 | |
2934d1c9 MH |
433 | return size; |
434 | } | |
435 | ||
c422ecc7 MH |
436 | |
437 | int | |
04885cc3 DE |
438 | sim_write (sd, addr, buffer, size) |
439 | SIM_DESC sd; | |
c422ecc7 MH |
440 | SIM_ADDR addr; |
441 | unsigned char *buffer; | |
442 | int size; | |
443 | { | |
444 | return xfer_mem( addr, buffer, size, 1); | |
445 | } | |
446 | ||
447 | int | |
04885cc3 DE |
448 | sim_read (sd, addr, buffer, size) |
449 | SIM_DESC sd; | |
c422ecc7 MH |
450 | SIM_ADDR addr; |
451 | unsigned char *buffer; | |
452 | int size; | |
453 | { | |
454 | return xfer_mem( addr, buffer, size, 0); | |
455 | } | |
456 | ||
457 | ||
04885cc3 DE |
458 | SIM_DESC |
459 | sim_open (kind, argv) | |
460 | SIM_OPEN_KIND kind; | |
461 | char **argv; | |
2934d1c9 MH |
462 | { |
463 | struct simops *s; | |
aeb1f26b | 464 | struct hash_entry *h; |
1eaaf305 | 465 | static int init_p = 0; |
04885cc3 DE |
466 | char **p; |
467 | ||
468 | sim_kind = kind; | |
469 | myname = argv[0]; | |
1eaaf305 | 470 | |
04885cc3 | 471 | for (p = argv + 1; *p; ++p) |
1eaaf305 | 472 | { |
04885cc3 DE |
473 | /* Ignore endian specification. */ |
474 | if (strcmp (*p, "-E") == 0) | |
475 | ++p; | |
476 | else | |
1eaaf305 | 477 | #ifdef DEBUG |
04885cc3 | 478 | if (strcmp (*p, "-t") == 0) |
1eaaf305 MM |
479 | d10v_debug = DEBUG; |
480 | else | |
481 | #endif | |
04885cc3 | 482 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unsupported option(s): %s\n",*p); |
1eaaf305 | 483 | } |
c422ecc7 | 484 | |
2934d1c9 | 485 | /* put all the opcodes in the hash table */ |
1eaaf305 | 486 | if (!init_p++) |
2934d1c9 | 487 | { |
1eaaf305 | 488 | for (s = Simops; s->func; s++) |
2934d1c9 | 489 | { |
1eaaf305 MM |
490 | h = &hash_table[hash(s->opcode,s->format)]; |
491 | ||
492 | /* go to the last entry in the chain */ | |
493 | while (h->next) | |
494 | h = h->next; | |
495 | ||
496 | if (h->ops) | |
497 | { | |
04885cc3 DE |
498 | h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry)); |
499 | if (!h->next) | |
500 | perror ("malloc failure"); | |
501 | ||
1eaaf305 MM |
502 | h = h->next; |
503 | } | |
504 | h->ops = s; | |
505 | h->mask = s->mask; | |
506 | h->opcode = s->opcode; | |
cee402dd | 507 | h->size = s->is_long; |
2934d1c9 | 508 | } |
2934d1c9 | 509 | } |
04885cc3 DE |
510 | |
511 | /* Fudge our descriptor. */ | |
512 | return (SIM_DESC) 1; | |
2934d1c9 MH |
513 | } |
514 | ||
515 | ||
516 | void | |
04885cc3 DE |
517 | sim_close (sd, quitting) |
518 | SIM_DESC sd; | |
2934d1c9 MH |
519 | int quitting; |
520 | { | |
04885cc3 DE |
521 | if (prog_bfd != NULL && prog_bfd_was_opened_p) |
522 | bfd_close (prog_bfd); | |
2934d1c9 MH |
523 | } |
524 | ||
525 | void | |
526 | sim_set_profile (n) | |
527 | int n; | |
528 | { | |
7eebfc62 | 529 | (*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile %d\n",n); |
2934d1c9 MH |
530 | } |
531 | ||
532 | void | |
533 | sim_set_profile_size (n) | |
534 | int n; | |
535 | { | |
7eebfc62 | 536 | (*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile_size %d\n",n); |
2934d1c9 MH |
537 | } |
538 | ||
c422ecc7 MH |
539 | |
540 | uint8 * | |
541 | dmem_addr( addr ) | |
542 | uint32 addr; | |
543 | { | |
544 | int seg; | |
545 | ||
546 | addr &= 0xffff; | |
547 | ||
548 | if (addr > 0xbfff) | |
549 | { | |
550 | if ( (addr & 0xfff0) != 0xff00) | |
04885cc3 DE |
551 | { |
552 | (*d10v_callback->printf_filtered) (d10v_callback, "Data address 0x%lx is in I/O space, pc = 0x%lx.\n", | |
553 | (long)addr, (long)decode_pc ()); | |
554 | State.exception = SIGBUS; | |
555 | } | |
556 | ||
c422ecc7 MH |
557 | return State.dmem + addr; |
558 | } | |
559 | ||
560 | if (addr > 0x7fff) | |
561 | { | |
562 | if (DMAP & 0x1000) | |
563 | { | |
564 | /* instruction memory */ | |
565 | return (DMAP & 0xf) * 0x4000 + State.imem; | |
566 | } | |
567 | /* unified memory */ | |
568 | /* this is ugly because we allocate unified memory in 128K segments and */ | |
569 | /* dmap addresses 16k segments */ | |
cee402dd | 570 | seg = (DMAP & 0x3ff) >> 3; |
c422ecc7 MH |
571 | if (State.umem[seg] == NULL) |
572 | { | |
b30cdd35 MM |
573 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unified memory region %d unmapped, pc = 0x%lx\n", |
574 | seg, (long)decode_pc ()); | |
04885cc3 | 575 | State.exception = SIGBUS; |
c422ecc7 | 576 | } |
cee402dd | 577 | return State.umem[seg] + (DMAP & 7) * 0x4000; |
c422ecc7 MH |
578 | } |
579 | ||
580 | return State.dmem + addr; | |
581 | } | |
582 | ||
583 | ||
584 | static uint8 * | |
585 | pc_addr() | |
586 | { | |
587 | uint32 pc = ((uint32)PC) << 2; | |
588 | uint16 imap; | |
589 | ||
590 | if (pc & 0x20000) | |
591 | imap = IMAP1; | |
592 | else | |
593 | imap = IMAP0; | |
594 | ||
595 | if (imap & 0x1000) | |
596 | return State.imem + pc; | |
597 | ||
598 | if (State.umem[imap & 0xff] == NULL) | |
599 | { | |
b30cdd35 MM |
600 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unified memory region %d unmapped, pc = 0x%lx\n", |
601 | imap & 0xff, (long)PC); | |
04885cc3 | 602 | State.exception = SIGBUS; |
c422ecc7 MH |
603 | return 0; |
604 | } | |
605 | ||
606 | return State.umem[imap & 0xff] + pc; | |
607 | } | |
608 | ||
609 | ||
cee402dd DE |
610 | static int stop_simulator; |
611 | ||
612 | static void | |
613 | sim_ctrl_c() | |
614 | { | |
615 | stop_simulator = 1; | |
616 | } | |
617 | ||
618 | ||
619 | /* Run (or resume) the program. */ | |
2934d1c9 | 620 | void |
04885cc3 DE |
621 | sim_resume (sd, step, siggnal) |
622 | SIM_DESC sd; | |
2934d1c9 MH |
623 | int step, siggnal; |
624 | { | |
cee402dd | 625 | void (*prev) (); |
2934d1c9 | 626 | uint32 inst; |
2934d1c9 | 627 | |
7eebfc62 | 628 | /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */ |
eca43eb1 | 629 | State.exception = 0; |
cee402dd DE |
630 | prev = signal(SIGINT, sim_ctrl_c); |
631 | stop_simulator = step; | |
632 | ||
aeb1f26b MM |
633 | do |
634 | { | |
c422ecc7 | 635 | inst = get_longword( pc_addr() ); |
cee402dd | 636 | State.pc_changed = 0; |
c422ecc7 MH |
637 | ins_type_counters[ (int)INS_CYCLES ]++; |
638 | switch (inst & 0xC0000000) | |
aeb1f26b | 639 | { |
c422ecc7 MH |
640 | case 0xC0000000: |
641 | /* long instruction */ | |
642 | do_long (inst & 0x3FFFFFFF); | |
643 | break; | |
644 | case 0x80000000: | |
645 | /* R -> L */ | |
646 | do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15, 0); | |
647 | break; | |
648 | case 0x40000000: | |
649 | /* L -> R */ | |
650 | do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF, 1); | |
651 | break; | |
652 | case 0: | |
653 | do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF); | |
654 | break; | |
aeb1f26b | 655 | } |
c422ecc7 MH |
656 | |
657 | if (State.RP && PC == RPT_E) | |
aeb1f26b | 658 | { |
c422ecc7 MH |
659 | RPT_C -= 1; |
660 | if (RPT_C == 0) | |
661 | State.RP = 0; | |
662 | else | |
663 | PC = RPT_S; | |
aeb1f26b | 664 | } |
cee402dd | 665 | else if (!State.pc_changed) |
c422ecc7 | 666 | PC++; |
aeb1f26b | 667 | } |
cee402dd | 668 | while ( !State.exception && !stop_simulator); |
c422ecc7 | 669 | |
aeb1f26b MM |
670 | if (step && !State.exception) |
671 | State.exception = SIGTRAP; | |
cee402dd DE |
672 | |
673 | signal(SIGINT, prev); | |
2934d1c9 MH |
674 | } |
675 | ||
676 | int | |
04885cc3 DE |
677 | sim_trace (sd) |
678 | SIM_DESC sd; | |
2934d1c9 | 679 | { |
7eebfc62 MM |
680 | #ifdef DEBUG |
681 | d10v_debug = DEBUG; | |
682 | #endif | |
04885cc3 | 683 | sim_resume (sd, 0, 0); |
7eebfc62 | 684 | return 1; |
2934d1c9 MH |
685 | } |
686 | ||
687 | void | |
04885cc3 DE |
688 | sim_info (sd, verbose) |
689 | SIM_DESC sd; | |
2934d1c9 MH |
690 | int verbose; |
691 | { | |
aeb1f26b MM |
692 | char buf1[40]; |
693 | char buf2[40]; | |
694 | char buf3[40]; | |
695 | char buf4[40]; | |
696 | char buf5[40]; | |
697 | unsigned long left = ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_COND_EXE ]; | |
698 | unsigned long left_nops = ins_type_counters[ (int)INS_LEFT_NOPS ]; | |
699 | unsigned long left_parallel = ins_type_counters[ (int)INS_LEFT_PARALLEL ]; | |
700 | unsigned long left_cond = ins_type_counters[ (int)INS_LEFT_COND_TEST ]; | |
701 | unsigned long left_total = left + left_parallel + left_cond + left_nops; | |
702 | ||
703 | unsigned long right = ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_COND_EXE ]; | |
704 | unsigned long right_nops = ins_type_counters[ (int)INS_RIGHT_NOPS ]; | |
705 | unsigned long right_parallel = ins_type_counters[ (int)INS_RIGHT_PARALLEL ]; | |
706 | unsigned long right_cond = ins_type_counters[ (int)INS_RIGHT_COND_TEST ]; | |
707 | unsigned long right_total = right + right_parallel + right_cond + right_nops; | |
708 | ||
709 | unsigned long unknown = ins_type_counters[ (int)INS_UNKNOWN ]; | |
710 | unsigned long ins_long = ins_type_counters[ (int)INS_LONG ]; | |
c422ecc7 MH |
711 | unsigned long parallel = ins_type_counters[ (int)INS_PARALLEL ]; |
712 | unsigned long leftright = ins_type_counters[ (int)INS_LEFTRIGHT ]; | |
713 | unsigned long rightleft = ins_type_counters[ (int)INS_RIGHTLEFT ]; | |
aeb1f26b MM |
714 | unsigned long cond_true = ins_type_counters[ (int)INS_COND_TRUE ]; |
715 | unsigned long cond_false = ins_type_counters[ (int)INS_COND_FALSE ]; | |
c422ecc7 | 716 | unsigned long cond_jump = ins_type_counters[ (int)INS_COND_JUMP ]; |
aeb1f26b MM |
717 | unsigned long cycles = ins_type_counters[ (int)INS_CYCLES ]; |
718 | unsigned long total = (unknown + left_total + right_total + ins_long); | |
719 | ||
720 | int size = strlen (add_commas (buf1, sizeof (buf1), total)); | |
721 | int parallel_size = strlen (add_commas (buf1, sizeof (buf1), | |
722 | (left_parallel > right_parallel) ? left_parallel : right_parallel)); | |
723 | int cond_size = strlen (add_commas (buf1, sizeof (buf1), (left_cond > right_cond) ? left_cond : right_cond)); | |
724 | int nop_size = strlen (add_commas (buf1, sizeof (buf1), (left_nops > right_nops) ? left_nops : right_nops)); | |
725 | int normal_size = strlen (add_commas (buf1, sizeof (buf1), (left > right) ? left : right)); | |
726 | ||
727 | (*d10v_callback->printf_filtered) (d10v_callback, | |
c422ecc7 | 728 | "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n", |
aeb1f26b MM |
729 | size, add_commas (buf1, sizeof (buf1), left_total), |
730 | normal_size, add_commas (buf2, sizeof (buf2), left), | |
731 | parallel_size, add_commas (buf3, sizeof (buf3), left_parallel), | |
732 | cond_size, add_commas (buf4, sizeof (buf4), left_cond), | |
733 | nop_size, add_commas (buf5, sizeof (buf5), left_nops)); | |
734 | ||
735 | (*d10v_callback->printf_filtered) (d10v_callback, | |
c422ecc7 | 736 | "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n", |
aeb1f26b MM |
737 | size, add_commas (buf1, sizeof (buf1), right_total), |
738 | normal_size, add_commas (buf2, sizeof (buf2), right), | |
739 | parallel_size, add_commas (buf3, sizeof (buf3), right_parallel), | |
740 | cond_size, add_commas (buf4, sizeof (buf4), right_cond), | |
741 | nop_size, add_commas (buf5, sizeof (buf5), right_nops)); | |
742 | ||
c422ecc7 MH |
743 | if (ins_long) |
744 | (*d10v_callback->printf_filtered) (d10v_callback, | |
745 | "executed %*s long instruction(s)\n", | |
746 | size, add_commas (buf1, sizeof (buf1), ins_long)); | |
747 | ||
748 | if (parallel) | |
749 | (*d10v_callback->printf_filtered) (d10v_callback, | |
750 | "executed %*s parallel instruction(s)\n", | |
751 | size, add_commas (buf1, sizeof (buf1), parallel)); | |
752 | ||
753 | if (leftright) | |
754 | (*d10v_callback->printf_filtered) (d10v_callback, | |
755 | "executed %*s instruction(s) encoded L->R\n", | |
756 | size, add_commas (buf1, sizeof (buf1), leftright)); | |
757 | ||
758 | if (rightleft) | |
759 | (*d10v_callback->printf_filtered) (d10v_callback, | |
760 | "executed %*s instruction(s) encoded R->L\n", | |
761 | size, add_commas (buf1, sizeof (buf1), rightleft)); | |
7eebfc62 | 762 | |
aeb1f26b MM |
763 | if (unknown) |
764 | (*d10v_callback->printf_filtered) (d10v_callback, | |
c422ecc7 | 765 | "executed %*s unknown instruction(s)\n", |
aeb1f26b | 766 | size, add_commas (buf1, sizeof (buf1), unknown)); |
7eebfc62 | 767 | |
c422ecc7 MH |
768 | if (cond_true) |
769 | (*d10v_callback->printf_filtered) (d10v_callback, | |
770 | "executed %*s instruction(s) due to EXExxx condition being true\n", | |
771 | size, add_commas (buf1, sizeof (buf1), cond_true)); | |
7eebfc62 | 772 | |
c422ecc7 MH |
773 | if (cond_false) |
774 | (*d10v_callback->printf_filtered) (d10v_callback, | |
775 | "skipped %*s instruction(s) due to EXExxx condition being false\n", | |
776 | size, add_commas (buf1, sizeof (buf1), cond_false)); | |
777 | ||
778 | if (cond_jump) | |
779 | (*d10v_callback->printf_filtered) (d10v_callback, | |
780 | "skipped %*s instruction(s) due to conditional branch succeeding\n", | |
781 | size, add_commas (buf1, sizeof (buf1), cond_jump)); | |
7eebfc62 MM |
782 | |
783 | (*d10v_callback->printf_filtered) (d10v_callback, | |
c422ecc7 | 784 | "executed %*s cycle(s)\n", |
aeb1f26b | 785 | size, add_commas (buf1, sizeof (buf1), cycles)); |
7eebfc62 MM |
786 | |
787 | (*d10v_callback->printf_filtered) (d10v_callback, | |
aeb1f26b MM |
788 | "executed %*s total instructions\n", |
789 | size, add_commas (buf1, sizeof (buf1), total)); | |
2934d1c9 MH |
790 | } |
791 | ||
04885cc3 DE |
792 | SIM_RC |
793 | sim_create_inferior (sd, argv, env) | |
794 | SIM_DESC sd; | |
2934d1c9 MH |
795 | char **argv; |
796 | char **env; | |
797 | { | |
7eebfc62 MM |
798 | #ifdef DEBUG |
799 | if (d10v_debug) | |
800 | (*d10v_callback->printf_filtered) (d10v_callback, "sim_create_inferior: PC=0x%x\n", start_address); | |
801 | #endif | |
c422ecc7 | 802 | |
57bc1a72 | 803 | /* reset all state information */ |
c422ecc7 MH |
804 | memset (&State.regs, 0, (int)&State.imem - (int)&State.regs[0]); |
805 | ||
57bc1a72 | 806 | /* set PC */ |
2934d1c9 | 807 | PC = start_address >> 2; |
c422ecc7 MH |
808 | |
809 | /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board */ | |
810 | /* resets imap0 and imap1 to 0x1000. */ | |
811 | ||
812 | SET_IMAP0(0x1000); | |
813 | SET_IMAP1(0x1000); | |
814 | SET_DMAP(0); | |
04885cc3 DE |
815 | |
816 | return SIM_RC_OK; | |
2934d1c9 MH |
817 | } |
818 | ||
819 | ||
820 | void | |
04885cc3 DE |
821 | sim_kill (sd) |
822 | SIM_DESC sd; | |
2934d1c9 MH |
823 | { |
824 | /* nothing to do */ | |
825 | } | |
826 | ||
827 | void | |
04885cc3 DE |
828 | sim_set_callbacks (sd, p) |
829 | SIM_DESC sd; | |
2934d1c9 MH |
830 | host_callback *p; |
831 | { | |
87178dbd | 832 | d10v_callback = p; |
2934d1c9 MH |
833 | } |
834 | ||
835 | void | |
04885cc3 DE |
836 | sim_stop_reason (sd, reason, sigrc) |
837 | SIM_DESC sd; | |
2934d1c9 MH |
838 | enum sim_stop *reason; |
839 | int *sigrc; | |
840 | { | |
7eebfc62 | 841 | /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */ |
d70b4d42 | 842 | |
a49a15ad | 843 | switch (State.exception) |
d70b4d42 | 844 | { |
a49a15ad | 845 | case SIG_D10V_STOP: /* stop instruction */ |
d70b4d42 | 846 | *reason = sim_exited; |
a49a15ad MM |
847 | *sigrc = 0; |
848 | break; | |
849 | ||
850 | case SIG_D10V_EXIT: /* exit trap */ | |
851 | *reason = sim_exited; | |
852 | *sigrc = State.regs[2]; | |
853 | break; | |
854 | ||
855 | default: /* some signal */ | |
d70b4d42 MH |
856 | *reason = sim_stopped; |
857 | *sigrc = State.exception; | |
a49a15ad | 858 | break; |
d70b4d42 MH |
859 | } |
860 | } | |
861 | ||
862 | void | |
04885cc3 DE |
863 | sim_fetch_register (sd, rn, memory) |
864 | SIM_DESC sd; | |
d70b4d42 MH |
865 | int rn; |
866 | unsigned char *memory; | |
867 | { | |
c422ecc7 MH |
868 | if (!State.imem) |
869 | init_system(); | |
870 | ||
871 | if (rn > 34) | |
5c839c67 | 872 | WRITE_64 (memory, State.a[rn-35]); |
c422ecc7 MH |
873 | else if (rn == 32) |
874 | WRITE_16 (memory, IMAP0); | |
875 | else if (rn == 33) | |
876 | WRITE_16 (memory, IMAP1); | |
877 | else if (rn == 34) | |
878 | WRITE_16 (memory, DMAP); | |
d70b4d42 | 879 | else |
c422ecc7 | 880 | WRITE_16 (memory, State.regs[rn]); |
d70b4d42 MH |
881 | } |
882 | ||
883 | void | |
04885cc3 DE |
884 | sim_store_register (sd, rn, memory) |
885 | SIM_DESC sd; | |
d70b4d42 MH |
886 | int rn; |
887 | unsigned char *memory; | |
888 | { | |
c422ecc7 MH |
889 | if (!State.imem) |
890 | init_system(); | |
891 | ||
892 | if (rn > 34) | |
5c839c67 | 893 | State.a[rn-35] = READ_64 (memory) & MASK40; |
c422ecc7 MH |
894 | else if (rn == 34) |
895 | SET_DMAP( READ_16(memory) ); | |
896 | else if (rn == 33) | |
897 | SET_IMAP1( READ_16(memory) ); | |
898 | else if (rn == 32) | |
899 | SET_IMAP0( READ_16(memory) ); | |
d70b4d42 | 900 | else |
c422ecc7 | 901 | State.regs[rn]= READ_16 (memory); |
2934d1c9 | 902 | } |
d70b4d42 | 903 | |
d70b4d42 MH |
904 | |
905 | void | |
04885cc3 DE |
906 | sim_do_command (sd, cmd) |
907 | SIM_DESC sd; | |
d70b4d42 MH |
908 | char *cmd; |
909 | { | |
7eebfc62 | 910 | (*d10v_callback->printf_filtered) (d10v_callback, "sim_do_command: %s\n",cmd); |
d70b4d42 MH |
911 | } |
912 | ||
04885cc3 DE |
913 | SIM_RC |
914 | sim_load (sd, prog, abfd, from_tty) | |
915 | SIM_DESC sd; | |
d70b4d42 | 916 | char *prog; |
04885cc3 | 917 | bfd *abfd; |
d70b4d42 MH |
918 | int from_tty; |
919 | { | |
04885cc3 DE |
920 | extern bfd *sim_load_file (); /* ??? Don't know where this should live. */ |
921 | ||
922 | if (prog_bfd != NULL && prog_bfd_was_opened_p) | |
923 | bfd_close (prog_bfd); | |
924 | prog_bfd = sim_load_file (sd, myname, d10v_callback, prog, abfd, | |
925 | sim_kind == SIM_OPEN_DEBUG); | |
926 | if (prog_bfd == NULL) | |
927 | return SIM_RC_FAIL; | |
928 | start_address = bfd_get_start_address (prog_bfd); | |
929 | prog_bfd_was_opened_p = abfd == NULL; | |
930 | return SIM_RC_OK; | |
d70b4d42 | 931 | } |